Hi All,
I am using sniper to model contention effects between programs running on a tiled architecture. I have a few quick questions about configurations:
I have been having trouble setting up my DRAM controllers. I am trying to simulate a system where the LLC (in my case the L2) is shared across all cores in my mesh, and there are a few memory controllers placed throughout the mesh (e.g. at the corners). Unfortunately, sniper is complaining that I cannot place memory controllers at positions other than the master node of a mesh. Is this normal/expected behavior, and if so, is there a way to get around this limitation (in order to have more than one memory controller--as the memory controller is currently limiting simulated performance, and I don't see the logic behind this limitation)?
Also, in the configuration file, we have the option called: "perf_model/l2_cache/shared_cores." How does this option work? Is it correct to understand that "shared_cores = N" means that N cores (across different tiles) have a logically shared L2 cache (each core having a slice of the overall cache)?
Thanks,
Stefan W.