Memory Contoller and Cache Sharing Configurations

[Stefan W.]

Hi All,

I am using sniper to model contention effects between programs running on a tiled architecture. I have a few quick questions about configurations:

I have been having trouble setting up my DRAM controllers. I am trying to simulate a system where the LLC (in my case the L2) is shared across all cores in my mesh, and there are a few memory controllers placed throughout the mesh (e.g. at the corners). Unfortunately, sniper is complaining that I cannot place memory controllers at positions other than the master node of a mesh. Is this normal/expected behavior, and if so, is there a way to get around this limitation (in order to have more than one memory controller--as the memory controller is currently limiting simulated performance, and I don't see the logic behind this limitation)?

Also, in the configuration file, we have the option called: "perf_model/l2_cache/shared_cores." How does this option work? Is it correct to understand that "shared_cores = N" means that N cores (across different tiles) have a logically shared L2 cache (each core having a slice of the overall cache)?

Thanks,

Stefan W.

[ahmad sedigh]

Hi Stefan

I don't know the answer for first question, but for second question the answer is YES. add this to your Makefile and see the topology generated by Sniper in current working directory.

../../tools/gen_topology.py

for example using "-g perf_model/l2_cache/shared_cores = 2" shares L2 cache with two cores even if L2 is not the LLC.

[Zilmarij Iqbal]

Hi Ahmad,

As you indicated in your previous email, the ../../shared-cores metric divides the cache to be shared by the specified number of cores. I want to find out how the cache is distributed after sharing - is it banked with each core and neighboring four of them share each other's slices; or is it just logically divided into chunks where each chunk is shared by four neighboring cores?

Further, are the cores sharing the cache consecutively placed in the mesh, or it is just to specify the maximum number of sharing cores at one time?

Thanks,

Zilmarij Iqbal

[ahmad sedigh]

Hi Zilmarij,

I am sorry that i don't know the exact answer to your questions but i assume that it is banked and they are placed in the mesh.

It would be appreciated if you share your experience alongside these questions.

Best Regards

Ahmad

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[shail...@gmail.com]

Hi Stefan,

I also do not understand the logic behind this limitation of Sniper --- "Memory controllers can only be placed at master node of shared cache". I would also want to share the last-level cache across all cores and at the same time have multiple memory controllers. Were you able to find a work-around to this limitation?

Thanks,

Shailja

[ahmad sedigh]

Hi  Shailja,

I see that your message is not directed to me but i would like to say that by looking into any config files for instance sim.cfg you can see that there is an option which seems like number of shared cores under the configs of L3 cache. By using the mentioned option in simulation command, you might be able to implement your aforementioned desired model. 

Ahmad

[Zilmarij Iqbal]

UPDATE: The shared LLC is banked physically at each core in mesh architecture, as can be visualised using the gen_topology script in tools.

Zilmarij Iqbal

[Joy Dong]

Hi Shail, 

I have some problem here. How did you managed to model such a CPU with unified L3 cache and multiple memory controllers at the same time? 

Joy