Perfect Cache in Sniper

[Ramyad Hadidi]

Hello,

What is the implementation of perfect cache in Sniper? How a perfect cache differs from a normal cache in Sniper?

[Wim Heirman]

Hi,

A perfect cache always returns a hit (in some definitions perfect caches can still give cold misses, but in Sniper they do not). As for the implementation, you can look at cache_cntlr.cc and search for places where m_perfect is used: what happens is that first a cache lookup is made as normal, and if it's a miss, the line is inserted (without reading it from DRAM / other cache levels). From there on, the same flow as for cache hits is followed.

Regards,

Wim

On 11 November 2014 17:44, Ramyad Hadidi <ramyad...@gmail.com> wrote:

Hello,

What is the implementation of perfect cache in Sniper? How a perfect cache differs from a normal cache in Sniper?

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[Newton]

                                 CPI       Time
  base                      0.25     40.40%
  depend-int            0.03      4.12%
  depend-branch    0.03      5.07%
  issue-port2            0.05      8.45%
  branch                    0.15     23.87%
  mem-l1d                0.11     17.06%
  other                       0.01      1.02%

  total                        0.62     100.00%

I wanted to get the statics for perfect cache. So, i made L1, L2, L3 caches perfect,
In the sim.out, i am getting 0 misses in L1, L2, L3 caches.
Can you please explain why?

But still in cpistack i am getting cycles consumed in servicing mem-l1d.
I am getting ITLB, DTLB misses. Is there any way to make TLB misses 0, like caches.

[Wim Heirman]

Newton,

You can model a perfect TLB by setting perf_model/dtlb/size=0

Regards,

Wim

[Newton]

Dear Wim,

I am using gainestown.cfg and nehalem.cfg as configurations for my simulations.
I had tried making all caches perfect by setting in the nehalem config file, the
perfect flag set for each cache as shown below for l1_icache

[perf_model/l1_icache]
perfect = true

But i was still getting mem-l1d component in the cpistack. To reduce that you
had suggested to make dtlb size 0 by setting perf_model/dtlb/size = 0 as shown below

[perf_model/dtlb]
size = 0  # 64, Number of D-TLB entries

but my cpi stack still contains mem-l1d component, although i am not getting any L1D
cache miss in sim.out file.
                        CPI       Time
  base                 0.25     18.74%
  depend-int           0.09      6.98%
  depend-fp            0.29     21.46%
  depend-branch        0.03      2.39%
  branch               0.16     12.00%
  mem-l1d              0.51     37.89%
  other                0.01      0.55%

I also tried setting itlb, stlb size to 0 and also tlb penalty to be 0, but still the

issue persisted.

I am sharing both the config files. Can you please help?

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Thanks

Newton

Research Scholar, EE Dept.
IIT Bombay

[Wim Heirman]

Hi Newton,

Even with a perfect L1-D (i.e. one that always returns a hit), its latency is 4 cycles in Sniper's Gainestown model. So if your code does not have enough ILP to overlap this 4-cycle latency, you still expect to see a mem-l1d component.

Regards,

Wim

[Newton]

Thanks Wim. It worked!

In the cfg file, i set the data_access_time & tags_access_time to 0,

to reduce cycles consumed in cache access to 0.

[perf_model/l1_icache]
perfect = true
cache_size = 32
associativity = 4
address_hash = mask
replacement_policy = lru
data_access_time = 0 # made the data access time 0 from 4
tags_access_time = 0 # made the tag access time 0 from 1
perf_model_type = parallel
writethrough = 0
shared_cores = 1