From memory_manager.cc every other object is being initalized(tlb, cache_ctrl for all levels, Dram-cache, Dram-cntrl). Access to memory hierarchy follows coreIntiateMemoryAccess()->processMemFromCore().
processMemFromCore is being called recusively for next level of cache_cntrl and the the end for dram. so upon miss to l1 cache_controller it goes for next l2 cache_cntrl with same recursive function.
i too went too into hadleMessageFromNetwork but felt too complicated for me.