Hi Ahmad,
I don't remember the size of the DRAM chip I used. Probably it was for 4 Gbit chips. What does the 0.17 W that you quote cover exactly?
The value in mcpat.py is the idle power (includes leakage, other static power, and refresh) and is configured as 0.111W per device (mcpat.py line 10). The 4W number you observe includes idle power but also the DDR bus static power (0.022W/device, line 16), for all chips in the system. At 8 chips per DIMM, (.111W+.022W)*8 = 1W per DIMM, and 4 DIMMs per socket (line 22) yields around 4W.
If you configure larger systems, the number of sockets will go up: the default configuration is a quad-core socket, so if you specify -n8 you'll get a two-socket system with two DRAM controllers and 4 DIMMs each which should bring the total idle DRAM power to 8W.
Regards,
Wim