Understanding the SMP architecture

[Neelam Sharma]

Hi,

I want to make the configuration that I am using for my experiments as SMP.

Current topology being used:

But, it appears to me as if it is not SMP because in the sim.out the file I can observe:

i) High idle time for most of the cores

ii) DRAM access latency to be inf  for the same cores

Please confirm if it is SMP architecture?

If not what changes I can make to the above topology to configure it as SMP with two DRAM controllers and a NUCA cache slice with each core.

Command used for sniper:

./run-sniper n 8 -d /results -c gainestown -c nuca-cache -c noc -c prefetcher --roi --viz -/BC  -num_roots 8 ./soc-LiveJournal1.cvgr

Link to the gainestown config file:

https://github.com/Neelam96/sniper-7.2/blob/master/config/gainestown.cfg

Thanks in advance

Thanks and Regards,

Neelam Sharma

M. Tech., Final yr. (RA)

Electronic Systems

Department of Electrical Engineering 

IIT BOMBAY

[Neelam Sharma]

Kindly, reply.

Any help is appreciated because this is a critical understanding that I want to have for my simulations.

Thanks and Regards,

Neelam Sharma

M. Tech., Final yr. (RA)

Electronic Systems

Department of Electrical Engineering 

IIT BOMBAY

[Job]

Hi Neelam,

  The Link to the gainestown config file is broken, can you upload it again?