NUCA cache setup question

[Ganesh Venkatesh]

Hello,

I am modeling a 16 - 64 core system connected via mesh interconnect. If I add a NUCA cache, then how does it distributed amongst these cores. For example, if I add a 16MB NUCA, then, in a 16-core simulation, will it split it up as 1MB chunks where each chunk is placed on a tile? Also, what NUCA does it model -- Static or Dynamic?

Thanks,

Ganesh

[Wim Heirman]

Hi Ganesh,

The size you specify is per slice. Each slice is co-located with a tag
directory (also called dram_directory). For these, you can specify
where they are using perf_model/dram_directory/locations, which is one
of
- llc: one tag directory at each last-level cache location, which is
every perf_model/lX_cache/shared_cores (probably this is 1 if you have
a standard tiled architecture)
- dram: at each dram controller, which in their turn are at select
cores/tiles as determined by perf_model/dram/num_controllers or
perf_model/dram/controllers_interleaving
- interleaved: every N cores with N = perf_model/dram_directory/interleaving

Mapping of addresses to NUCA slices (and tag directories) is done
statically in an interleaved fashion default by cache line. You can
increase the interleaving using the parameter
perf_model/dram_directory/home_lookup_param which defines the number
of bits that the address has to be shifted to the right to get the
home node (modulo the number of nodes) -- the default for this last
parameter is 6 which corresponds to an interleaving of 2^6 = 64 bytes
= 1 cache line.

Regards,
Wim

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[Ganesh Venkatesh]

Couple of quick follow-up questions. Just to recap, I am simulating a tile architecture where each tile has L1, L2, and a slice of the nuca cache.

- Is there an associated energy/power model for the NUCA cache? In mcpat.py, I do not see a nuca entry in the all_items array.

- I see the L1-D.loads-where-nuca-cache entry when I do dumpstats. Is there a way I can differentiate the NUCA accesses to the remote tiles vs local tile?

Thank you for the help in advance.

-Ganesh

[Wim Heirman]

Ganesh,

See attached for an updated mcpat.py file which does include NUCA cache statistics.

There currently is no way to distinguish local from remote NUCA hits. We do support this for DRAM accesses (DRAM_LOCAL versus DRAM_REMOTE), if you look at how that's implemented it should be pretty straightforward to enable the same thing for NUCA as well.

Regards,

Wim

[Abbas Banaiyan]

Hello,

I have the same problem. First, I need to distinguish between local vs remote accesses to shared LLC banks of each tile in a tiled architecture. Second, I need to change the access latency of just one path because I‌ want to add ECC‌ blocks in the critical path of one of them (ex. in the path of local core/L1 to LLC bank). 

Should I‌ do required changes in "processShmemReqFromPrevCache" function in cache_cntlr.cc file?

Any help would be appreciated.

Thanks,

Abbas

[Wim Heirman]

Abbas,

I think you should be able to use the CacheCntlr::getHome(address) function for this. It will return the tile ID of the tag directory and NUCA cache slice corresponding to a given address. If the returned value is not the same as the local tile id (available in the m_master_core_id member), it's a remote NUCA slice.

Regards,

Wim

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[Abbas Banaiyan]

Dear Wim,

Thanks for your very quick answer. Where is the best point to do this checking?

Should I call the CacheCntlr::getHome(address) function for the checking inside the "processShmemReqFromPrevCache" function? what is your suggestion?

Best,

Abbas

[Job]

Hi Abbas and Wim,

I also want to distinguish the local vs remote NUCA slice access that requests from the specified core.

Where and how can i modify in the source code?

Thanks in advance.