RISC-V peripherals / NVM options

[Ernest Seah]

Hi,

   Is there documentation on what end-user capability is available on the RISC-V supervisor?

Firstly, I'm interested in whether there is:-

1) JTAG debug interface that can map/modify end-user 64kx16 NVM.

2) USB Host capability

3) USB Hub on-chip

4) need for external RAM/ROM for the RISC-V, and whether this chews up the ~40 I/O available.

5) RISC-V GPIO for bit-banging serial protocol to user design

Secondly, is dual-port FRAM an option supported by the tools/process? It's not clear from the presentation what the NVM options definitively are. I'd like to figure out die area based on needing 64kx16 bits and am not sure where to start.

Thanks.

Regards,

Ernest

[Tim 'mithro' Ansell]

On Sun, 19 Jul 2020 at 10:53, Ernest Seah <ernes...@gmail.com> wrote:

Hi,

   Is there documentation on what end-user capability is available on the RISC-V supervisor?

Firstly, I'm interested in whether there is:-

1) JTAG debug interface that can map/modify end-user 64kx16 NVM.

The supervisor will load it's program from an external SPI flash. There will be some default programs and you'll be able to also provide your own.

 

2) USB Host capability

3) USB Hub on-chip

There is currently no USB support. I am interested in seeing people create working USB IP here which will lead to future harnesses having a USB interface.

 

4) need for external RAM/ROM for the RISC-V, and whether this chews up the ~40 I/O available.

The current plan is to have ~40 I/O pins for the user (with about 48 in total). The RISC-V harness will have internal RAM and load it via SPI meaning you only lose 4 pins, then you need power and GND pins.

You also have plenty of space to put your own SRAM in your area using OpenRAM.

5) RISC-V GPIO for bit-banging serial protocol to user design

The harness should have plenty of "internal" GPIO pins which can be connected to a user's design. Guidance around this will be released in the near future.

Secondly, is dual-port FRAM an option supported by the tools/process? It's not clear from the presentation what the NVM options definitively are. I'd like to figure out die area based on needing 64kx16 bits and am not sure where to start.

There will be an NVM build space released in the future but someone will need to develop a NVM compatible memory compiler which is able to turn the individual cells into a full blown memory block.

 

Hope that helps,

Tim 'mithro' Ansell

[Sylvain Munaut]

Hi,

> There is currently no USB support. I am interested in seeing people create working USB IP here which will lead to future harnesses having a USB interface.

Definitely something I will be working on.

I have a core (originally written for FPGA and used in several
projects) that I intend to adapt / build for sky130.
It's FS only but it's IMHO quite well suited compared to other
open-source cores :
- Single clock domain and flexible on frequency ( any multiple of 12
MHz, starting at 36 MHz )
- Entirely reconfigurable at run time ( end point config is not fixed
at build time like some other cores )
- Isochronous support
- Spec compliant Error / Retry handling

I also want to work on getting a HS PHY in there but that's obviously
trickier. I'm hoping to have some "tests" ready for the first shuttle.
Probably won't be a working core but just the beginning of a HS PHY
exposing tests signals to the outside so I can test the PHY SERDES
part.

Cheers,

Sylvain

[Ernest Seah]

"The current plan is to have ~40 I/O pins for the user (with about 48 in total). The RISC-V harness will have internal RAM and load it via SPI meaning you only lose 4 pins, then you need power and GND pins."

Thanks Tim. Does that mean that the WLCSP package hasn't been finalized? I'm curious if a 2-layer board would suffice from a break-out standpoint given the low pin-count.

Regards,

Ernest

[Tim 'mithro' Ansell]

The exact style of the WCSP is currently still being explored. The goal is to have 1 trace between the balls on a cheap PCB process.

Sylvain did some drawings that show a 2 layer board should be reasonable for breakout.

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[Ernest Seah]

Does the RISC-V work off an internal RC oscillator or are any pins reserved for a clock source? I need 25MHz and am trying to understand if I can derive that from an existing clock. Thanks.