Hello everyone,
Please see updates for this week.
MPW-2 Silicon Testing
I/O Configuration
We now have one part where we have been able to demonstrate configuring 38 IO’s (all I/O except 1 that has a known conflict). We are now verifying this approach works reliably on other parts.
Please see the video link with the demonstration…
The IO configuration depends on characterizing the hold violations for a particular chip. We are automating the routine for the characterization to support project owners being able to run this routine for their parts.
Based on the process used to enable the first part, we have been able to demonstrate similar results on a second part on the bench (using a manual process).
We are working to understand how repeatable the process is when applied to additional parts and if this will work for all parts or just some.
Caravel Functionality
A full silicon validation test suite has been built. We are currently working to support IO configuration required to run many of the tests.
Automation
Work on the automated test continues. The focus is implementing tests for the IO characterization and configuration. This will enable additional testing mentioned above.
MPW-2 Hardware
Breakout board fabrication and assembly is in process. There have been a couple of delays and we are now expecting final assemblies by Tuesday, September 13th. Breakout boards and parts will begin shipping to project owners once the breakout board assemblies are complete.
Progress continues to be made on the test harness for characterizing parts. Several Nucleo development samples have been obtained and the updated layouts for compatible boards are being reviewed and will be built for initial testing.
MPW-2 Simulation
Issues for the open source tools are continuing to be worked on.
Proprietary tools have been set up and are being used in parallel to reproduce the failure in simulation.
Other Analysis
User projects on MPW-2 are still being reviewed and we don’t have further information at this time.
Regards,
Jeff DiCorpo