Some digital designs hardened with older versions of OpenLane would show as being completed successfully but would still contain timing issues. If you use OpenLane to submit a design to one of the MPW programs, your submission may not produce working silicon.
“Is my submission broken?”
If you have used OpenLane prior to the ‘mpw-3’ tag (commit 2e6f340) to harden digital blocks then the resulting output may suffer from timing violations (such as hold violations) which will prevent your design from functioning.
This likely impacted digital designs submitted to MPW-1 / MPW-2 which were not verified by independent timing analysis tooling. Instructions are on how to redo timing analysis for your project can be found in this document. The manufacturing of MPW-2 has also been delayed to allow an injection of an update to the management area (as mentioned previously).
This issue should not have impacted MPW-3 designs which were created using up to date tooling. To enable people to confirm this, instructions for redoing timing analysis on MPW-3 is also provided in the document.
“I found a violation. What should I do?”
For MPW-1 or MPW-2 projects:
Send us an email with the details at tim...@efabless.com .
We cannot correct your design on the current shuttles but you are encouraged to submit a fixed version of your project to any future MPW run including MPW-3 or MPW-4.
For MPW-3 projects:
Update to the latest version of OpenLane (tag ‘mpw-3a’) and rerun.
If you are still seeing timing issues, check the following document for guidance.
You can also get help on the Slack channel #timing-closure
Resubmit the updated design before the MPW-3 deadline.
Please do let us know you found an issue. We are collecting data to understand how widespread this issue is. Send us an email with the details at <tim...@efabless.com>.
If you do find a timing issue please do not let it kill your passion. The fact that over 40 people delivered designs that were DRC clean and manufacturable was a massive achievement by itself. The Wilson Research Group @ Siemens noted in 2020 that less than 1/3rd of ASIC projects achieve success on their first spin when using extremely advanced tooling and large and very expensive verification teams!
“Success is going from failure to failure without losing your enthusiasm.”
The goal of OpenLane is to enable designers to produce correct working designs without being experts in ASIC design. To meet this goal OpenLane developers will continue to enhance the automated verification to enable anyone to easily create working silicon. People actually use the tools with things like the MPW program is an important part of making this a reality.
We encourage the experienced members of the community to continue to help improve and expand the capabilities. People like Matt Venn are providing great resources for people to learn more (see his recent “MPW1 silicon arrived! What went wrong” video).
The Efabless Team