[SimpleCPU/SimpleCPU] 0a75d2: [RTL] - Added valid signals to all the pipe regist...

[bubble12]

Branch: refs/heads/master
Home: https://github.com/SimpleCPU/SimpleCPU
Commit: 0a75d247db48aa0ab01e87b0c7950778add805b4
https://github.com/SimpleCPU/SimpleCPU/commit/0a75d247db48aa0ab01e87b0c7950778add805b4
Author: bubble12 <guptasa...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/ex_pipe_reg.v
M mips/mips-pipeline/verilog/mem_pipe_reg.v
M mips/mips-pipeline/verilog/wb_pipe_reg.v

Log Message:
-----------
[RTL] - Added valid signals to all the pipe registers

- This was required to correctly assert the instr retired signal
- The instr retired signal will be used by the ISS compare logic


Commit: 00343028f13b7b521f7d9f02704342c5d3fc17a1
https://github.com/SimpleCPU/SimpleCPU/commit/00343028f13b7b521f7d9f02704342c5d3fc17a1
Author: bubble12 <guptasa...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] - Added valid signal to top

- valid is asserted if the decoded instruction falls into either R, I or J-type
- The above check is done in the issue stage and the valid is then propagated till retire stage


Commit: a31ac6c5b31488c70df695b9749e3d9cc065df98
https://github.com/SimpleCPU/SimpleCPU/commit/a31ac6c5b31488c70df695b9749e3d9cc065df98
Author: bubble12 <guptasa...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] - Corrected few signal names

- Few signals were not following the correct pipeline naming conventions


Commit: cf50ca46550e8ce342855e9fce74c4b1e4b8e26d
https://github.com/SimpleCPU/SimpleCPU/commit/cf50ca46550e8ce342855e9fce74c4b1e4b8e26d
Author: bubble12 <guptasa...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] - Added next PC logic


Compare: https://github.com/SimpleCPU/SimpleCPU/compare/36129cd5e379...cf50ca46550e