[SimpleCPU/SimpleCPU] 0cac88: [RTL] - Fixed signals to ALU port

[Rahul Behl]

Branch: refs/heads/master
Home: https://github.com/SimpleCPU/SimpleCPU
Commit: 0cac887595c5ae7063f7b584be921b7186167d6b
https://github.com/SimpleCPU/SimpleCPU/commit/0cac887595c5ae7063f7b584be921b7186167d6b
Author: Rahul Behl <raul...@users.noreply.github.com>
Date: 2017-02-26 (Sun, 26 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] - Fixed signals to ALU port

ALU port was not connected to the right signals