[SimpleCPU/SimpleCPU] 1f1c33: [RTL] Completed forwarding paths

[raulbehl]

Branch: refs/heads/master
Home: https://github.com/SimpleCPU/SimpleCPU
Commit: 1f1c33624736ac17e89f7dfd9c1ecca369153a4d
https://github.com/SimpleCPU/SimpleCPU/commit/1f1c33624736ac17e89f7dfd9c1ecca369153a4d
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/hazard_unit.v
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] Completed forwarding paths

- Added forwarding paths from ALU/MEM stage to RF
- Added forwarding checking logic to hazard unit


Commit: 533cff3f9059be876f90fdbfb075aa7d392e81cb
https://github.com/SimpleCPU/SimpleCPU/commit/533cff3f9059be876f90fdbfb075aa7d392e81cb
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
M mips/scripts/regressionManager.py

Log Message:
-----------
Fixed git history


Commit: 36129cd5e379ab8abf22c4e6b9583f4c1e82ffe4
https://github.com/SimpleCPU/SimpleCPU/commit/36129cd5e379ab8abf22c4e6b9583f4c1e82ffe4
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-25 (Sat, 25 Feb 2017)

Changed paths:
R mips/mips-single-cycle/verilog/write_back.v

Log Message:
-----------
Merge branch 'master' of github.com:SimpleCPU/SimpleCPU


Compare: https://github.com/SimpleCPU/SimpleCPU/compare/baaa4bc01f06...36129cd5e379