[SimpleCPU/SimpleCPU] 6c5334: Removed valueplusarg from init_imem. It is already...

[raulbehl]

Branch: refs/heads/master
Home: https://github.com/SimpleCPU/SimpleCPU
Commit: 6c53345f822f8fbffb34e7ecf27945f323bfaac2
https://github.com/SimpleCPU/SimpleCPU/commit/6c53345f822f8fbffb34e7ecf27945f323bfaac2
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-24 (Fri, 24 Feb 2017)

Changed paths:
M mips/mips-single-cycle/testbench/init_imem.sv

Log Message:
-----------
Removed valueplusarg from init_imem. It is already present in top_tb.sv


Commit: f064cf47323a1b21dfdcbdcc439604053ffcc1ec
https://github.com/SimpleCPU/SimpleCPU/commit/f064cf47323a1b21dfdcbdcc439604053ffcc1ec
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-24 (Fri, 24 Feb 2017)

Changed paths:
M mips/iss/src/sim.c

Log Message:
-----------
[ISS] Fixed prints for shift instr


Commit: 57f4b4648ce7624b8b84abbe62425620f1302a3a
https://github.com/SimpleCPU/SimpleCPU/commit/57f4b4648ce7624b8b84abbe62425620f1302a3a
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-24 (Fri, 24 Feb 2017)

Changed paths:
M mips/mips-pipeline/verilog/top.v

Log Message:
-----------
[RTL] Instantiated hazard unit at top

- Connected all the signals to/fro hazard unit


Commit: 8e3c86068ad5bc0b75e720fb3aa23bb35974359a
https://github.com/SimpleCPU/SimpleCPU/commit/8e3c86068ad5bc0b75e720fb3aa23bb35974359a
Author: raulbehl <raul...@gmail.com>
Date: 2017-02-24 (Fri, 24 Feb 2017)

Changed paths:
M LICENSE

Log Message:
-----------
Merge branch 'master' of github.com:SimpleCPU/SimpleCPU


Compare: https://github.com/SimpleCPU/SimpleCPU/compare/266b2f54dd15...8e3c86068ad5