Как отделить зерно от плевела среди AI-стартапов в области EDA
3 views
Skip to first unread message
Yuri Panchul
Aug 6, 2025, 12:21:33 PMAug 6
to Silicon Russia
Сделал задачку для фильтрации легитимных ИИ-стартапов в области EDA от Остапов Бендеров. Уже проверил, что она эффективна - один ИИ ее с большим трудом решил, другие нет. Почти все тулы на это что-то генерят (хотя некоторые крэшатся), но сгенеренное (кроме одного исключения) не работает, то есть не удовлетворяет условию промпта.
https://verilog-meetup.com/2025/08/05/ai-eda-challenge-1/
Separating the wheat from the chaff in AI-driven EDA startups
August 5, 2025 By Yuri Panchul
Not all AI entrepreneurs are the same. There are good guys who make prototypes of something useful, and bad guys who try to confuse venture capitalists out of their money by hyping and shmoozing. We should remember that VCs do not spend their own money: they get funds from institutional investors such as pension funds. Therefore, bad AI entrepreneurs are de-facto predators on old ladies investing into 401(k) plans.
How to help VCs (and therefore orphans and widows) to differentiate between the legitimate innovators – and “fake it till you make it” wannabees? In the area of “AI for the Front-end Digital Chip Design” – very easily. We at Verilog Meetup created a SystemVerilog Microarchitecture Challenge for AI No.1. If a startup’s prototype passes the challenge, we recommend continuing the discussion; if it does not – the tool is useless for the real industrial design. The challenge requires an intern-level expertise and imitates a real task given to a typical intern in a typical electronic company. If an AI software cannot do it – it is dead on arrival.
https://github.com/verilog-meetup/systemverilog-microarchitecture-challenge-for-ai-1
SystemVerilog Microarchitecture Challenge for AI No.1
This repository contains a challenge to any AI software that claims to generate Verilog code. The challenge is based on a very typical scenario in an electronic company: an engineer has to write a pipelined block using a library of sub-blocks written by somebody else. Then this engineer has to verify his block using a testbench written by somebody else. He may also need to figure out the sub-block latencies and handshakes by analyzing the code, since a lot of code in electronic companies is not sufficiently documented.
The SystemVerilog Microarchitecture Challenge for AI No.1 is based on the SystemVerilog Homework project by Verilog Meetup. It also uses the source code of an open-source Wally CPU.
1. The Prompt
Finish the code of a pipelined block in the file challenge.sv. The block computes a formula “a ** 5 + 0.3 * b + c”. You are not allowed to implement your own submodules or functions for the addition, subtraction, multiplication, division, comparison or getting the square root of floating-point numbers. For such operations you can only use the modules from the arithmetic_block_wrappers directory. You are not allowed to change any other files except challenge.sv. You can check the results by running the script “simulate”. If the script outputs “FAIL” or does not output “PASS” from the code in the provided testbench.sv by running the provided script “simulate”, your design is not working and is not an answer to the challenge. Your design must be able to accept a new set of the inputs (a, b and c) each clock cycle back-to-back and generate the computation results without any stalls and without requiring empty cycle gaps in the input. The solution code has to be synthesizable SystemVerilog RTL. A human should not help AI by tipping anything on latencies or handshakes of the submodules. The AI has to figure this out by itself by analyzing the code in the repository directories. Likewise a human should not instruct AI how to build a pipeline structure since it makes the exercise meaningless.
https://verilog-meetup.com/2025/08/05/ai-eda-challenge-1/
Separating the wheat from the chaff in AI-driven EDA startups
August 5, 2025 By Yuri Panchul
Not all AI entrepreneurs are the same. There are good guys who make prototypes of something useful, and bad guys who try to confuse venture capitalists out of their money by hyping and shmoozing. We should remember that VCs do not spend their own money: they get funds from institutional investors such as pension funds. Therefore, bad AI entrepreneurs are de-facto predators on old ladies investing into 401(k) plans.
How to help VCs (and therefore orphans and widows) to differentiate between the legitimate innovators – and “fake it till you make it” wannabees? In the area of “AI for the Front-end Digital Chip Design” – very easily. We at Verilog Meetup created a SystemVerilog Microarchitecture Challenge for AI No.1. If a startup’s prototype passes the challenge, we recommend continuing the discussion; if it does not – the tool is useless for the real industrial design. The challenge requires an intern-level expertise and imitates a real task given to a typical intern in a typical electronic company. If an AI software cannot do it – it is dead on arrival.
https://github.com/verilog-meetup/systemverilog-microarchitecture-challenge-for-ai-1
SystemVerilog Microarchitecture Challenge for AI No.1
This repository contains a challenge to any AI software that claims to generate Verilog code. The challenge is based on a very typical scenario in an electronic company: an engineer has to write a pipelined block using a library of sub-blocks written by somebody else. Then this engineer has to verify his block using a testbench written by somebody else. He may also need to figure out the sub-block latencies and handshakes by analyzing the code, since a lot of code in electronic companies is not sufficiently documented.
The SystemVerilog Microarchitecture Challenge for AI No.1 is based on the SystemVerilog Homework project by Verilog Meetup. It also uses the source code of an open-source Wally CPU.
1. The Prompt
Finish the code of a pipelined block in the file challenge.sv. The block computes a formula “a ** 5 + 0.3 * b + c”. You are not allowed to implement your own submodules or functions for the addition, subtraction, multiplication, division, comparison or getting the square root of floating-point numbers. For such operations you can only use the modules from the arithmetic_block_wrappers directory. You are not allowed to change any other files except challenge.sv. You can check the results by running the script “simulate”. If the script outputs “FAIL” or does not output “PASS” from the code in the provided testbench.sv by running the provided script “simulate”, your design is not working and is not an answer to the challenge. Your design must be able to accept a new set of the inputs (a, b and c) each clock cycle back-to-back and generate the computation results without any stalls and without requiring empty cycle gaps in the input. The solution code has to be synthesizable SystemVerilog RTL. A human should not help AI by tipping anything on latencies or handshakes of the submodules. The AI has to figure this out by itself by analyzing the code in the repository directories. Likewise a human should not instruct AI how to build a pipeline structure since it makes the exercise meaningless.
Reply all
Reply to author
Forward
0 new messages