Образовательные технологии опробованные в России - работают и в США

[Yuri Panchul]

Провели мероприятие в Калифорнийском политехническом государственном университете в Сан-Луис-Обиспо. Докладчиками были: ваш покорный слуга Юрий Панчул, два американских инженера проектирующие чип по ускорению ИИ, и китайский студент из Университета Калифорнии в Санта-Барбаре. Идея мероприятия возникла, когда я встретился с выпускником Cal Poly Стенли на конференции самоделкиных OpenSause, и он поведал мне то, что я уже знал из собеседований американских студентов: они изучают в вузе карты Карно, доходят до конечного автомата светофора, отдельно постигают классический 5-стадийный конвейер MIPS (ныне RISC-V), а потом идут на собеседование на работу, и - хоба! - выясняется что их карты Карно никого в индустрии не интересуют, а вопросы идут про сопряжение конвейера обработки данных (не процессорного!) и FIFO, чего они не проходили.

Отчет и все видео - https://verilog-meetup.com/2025/10/29/calpoly-slo-report/

Начало:

A push for better workforce development in EE starts with the Verilog Meetup at Cal Poly 

The idea to make a Verilog Meetup event at California Polytechnic State University, San Luis Obispo, started as a discussion between Yuri Panchul, a chip designer, and Stanley To, a CalPoly EE graduate working as an airspace contractor. This happened during an OpenSauce exhibition in the San Francisco Bay Area back in the summer. The discussion was joined by several student activists and the topic was the following:

It is not a secret to anybody in the digital chip design industry that students in many schools are not trained in solving microarchitectural problems with pipelines, FIFOs, credit-based flow control, arbiters etc, which constitute the bulk of work in front-end RTL design in the industrial projects: GPU, networking chips etc.

In a school, students usually have a Verilog class with FPGA labs that goes from gates to FSMs, plus a computer architecture class that presents the only kind of pipeline they know: a traditional 5-stage static pipeline for RISC-V (and MIPS in the past). This is not enough to work productively or even to pass a job interview, because many companies ask candidates questions on data pipelining.

So we decided to make an event to start the process of repairing the education system to better align it with industrial needs. To make the event more complete, we added a lecture on static timing analysis to microarchitecture, since designing a perfect pipeline should go along with measuring how many picoseconds are left in each stage we are building, and balancing the pipeline latency versus the maximum clock frequency.

Since learning digital design without doing is similar to learning to play a flute by watching slides on how to press the flute keys, we added FPGA boards and a path to move the design to a manufactured ASIC to our event.

We also covered Built-In Self-Test (BIST), memory repair with BIRA and BISR, a bit of emulation, and a talk on challenging AI. We tried to make FPGA exercises more fun by generating graphics on LCD screens. Then we also planned work work with music, but ran out of time.

Дальше - см. ссылку выше