Теперь и в американском университете

[Yuri Panchul]

Итак, после проведения кучи семинаров в университетах России, Украины, Казахстана, Киргизии, Армении, Азербайджана и Мексики - проводим семинар в Калифорнийском политехническом государственном университете в Сан-Луис-Обиспо:

Verilog Meetup at California Polytechnic State University, San Luis Obispo, California on October 25-26

See the location and schedule at the link below. The goals for the Verilog Meetup at Cal Poly SLO:

1. Introduce the basic technologies of digital chip design to a wider audience than EE students. It includes students who are choosing a career path or simply curious about neighboring areas, such as a software student who wants to build an FPGA-based hardware accelerator for his project.

2. Help the graduating students to train themselves for job interviews, particularly in the areas of SystemVerilog and microarchitecture. These areas are key to job success for a front-end RTL designer in an electronic company.

3. Discuss how the current EE and CS curricula can be improved in the area of register transfer level (RTL) microarchitecture, design verification and EDA vendor independence.

https://verilog-meetup.com/2025/10/11/calpoly-slo-plan/