RTL Design Engineer And validation Engineer Positions for Pune

[Vasu]

Dear group Members

Please share your resume if you are looking out for change


Work Location:Pune

Designation: Senior Design Engineer / Staff Design Engineer
Experience Level: 4-8 years/8+ years of good RTL design experience.
Responsibilities:

Will be responsible for micro-architecture definition and RTL design
of blocks and all other associated tasks as a designer eg: working
with the verification team, defining synthesis constraints etc.

Requirements:
Overall exp 4-6 yrs
Should have good knowledge of the Protocol
Should have experience working with verification teams and guiding
them with the verification plan
Should have been involved in atleast one Tapeout
Should have good understanding about the entire ASIC flow
Team Player
Exp with one of the Skills is mandatory• PCIE; Security Engine Design;
SATA/Serdes Design; USB Design


Designation: Senior/Staff Validation Engineer
Experience Level:

B.Tech. with 2-5years experience for Senior Validation Engineer
B.Tech. with 2-5years experience for Staff Validation Engineer

Requirements:

ASIC Prototyping in FPGA
Experience in SoC Integration is desired
Should know verilog and test bench components
Pre silicon and post silicon Validation experience
Knowledge of PCI Express, Ethernet, USB,DDR2 etc. is required
Xilinx, Synpify tool flow experience
Scripting Knowledge of Perl, TCL
Optional Experience:
Knowledge of C is advantage
Knowledge of debugging in FPGA based designs, using LA, embedded ICE,
Chip-scope etc is desired.

Regards

vasu