Openings in Semiconductor Companies -Individual contributor

[Vasu]

Dear friends

Please share your resume if you are looking out for change

work Location :bangalore

Physical Design:



Bachelor or Master’s in (Micro) Electronics plus 2-15 years of
relevant experience in implementation / physical design
Hands on experience in Synthesis and/or Custom design in 500Mhz-2Ghz
frequency

(Including exposure to Design Compiler, IC Compiler, Nanoroute, Zroute
etc)

Working knowledge of Timing Analysis, physical verification, signal
integrity issues

(Including Primetime STA, Calibre DRC/LV, EM/IR
analysis using Apache Redhawk etc)

Working knowledge of basic circuit design (Including exposure to
Hspice etc)

Exposure to SRAM memory design is desirable
Ability to lead / mentor a small team of engineers (3-4)
Strong domain expertise in one or more areas of physical design
PERL, Unix & TCL coding skills

Verification: -



Experience Level: - 3-15 Years



1. Experience of verification of complex ICs, preferably
microprocessors, using SV, C++, OVM at IP level (preferred) and/or SOC
level

2. Strong C++ and SV skills

3. Strong problem solving and debug skills

4. Exposure to tools like VCS, Verdi

5. Exposure to silicon debug, tester, gatesims (preferred)

6. Would prefer resumes from product companies (Freescale,
Intel, ARM, APM)



Core Verification: -



Experience Level: - 3 – 15 Years



Good programming skills in C++, Verilog, Assembly
Experience in verifying complex designs.
Good understanding of verification methodology
Processor verification and/or X86 architecture knowledge a plus



DFT/ATPG Engineer: -



Experience Level:- 3 – 15 Years



Main work requirement will include (But not limited to)

1) ATPG tools –

a. Mentor - Test Kompress & Fast scan

b. Synopsys –Tetramex & DFT max

2) Pattern generation


i. Modes => Compressed mode & Compressor Bypass mode


ii. Fault models –Must –Transition & Stuck at

Good to have –path delay/Bridging faults

3)Pattern simulation – gate level pattern simulation
and debug.

4)Fault grading

5)Coverage analysis

6)Memory modeling in scan

7)Logic bist

8)Perl/tcl programming

9)Unix/Linux OS/environment

10)Knowledge of Scan insertion flow

11)Aware of memory bist & Jtag insertion &
verification flow

regards

srinivas