Serial And Parallel Io 8251 And 8255
Rapheal Pinto
Limited functionality: While the 8251 USART is a useful peripheral for serial communication, it does not include more advanced features, such as DMA (direct memory access) or advanced error correction.
The 8255 PPI has a 26 pin header that matches the 8155 I/O on the SBC-85 CPU, except the last two pins (25 & 26) are used for I/O rather than redundant power and ground. A very nice feature of the 8255 is direct bit set/reset capability and will be handy for bit-banging out to all of your I2C, Dallas 1-wire, and SPI devices. As common to all Intel parallel port devices, port C can also be used for handshaking for ports A & B if you have your eye on a Centronics style parallel port.
For those that are offended by RS232 out the 8085 SID and SOD, need another serial port, or just want more throughput than bit-banging can deliver, the 8251 USART offers an interrupt driven turn-key serial port up to 19.2K Baud. Its DB9 uses the CTS-RTS or they can (must!!) be looped with a jumper if not used. There is a little patch area where the USART buffer pins can be connected to interrupt lines, and a left over OR gate is provided if you want to hybridize the interrupt request. (Two other unused OR gates and two inverters are left with solder jumpers if you want to patch them in to something.)
All totaled, the board takes eight sequential port addresses with the base address set by a five position DIP. As always, I used brute force address decoding to avoid the use of any programmable devices and while decoding was straight forward it is a little bit messy since everyone needed a different number of ports. The 8255 gets the bottom four port addresses ( i.e., xxxx x0xx), the 8251 gets the next two (base + 04H & 05H, i.e., xxxx x10x), the sandbox header gets the next address (base + 06H, i.e., xxxx x110) and the roll-your-own port gets the top address (base = 07H, i.e., xxxx x111).
The v0.9 prototype hardware has been received and assembled and is now undergoing initial tests. So far, I am happy with its performance and, aside from maybe a silkscreen placement here and there, I have not found any hardware problems. I have been able to test the home-brew 8-bit I/O port, the three 8255 I/O ports, and the 8251 USART. Unfortunately, i forgot to add the real time clock to my last component order so i just got that on order today. I am sending some out to beta testers and if things still look good in a few weeks I will add the build files to the project site and order a batch of v1.0 boards to put up on tindie and ebay.
He later joined Intel in 1972. There, he worked with Faggin to develop the Intel 8080, released in 1974. Shima then developed several Intel peripheral chips, some used in the IBM PC, such as the 8259 interrupt controller, 8255 programmable peripheral interface chip, 8253 timer chip, 8257 direct memory access (DMA) chip and 8251 serial communication USART chip. He then joined Zilog, where he worked with Faggin to develop the Zilog Z80 (1976) and Z8000 (1979).[2]
After the 4004, Intel designed the 8008 (architecture by Computer Terminal Corporation, design by Federico Faggin and Hal Feeney). Shima then joined Intel in 1972.[2] He was employed to implement the transistor-level logic of Intel's next microprocessor, which became the Intel 8080 (conception and architecture by Federico Faggin), released in 1974.[3] Shima then developed several Intel peripheral chips, some used in the IBM PC, such as the 8259 interrupt controller, 8255 parallel port chip, 8253 timer chip, 8257 DMA chip and 8251 serial communication USART chip.[2] He was not involved in the creation of the Intel 8088 or 8086.
The 8251 chip is Universal Synchronous Asynchronous Receiver Transmitter (USART). It acts as a mediator between the microprocessor and peripheral devices. It converts serial data to parallel form and vice versa. This chip is 28 pin DIP.
Now let us see how 8251 can be interfaced with 8085. In the diagram, we can see that eight data lines D7-0 are connected to the data bus of the microprocessor. And also the RD and WR of the 8251 are also connected with the RD and RD of 8051. The 8251 is getting the clock from the CLK OUT pin of 8085. And the RESET is also connected to the RESET OUT pin of the microprocessor.
The C/D pin is used to select either control register or data register. This pin is connected to the A0 pin of 8085. The CS pin of 8251 is attached to the output of an address decoder circuit. The address decoder uses A7 to A1 lines of the microprocessor. In this diagram the CS will be enabled when A7 and A4 is at logic 1, and all other lines are at logic 0.
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D0 - D7:data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines. CS (Chip Select). If this line is a logical 0, the microprocessor can read and write to the 8255. RESET: The 8255 is placed into its reset state if this input line is a logical 1
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