H89 on a Veroboard!

[Norberto Collado]

I ordered a Veroboard size 5"x10" to do the H89 prototyping. It is all going to be wire-wrap to allow me to debug easily as I make design changes. It will be nice to see a "new" H89 on a Veroboard booting HDOS and CP/M. Once I get a working wire-wrap prototype board, then I will proceed to layout the board to the smallest size possible.

 

The target is to get the H17, Z67, two serial ports, USB support, CPU speed control, RTC. One RAM and one EPROM IC along with the Z80 and all supported logic.

To be succesfull, I'm planning to break the design into pieces.

 

1. Add Z80 with all supported logic using a Single EPROM and RAM IC.

    - Integrate MMS-IDE monitor along with the H17 monitor on a single EPROM

    - Integrade MTR90 along with H17 monitor into a single EPROM.

2. Get Serial communications working on power-on

3. Run Heath memory tests

4. Add H17 circuitry

    - Boot HDOS

        - Run HDOS test utilities

    - Boot CP/M

4a. Add HSFE to support 3.5" floppies

5. Add Z67

    - Boot Heath HDOS and CP/M

    - Boot Quikdata CP/M

6. Add RTC support

7. Add USB support

8. Add CPU speed control for 2,4,8,16 MHz

9. Add wait states to Z80

9a. Add P506 10-pin connector and P512 25-pin connector for testing/debug purposes.

10. Layout the design

11. Done!

 

I will need to name this design "H89-NCR" or something similar.....

 

One question; The H89 uses the 8250 to talk to the H19 serial port. So using the 16C550 instead should work; correct?

 

Norberto

 

[Mark Garlanger]

Quite impressive. Any plans to support bank switched memory? I finally got the IMD program working on one of my old computers/floppies and imaged MMS's CP/M Plus (3.0). The disk images are up on my site:
http://heathkit.garlanger.com/library/MagnoliaMicrosystems/

It requires the bankswitching that was done on their 128k add-on board. We have documentation on how it is controlled.

According to an earlier discussion on the list, the 16550 will work, but the buffers will not be utilized unless the ROM code is updated.

I also have documentation on how the DG Super 89 did bank-switching, but unfortunately, I don't have either CP/M Plus or MP/M for that one.

Lee, did the H-1000 also do bank-switching? Did it run CP/M Plus and/or MP/M?

Mark

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[Lee Hart]

On 6/5/2013 1:45 PM, Mark Garlanger wrote:
> Lee, did the H-1000 also do bank-switching? Did it run CP/M Plus and/or
> MP/M?

The H-1000 had both Z80 and 8086 CPUs. The 8086 could directly address 1
Mbyte. When you were running CP/M or HDOS, the Z80 used the 8086 as a
programmable coprocessor, to read/write memory outside the Z80's range.

Memory beyond 64k was typically used as a RAM disk. CP/M-80 had a BIOS
extension, and HDOS had a device driver. The Z80 part was tiny; it just
put the addresses to move data to/from in RAM, and called the 8086 to do
the actual work.

Technical Microsystems implemented CP/M-80, CP/M-86, HDOS, and MS-DOS on
the H-1000. Others may have done CP/M Plus or MP/M; I don't know. One
thing for sure; the 8086 with its 16-bit data path moved data about 8
times faster than the Z80!

--
Never doubt that the work of a small group of thoughtful, committed
citizens can change the world. Indeed, it's the only thing that ever
has! -- Margaret Mead
--
Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm

[Norberto Collado]

First is to get the basic H89 working and then to add enhancements as needed because it is easy on a wire-wrap board. Do you have the schematics for the MMS solution? Where is the documentation in PDF format? Can I boot such images on my H8 system or it is only for the H89 system? How do I install the IMD images into floppies?

 

Norberto

 

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!
From: Mark Garlanger <garl...@gmail.com>
Date: Wed, June 05, 2013 11:45 am
To: "se...@googlegroups.com" <se...@googlegroups.com>

Quite impressive. Any plans to support bank switched memory? I finally got the IMD program working on one of my old computers/floppies and imaged MMS's CP/M Plus (3.0). The disk images are up on my site:
http://heathkit.garlanger.com/library/MagnoliaMicrosystems/

It requires the bankswitching that was done on their 128k add-on board. We have documentation on how it is controlled.

According to an earlier discussion on the list, the 16550 will work, but the buffers will not be utilized unless the ROM code is updated.

I also have documentation on how the DG Super 89 did bank-switching, but unfortunately, I don't have either CP/M Plus or MP/M for that one.

Lee, did the H-1000 also do bank-switching? Did it run CP/M Plus and/or MP/M?

Mark

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[Kenneth L. Owen]

Hi Norberto,

 

IMD files are foreign disk images made on the MSDOS application IMD by I believe a Mr. Dunfield.  If you send me the IMD files, I can write the disk and then send you the files.

 

-- ken

 

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[Mark Garlanger]

Yes, IMD was create by Dave Dunfield and requires a PC with DOS. The format is well documented on his site and easily images disks (as long as your PC has a compatible floppy controller and floppy drive.

Mark

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[Mark Garlanger]

Yes, it's best to first get the basics going. I just wanted to throw that out, in case there was any choices that might make a bank-switching easier...  There is a manual on Les's site, but I don't think it has the schematics.

Another option, I forgot about was Terry's new board for the H89, that had 512k and supported bank-switching...

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[Norberto Collado]

Terry board is on my radar screen. Once I get the basic board working, I think all I need is to insert his board into the Z80 socket before prototyping it. Not sure if HDOS boot support is kept.

 

Norberto

 

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[Norberto Collado]

I need to know the answer to the following question;

 

1.       On the H89 once it is using the MTR90 or the MMS-84B EPROM, then the H17 floppy RAM (U523 & U525) is disabled as in the H8 with PAM-37; correct?  So I can delete this circuit without any issues as long it is supporting the MTR90 or the MMS-84B monitors. Just want to be sure.

 

I think I have a working hand-made schematics to start the wire-wrapping once I get the board from Canada. For the H89 OTPs, I will use a 512K OTP EPROM as a replacement, but it is all about timing. For the RAM is the same IC that Les’ is using on the H8 64K RAM board. For the MONITOR and the H17 FW, is the M27C1001, due to its timing. For serial port is either the 8250 or the 16550 USART. The osc circuit is the same as the H8 speed board 2-16MHz. CPU is a 40-pin Z80 at 20MHz.  The reset circuit is based on the H19 reset circuit. Power is from a PC power supply (+3.3,+5,+12,-12V). Also I will keep the Single Step and the 2ms clock interrupts. For power-on I will use the H19 circuitry to beep the speaker along with the voltage supervisor. I think that is all for the basic system to work. All the work will be done by the OPT EPROM’s keeping the circuit footprint small. Once it is working, then I will start adding new features one at a time starting with the H17 controller and the last features will be the PC PS2 keyboard along with the Propeller RISC micro to support a VGA display to emulate the H19 terminal. The target is to be able to use the H19 terminal or the PC keyboard along with a VGA LCD display. LED’s for HALT, Power-on, I/O, & speed control.

 

Norberto

[Mark Garlanger]

I'm pretty sure the H17 RAM is still used when the ORG-0 is disabled in HDOS mode.

Mark

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[Norberto Collado]

I rather play safe and keep this circuitry them. I will add the 6116P-70 SRAM to support this circuit.

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!
From: Mark Garlanger <garl...@gmail.com>

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[Norberto Collado]

Based on feedback I decided to map the 128K x8 RAM into two sections;

 

64K map to the OS

64K map to floppy RAM. The H17 will use the first 1K bytes and 63K bytes are free for any future applications or debug code.

 

I’m still trying to find out a cheap and simple circuit to replace the 444-83, 444-86 and the 444-61 OTP’s. So far the indication is to use the newer OTP AT27C256R-45PU (three of them @ $1.95 each which is not that bad) to keep circuit the same as the original H89A.

 

Norberto

[Norberto Collado]

Any idea why I need this circuit? It is just putting LOW’s on the data bus. I wonder if this is part of the refresh circuitry which I longer need.

 

Norberto

 

[Terry Gulczynski]

Norberto,

More correctly, it puts a 00H byte on the data bus WHEN you attempt to read an address that doesn't exist in the memory map.  For instance, reading an address above 48K in a 48K system.

No, you don't need it, especially if 64K is 'stock' - there will never be an address that doesn't map to an actual RAM cell.

If you're attempting to determine the installed RAM capacity, it's possible that writing then reading a non-existant cell could give you a 'good' RAM indication.  This circuit helps prevent that by eliminating a 'phantom' RAM read, guaranteeing that reading a non-existent cell will always return a 00 byte.

 
Terry

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[Lee Hart]

On 6/9/2013 2:03 PM, Norberto Collado wrote:
> Any idea why I need this circuit? It is just putting LOW�s on the data

> bus. I wonder if this is part of the refresh circuitry which I longer need.

U521 was enabled by the PROMs when there was no memory installed at that
address. It was there so Heath's memory sizing routine would be sure to
find 00h when it read a non-existent location.

If you leave it out, the data bus floats during non-memory access, and
you would read random data that might make the Z80 think there is RAM there.

They could have used pull-up resistors instead, but the chip uses less
power.

In your case, you can design so there never *is* an address with no
memory at it. So U521 is unnecessary.

--
Progress is the product of human agency. Things get better because we
make them better. Things go wrong when we get too comfortable, when we
fail to take risks or seize opportunities. -- Susan Rice

[Mark Garlanger]

Hi Terry,

  What happens in low memory, when in non-ORG-0 mode? There is a 1k hole at 4k between the MTR-90 ROM and the H17 RAM? Would read and writes to that area go to the RAM even when the RAM is not mapped?

Mark

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[Terry Gulczynski]

The circuit only responds with the 00H byte when you attempt to read above the top of mapped memory.� The 8K 'banks' selected by the Memory Map Decoder @ U517 are either an actual 8K bank of RAM, or the NULL circuit described here when you attempt to access above the mapped RAM.

In the case of the lowest 8K bank (comprised of the MTR ROM, H17 ROM, and H17 RAM) the NULL byte will never be accessed - this RAM + ROM bank is always present.

Finally, there is a 1K RAM page in the lowest 8K bank that is normally not present.� Typically, the MTR ROM is 4K, the H17 ROM is 2K, and the H17 RAM is 1K, leaving 1K that is not present in the lower 8K bank.� The reality is that the 1K page IS present, but it is not normally stuffed with RAM.� Specifically, U522 and U524 (I think - it might be U523 and U525) are empty sockets.� You can install a pair of RAM chips in these empty sockets and the 1K RAM 'hole' is then filled.� HDOS will never attempt to access that RAM, so you can have a protected RAM page the OS will never touch.

CP/M, on the other hand, wipes that page out via ORG-0, so the extra 1K will never be present in the memory map.


So, the short answer to your question is yes, accesses to the lower 8K always go only to the lower 8K, even when that 1K page of RAM is accessed but not present.� The RAM sizing routine Lee mentions starts at a RAM address above the lowest 8K, so the empty 1K RAM page cannot affect the RAM sizing routine.


Terry



On 6/9/2013 3:32 PM, Mark Garlanger wrote:

Hi Terry,

� What happens in low memory, when in non-ORG-0 mode? There is a 1k hole at 4k between the MTR-90 ROM and the H17 RAM? Would read and writes to that area go to the RAM even when the RAM is not mapped?

Mark

On Sun, Jun 9, 2013 at 2:22 PM, Terry Gulczynski <terr...@cfl.rr.com> wrote:

Norberto,

More correctly, it puts a 00H byte on the data bus WHEN you attempt to read an address that doesn't exist in the memory map.� For instance, reading an address above 48K in a 48K system.

No, you don't need it, especially if 64K is 'stock' - there will never be an address that doesn't map to an actual RAM cell.

If you're attempting to determine the installed RAM capacity, it's possible that writing then reading a non-existant cell could give you a 'good' RAM indication.� This circuit helps prevent that by eliminating a 'phantom' RAM read, guaranteeing that reading a non-existent cell will always return a 00 byte.

�

Terry

On 6/9/2013 3:03 PM, Norberto Collado wrote:

Any idea why I need this circuit? It is just putting LOW�s on the data bus. I wonder if this is part of the refresh circuitry which I longer need.

�

Norberto

�

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�

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�

[Mark Garlanger]

I'm still a little confused. For a 64k system, like Norberto is doing, he doesn't need the circuit. But in my emulator, I plan to allow the user to specify the memory size, so they might select 16k, 32k, or 48k. Based on the memory map diagrams in the manuals, if there is less than 64k, the RAM starts at 8k, and goes up to allow HDOS to use the full amount of memory. So in those cases, there will not be RAM there. Do you know what the H89 would do if it tried to access that empty spot? Or if the 2k MTR-88 or MTR-89, is used and access is attempted to the 2k-4k range? Will the earlier support chips that are required for MTR-88 and MTR-89, change this behavior?

Mark

On Sun, Jun 9, 2013 at 2:57 PM, Terry Gulczynski <terr...@cfl.rr.com> wrote:

The circuit only responds with the 00H byte when you attempt to read above the top of mapped memory.  The 8K 'banks' selected by the Memory Map Decoder @ U517 are either an actual 8K bank of RAM, or the NULL circuit described here when you attempt to access above the mapped RAM.

In the case of the lowest 8K bank (comprised of the MTR ROM, H17 ROM, and H17 RAM) the NULL byte will never be accessed - this RAM + ROM bank is always present.

Finally, there is a 1K RAM page in the lowest 8K bank that is normally not present.  Typically, the MTR ROM is 4K, the H17 ROM is 2K, and the H17 RAM is 1K, leaving 1K that is not present in the lower 8K bank.  The reality is that the 1K page IS present, but it is not normally stuffed with RAM.  Specifically, U522 and U524 (I think - it might be U523 and U525) are empty sockets.  You can install a pair of RAM chips in these empty sockets and the 1K RAM 'hole' is then filled.  HDOS will never attempt to access that RAM, so you can have a protected RAM page the OS will never touch.

CP/M, on the other hand, wipes that page out via ORG-0, so the extra 1K will never be present in the memory map.

So, the short answer to your question is yes, accesses to the lower 8K always go only to the lower 8K, even when that 1K page of RAM is accessed but not present.  The RAM sizing routine Lee mentions starts at a RAM address above the lowest 8K, so the empty 1K RAM page cannot affect the RAM sizing routine.

Terry

On 6/9/2013 3:32 PM, Mark Garlanger wrote:

Hi Terry,

  What happens in low memory, when in non-ORG-0 mode? There is a 1k hole at 4k between the MTR-90 ROM and the H17 RAM? Would read and writes to that area go to the RAM even when the RAM is not mapped?

Mark

On Sun, Jun 9, 2013 at 2:22 PM, Terry Gulczynski <terr...@cfl.rr.com> wrote:

Norberto,

More correctly, it puts a 00H byte on the data bus WHEN you attempt to read an address that doesn't exist in the memory map.  For instance, reading an address above 48K in a 48K system.

No, you don't need it, especially if 64K is 'stock' - there will never be an address that doesn't map to an actual RAM cell.

If you're attempting to determine the installed RAM capacity, it's possible that writing then reading a non-existant cell could give you a 'good' RAM indication.  This circuit helps prevent that by eliminating a 'phantom' RAM read, guaranteeing that reading a non-existent cell will always return a 00 byte.

 
Terry

On 6/9/2013 3:03 PM, Norberto Collado wrote:

Any idea why I need this circuit? It is just putting LOW’s on the data bus. I wonder if this is part of the refresh circuitry which I longer need.

 

Norberto

 

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[Terry Gulczynski]

OK, let's look at it from the other direction...

Regardless of the memory size specified, the null circuit Norberto showed us is not going to respond to a RAM access in the lowest 8K bank where the ROM resides.

As you say, the MTR-88 and MTR-89 ROMs are 2K, leaving a 2K 'hole' in the map (from 2K-4K) where the upper half of MTR-90 resides.� Also, there is another hole at the 7K-8K range where the empty RAM sockets are located (U522 & U524.)

When performing a memory read at one of these holes in the memory map, you will read garbage from the floating, not-driven data bus.� The data won't be random, but the data bus is in an undefined state since none of the RAM chips are actually driving it.

These 'holes' in the 0K-8K map are only present when ORG-0 is not enabled.� Once ORG-0 is in effect, regular RAM has been swapped in to the 0K-8K bank, so it contains contiguous RAM for the entire 8K.

Your emulator can report the 00H bytes at 2K-4K (when using MTR-88 or -89) and 7K-8K during non-ORG-0 if you want - it won't bother HDOS.� You can also allow it to report random or any other garbage - it still won't bother HDOS.

Many years ago, I installed the 1K RAM chips @ U522 & U524, closing the 7K-8K 'hole' we've been discussing - the result was that testing the 1K RAM hole reported proper reads/writes in that 1K page; before installing the RAM, I always read garbage there - not 00H bytes.� HDOS does not use that RAM in any way - doesn't even recognize that it exists - so the end result is a protected 1K RAM page that is never violated by the OS (or any other software, for that matter, since nothing expects that RAM to be present.)

If I were creating an H89 emulator, I'd fill that RAM page with 'real' RAM, just as I did when I installed U522 & U524.


Terry

On 6/9/2013 4:54 PM, Mark Garlanger wrote:

I'm still a little confused. For a 64k system, like Norberto is doing, he doesn't need the circuit. But in my emulator, I plan to allow the user to specify the memory size, so they might select 16k, 32k, or 48k. Based on the memory map diagrams in the manuals, if there is less than 64k, the RAM starts at 8k, and goes up to allow HDOS to use the full amount of memory. So in those cases, there will not be RAM there. Do you know what the H89 would do if it tried to access that empty spot? Or if the 2k MTR-88 or MTR-89, is used and access is attempted to the 2k-4k range? Will the earlier support chips that are required for MTR-88 and MTR-89, change this behavior?

Mark

On Sun, Jun 9, 2013 at 2:57 PM, Terry Gulczynski <terr...@cfl.rr.com> wrote:

The circuit only responds with the 00H byte when you attempt to read above the top of mapped memory.� The 8K 'banks' selected by the Memory Map Decoder @ U517 are either an actual 8K bank of RAM, or the NULL circuit described here when you attempt to access above the mapped RAM.

In the case of the lowest 8K bank (comprised of the MTR ROM, H17 ROM, and H17 RAM) the NULL byte will never be accessed - this RAM + ROM bank is always present.

Finally, there is a 1K RAM page in the lowest 8K bank that is normally not present.� Typically, the MTR ROM is 4K, the H17 ROM is 2K, and the H17 RAM is 1K, leaving 1K that is not present in the lower 8K bank.� The reality is that the 1K page IS present, but it is not normally stuffed with RAM.� Specifically, U522 and U524 (I think - it might be U523 and U525) are empty sockets.� You can install a pair of RAM chips in these empty sockets and the 1K RAM 'hole' is then filled.� HDOS will never attempt to access that RAM, so you can have a protected RAM page the OS will never touch.

CP/M, on the other hand, wipes that page out via ORG-0, so the extra 1K will never be present in the memory map.

So, the short answer to your question is yes, accesses to the lower 8K always go only to the lower 8K, even when that 1K page of RAM is accessed but not present.� The RAM sizing routine Lee mentions starts at a RAM address above the lowest 8K, so the empty 1K RAM page cannot affect the RAM sizing routine.


Terry

[Lee Hart]

The H89 memory map looks like this:

BANK 0 - ROMs and static RAMs
- enabled by RESET, or when General Purpose Port A (F2h) bit 5 = 0
- 0000-07FF monitor ROM (U518) used for 2k ROMs (MTR88, MTR-89)
U518 has jumpers to also select 0000-0FFF for 4k ROMs (MTR-90)
- 0800-0FFF spare ROM (U519) not normally used
- 1000-17FF floppy RAM (U522-U525) 2k of 2114 static RAMs
1000-13FF - U523 and U525 (normally installed)
1400-17FF - U522 and U524 (not normally installed)
This RAM write-protected by a bit from the H17 controller board
(normal), or by bit 3 of General Purpose Port A (jumper option).
- 1800-1FFF H17 ROM (U520) for hard-sector floppy disk controller

Writing to the ROMs in Bank 0 actually does a write to Bank 1
system RAM at the same address.

BANK 1 - System RAM
- dynamic RAM, 16k to 64k, 1 to 4 banks of eight 16kx1 chips each
- when 16k to 48k of RAM is installed it is addressed from 2000-up.
RAM above the top of this reads 00h (due to U521)
- when 64k of RAM is installed, it is addressed from 0000-FFFF

Terry Gulczynski wrote:
> Regardless of the memory size specified, the null circuit Norberto
> showed us is not going to respond to a RAM access in the lowest 8K bank
> where the ROM resides.

Agreed. There is *always* RAM there, because at least 16k of Bank 2 RAM
is always installed.

> As you say, the MTR-88 and MTR-89 ROMs are 2K, leaving a 2K 'hole' in

> the map (from 2K-4K) where the upper half of MTR-90 resides. Also,

> there is another hole at the 7K-8K range where the empty RAM sockets are
> located (U522 & U524.)

Yes. U521 won't respond to addresses in this range, so you will either
get the static RAMs, or garbage (for empty static RAMs sockets).

> Many years ago, I installed the 1K RAM chips @ U522 & U524, closing the
> 7K-8K 'hole' we've been discussing - the result was that testing the 1K

> RAM hole reported proper reads/writes in that 1K page...

> so the end result is a protected 1K RAM page that is never violated
> by the OS (or any other software, for that matter, since nothing expects
> that RAM to be present.)

I installed the extra 1k RAMs, and used them with a version of Write
Hand Man to save/restore BIOS and BDOS state information when swapping
tasks. (Write-Hand-Man was a TSR program for CP/M-80. You could hit a
"hot" key, and essentially be back at the CP/M prompt to run little
programs, and then return to the interrupted application right where you
left off).

I also used this 2K static RAM on the H-1000. It holds 8086 programs,
which are called by the BIOS for things like RAM disks.

--
Lee A. Hart | Ring the bells that still can ring
814 8th Ave N | Forget the perfect offering
Sartell MN 56377 | There is a crack in everything
leeahart earthlink.net | That's how the light gets in -- Leonard Cohen

[Norberto Collado]

Thanks for the memory map hex addresses so that I can double check my decoder. 

 

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!

[Norberto Collado]

Received today the H89-Vero-board and it is the right size to prototype all the features that I will like to have with a lot of space. Attached are some pictures and I inserted on the Vero-board the H89-Serial Port just to see something on the board. I decided to have one H89 P512-P506 connector to use the H89 boards for testing before adding that feature to the vector board. The same connector will be configurable with jumpers to be P511-P505, so that I can test with the H89 Serial port, the H17 and the H67 before prototyping and to make troubleshooting.  easier.

 

I’m also thinking in adding one H8 2x25 pins connectors to enable the testing of the H8-RTC, H8-USB and H8-Speed board. See attached picture.

 

Baby steps feature enabling checklist:

(  ) 1. enabling basic features with; Z80 CPU, MTR90, 64K RAM, 2MHz clock and serial port. Prototype using the original 444-83, 444-66 and 444-61C OTP’s to verify basic functionality. If I can pass the H89 self-test then I’m in good shape.

(  ) 2. enable H17 controller and boot HDOS and run floppy drive diagnostics. If this works then everything below should be easy to implement.

(  ) 3. enable H67 and boot HDOS

(  ) 4. enable H89 Serial port on only 1 port (need to figure out the default port for normal operations. There are 3 ports and which one to select with the PC for file transfers)

(  ) 4a. replace 444-83 with new OPT and retest

(  ) 4b. replace 444-66 with new OPT and retest

(  ) 4c. replace 444-61C with new OTP and retest

(  ) 5. enable H89 Speed control for 2/4/8/16MHz (optional) Might use Ken’ speed board instead.

(  ) 6. enable H89 USB support (optional)

(  ) 7. enable H89 RTC support (optional)

(  ) 8. enable PS2 keyboard support (stretch goal)

(  ) 9. enable VGA support (stretch goal)

(  ) 10. Add two connectors to bring the Address, data lines and control lines to individual LED’s (PDP-8 style from CPU-Ville – picture attached) when single stepping.

(  ) 11. Layout board to minimum size possible

(  ) 12. Use the smallest PC chassis to support such board or use an instrument case as well.

Norberto

[Norberto Collado]

I’m still toying with this idea on the Vero board that I have, but on seconds thoughts it will be very easy to prototype on one of the wire-wrap H8 boards that Carroll put together a while back. If someone has one of this bare board, then I will like to buy it if the price is right or donate it for this project.

 

Thanks,

 

Norberto

 

[Norberto Collado]

Here is the H89-Proto-board! I do not think I have the space for the floppy controller, so I will use the original H89 floppy controller board instead for proof of concept. It will take time to assembled, but at least it will provide the ability to test replacement circuits and for ease in debugging any new change. I will start running the Z80 at 2MHz and then at 4MHz to ensure that I have a robust design.  

 

Norberto

 

[Norberto Collado]

I’m ready to burn a single EPROM with the MMS-IDE H89 Monitor + the H17 ROM contents to support this project. Is the mapping below correct;

 

0000-07FF Monitor ROM (U518)

1800-1FFF H17 ROM (U520) for hard-sector floppy disk controller 

 

MMS-IDE    starts at 0000H

H17 ROM starts at 1800H

 

See attached file for current mapping.

 

MMS-IDE starts at 000 hex

To 1FFF hex

 

H17 ROM starts at 1800 hex

To 1FFF hex.

 

Norberto

[Mark Garlanger]

I didn't look at the hex file, but this is from the text. Those are the two starting addresses - they match my emulator. But for the monitor ROM, it's 4k so it goes to 0xFFF, not 0x7FF, that you listed in one place nor the 0x1FFF you listed in the second spot.

Mark

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[Norberto Collado]

On the H89 OTP's I'm still debating if I should use one of the following IC's as a replacement. Feedback will be appreciated.

From Jameco 20 pin OTP;

http://www.jameco.com/1/1/25392-74s472-4k-bit-512-x-8-prom-high-speed-3-state-dip-20-74s-series.html

Price: $12.94

From Jameco 28 pin IC;

http://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?search_type=jamecoall&catalogId=10001&freeText=394986&langId=-1&productId=394986&storeId=10001&ddkey=http:StoreCatalogDrillDownView

Price: $1.95

Norbert

[Rob Doyle]

I'd go with the modern 27Cxx part. But - check the speeds carefully.
The old bipolar parts were pretty fast in their day.

Rob.

On 7/3/2013 12:04 AM, Norberto Collado wrote:
>
> On the H89 OTP's I'm still debating if I should use one of the following
> IC's as a replacement. Feedback will be appreciated.
>
> From Jameco 20 pin OTP;
> http://www.jameco.com/1/1/25392-74s472-4k-bit-512-x-8-prom-high-speed-3-state-dip-20-74s-series.html
>
> Price: $12.94

Bipolar nichrome? fusable link technology.

> From Jameco 28 pin IC;
>
> http://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?search_type=jamecoall&catalogId=10001&freeText=394986&langId=-1&productId=394986&storeId=10001&ddkey=http:StoreCatalogDrillDownView
>
> Price: $1.95
>

Low power CMOS floating-gate EPROM.

[Mark Garlanger]

Norberto,

   Wouldn't you need 8 of the 74s472 just for the monitor ROM? That would be over $100 just for that. Or am I misreading it.

Mark

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[Norberto Collado]

It is only 3-pcs. I'm got feedback on another email thread to think about using RAM chips instead and add some code to program them on power-ona and/or reset.

 

Norberto 

 

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!

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[Mark Garlanger]

Since the monitor rom is 4K Bytes, why would you not need 8 of these 4K bit parts? 

"512X8 4096 Bit TTL DIP-20 Prom"

As for using RAM instead of ROM, unless you create some type of write protection, it's not going to be functionally equivalent. Writes to that area will corrupt the image.

Mark

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[Norberto Collado]

These are for the Memory Map Decoder (RAM/ROM) and the I/O MAP decoder to eliminate complicated logic and keeping IC count to the minimum (replacement for 444-83, 444-42 and 444-43 OTP's.)

 

I combined the Monitor ROM and the H17 ROM into a single EPROM.

 

Norberto

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[Norberto Collado]

I agree! The speed is the "main" issue right now and going crazy as I move forward on the prototype. The original design is using a ROM to enable another ROM and speed is a factor to have a working solution. 

 

I think a workaround will be to inject wait states, but I love performance. I will continue with the proto-type by using the original parts and in the meantime I will keep evaluating for alternatives.

 

Thanks,

 

Norberto 

 

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!
From: Rob Doyle <radi...@gmail.com>
Date: Wed, July 03, 2013 8:45 am
To: se...@googlegroups.com

I'd go with the modern 27Cxx part. But - check the speeds carefully.
The old bipolar parts were pretty fast in their day.

Rob.

On 7/3/2013 12:04 AM, Norberto Collado wrote:
>
> On the H89 OTP's I'm still debating if I should use one of the following
> IC's as a replacement. Feedback will be appreciated.
>
> From Jameco 20 pin OTP;
> http://www.jameco.com/1/1/25392-74s472-4k-bit-512-x-8-prom-high-speed-3-state-dip-20-74s-series.html
>
> Price: $12.94

Bipolar nichrome? fusable link technology.

> From Jameco 28 pin IC;
>
> http://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?search_type=jamecoall&catalogId=10001&freeText=394986&langId=-1&productId=394986&storeId=10001&ddkey=http:StoreCatalogDrillDownView
>
> Price: $1.95
>

Low power CMOS floating-gate EPROM.

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[Rob Doyle]

I don't understand your part selection criteria -

You seem to be willing to program a fusable link PROM to do address
decoding...

What about a standard PLD? Can you program something like:

<http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_876539_-1>

Fast, cheap, low power, reprogrammable, etc

... just wondering.

Rob

[Norberto Collado]

I was thinking about it, but I'm not sure on how to fit 256 bytes of data into it. If I send out the hex data, is this something you can help me with? or point me into the right direction?

Thanks,

Norberto

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!
From: Rob Doyle <radi...@gmail.com>

[Rob Doyle]

With the bipolar PROM, the address decoding is done by a lookup table.

The PAL/GAL has "sum-of-product" device, not a straight lookup table.

A boolean sum is an 'OR gate'. A boolean product is a 'AND gate'.
Eventually you have to reduce the lookup table to logic equations in
sum-of-product format.

PALASM was to generate the files to program the devices. See:

http://en.wikipedia.org/wiki/PALASM
http://www.engr.uky.edu/~melham01/ee481/software.htm

(You can see the sum-of-product logic in the example at the right side
of the WIKI URL).

If you have the contents for the PROM it would be very simple to convert
this to logic equations in PALASM format. I can certainly help with that.

Many of these parts (PAL22V10 etc) used exactly the same bipolar fusable
link technology as the PROMs - so this isn't a big stretch.

I'll have to look around an see if I can still program those parts.

Do you have the PROM contents?

Rob.

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[Norberto Collado]

Hello Rob,

I do have the ROM contents and also I can program any of PALS and GALS without any issues (prefer the GALS). All ROM contents are inside my programmer, so I will send that shortly.

Thanks,

Norberto

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/51D51C16.6060301%40gmail.com.

[Norberto Collado]

U550 - 444-61

U516 - 444-83

U517 - 444-66

 

All hex files attached in zip file. I added a picture as well. If you need a high resolution picture just let me know.

 

If you can convert the logic to use a GAL that will be great.

 

Thanks,

 

Norberto

 

-----Original Message-----
From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Rob Doyle
Sent: Wednesday, July 03, 2013 11:54 PM
To: se...@googlegroups.com
Subject: Re: [sebhc] H89 on a Veroboard!

 

With the bipolar PROM, the address decoding is done by a lookup table.

[Rob Doyle]

One last thing...

Can you send a schematic - the PLD design will make more sense if I can
use the net names from the schematic...

Rob.

[Norberto Collado]

I do not have the net names yet. I can put them together once I get home. Right now I'm using the original H89 schematics from Les' website. Match the "U550, U516, U517" designations from the files to the H89 schematic. Attached is a picture of each OTP from the H89 schematics.

 

Norberto 

 

-------- Original Message --------
Subject: Re: [sebhc] H89 on a Veroboard!

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[Rob Doyle]

I'm working on the IO Map decoder for Norberto and I'm not sure what I'm
seeing. I'm try to document and check the device against the monitor
listing and there is a bunch of decoded IO that I can't find in the
monitor. Any help would be appreciated.

I know absolutely nothing about H8/H89 hardware...

; q7
; ROM address 0xdc - 0xdf
; This corresponds to IO addresses:
; 7ch-7fh (174q-177q) - Floppy Disk

This looks OK - but I also see floppy addresses (170q-171q) in the
monitor listing which doesn't seem to be decoded...

; q6
; ROM address 0xd8 - 0xdf
; This corresponds to IO addresses:
; 78h-7fh (170q-177q) - Cassette?

This one looks like it goes to the cassette device but the monitor
listing says the cassette address is 370q-377q and it doesn't match....

; q5
; ROM address 0x80 - 0x97 and 0x1c0 - 0x1c7
; This corresponds to IO addresses:
; 40h-57h (100q-127q) - Printer?
; e0h-e7h (340q-347q) - Printer?

This looks like printer (IO_LP netname). Is one of these the primary
printer address and the other an alternate printer address?
I don't see printer addresses in the monitor listing...

; q4
; ROM address 0x80 - 0x87, 0x90-0x9f, and 0x190-0x197
; This corresponds to IO addresses:
; 40h-47h (100q-100q) - Serial Port 0 ?
; 50h-5fh (120q-137q) - Serial Port 0 ?
; d0h-dfh (320q-337q) - Serial Port 0 ?

Are these all alternate addresses for serial port 0?
Is one of these the primary address?

; q3
; ROM address 0x80-0x8f, 0x98-0x9f, and 0x198-0x19f
; This corresponds to IO addresses:
; 40h-4fh (100q-117q) - Serial Port 1
; 58h-5fh (130q-137q) - Serial Port 1
; d8h-dfh (330q-337q) - Serial Port 1

Are these all alternate addresses for serial port 1?
Is one of these the primary address?

; q2
; ROM addresses 0x1c8-1cf
; This corresponds to IO addresses:
; e8h-efh (350q-357q) - System Console USART

This one looks OK.

; q1
; ROM address 0x1d0-0x1d1, 0x1da-0x1db
; This corresponds to IO addresses:
; f0h-f1h (360q-361q) - Front panel trap
; fah-fbh (372q-373q) - 8251 trap

It looks like the H89 emulates the H8 front panel and i8251 in
an NMI handler?

; q0
; ROM address - 0x58-0x59, 0x5b-0x5f, 0x1d2
; This corresponds to IO addresses:
; 38h-39h (070q-071q) - what is this?
; 3bh-3fh (073q-077q) - what is this?
; f2h (362q) - DIP Switch and Clock Control

Some of the IO addresses overlap which concerns me. I would have
expected that the IO addresses be unique but I'm guessing that there is
additional IO decoding on the IO cards.

The mapping between PROM addresses and IO addresses is odd because the
designers used PROM address A5 as a chip enable signal (see schematic).
If you remove A5, the PROM address and the decoded IO address are the same.

I would appreciate some comments to help me understand what I am seeing.

Thanks -

Rob.

[Mark Garlanger]

Which monitor listing are your looking at? (MTR-88, MTR-89, or MTR-90)

On Sat, Jul 6, 2013 at 1:42 PM, Rob Doyle <radi...@gmail.com> wrote:

I'm working on the IO Map decoder for Norberto and I'm not sure what I'm seeing.   I'm try to document and check the device against the monitor listing and there is a bunch of decoded IO that I can't find in the monitor.   Any help would be appreciated.

I know absolutely nothing about H8/H89 hardware...

; q7
; ROM address 0xdc - 0xdf
; This corresponds to IO addresses:
;   7ch-7fh (174q-177q)         - Floppy Disk

This looks OK - but I also see floppy addresses (170q-171q) in the monitor listing which doesn't seem to be decoded...

0x7c - 0x7f is the default for the hard-sectored controller. and I believe any controller that is in the far right slot (Z-89-47 and Z-89-67).

0x78 - 0x7b is the default for the soft-sectored controller (Z-89-37) or if the other controllers (Z-89-47 or Z-89-67) is on the left slot on the right side.

 

; q6
; ROM address 0xd8 - 0xdf
; This corresponds to IO addresses:
;   78h-7fh (170q-177q)         - Cassette?

This one looks like it goes to the cassette device but the monitor
listing says the cassette address is 370q-377q and it doesn't match....

I'll have to check, but I would assume it would be 0x78-0x7b.

 

; q5
; ROM address 0x80 - 0x97 and 0x1c0 - 0x1c7
; This corresponds to IO addresses:
;   40h-57h (100q-127q)         - Printer?
;   e0h-e7h (340q-347q)         - Printer?

This looks like printer (IO_LP netname). Is one of these the primary
printer address and the other an alternate printer address?
I don't see printer addresses in the monitor listing...

Don't think the first one is anything.

But the Octal - 340-347 is one of the serial ports on the 3 port serial board. The other 2 start at Octal 320 and 330.

 

; q4
; ROM address 0x80 - 0x87, 0x90-0x9f, and 0x190-0x197
; This corresponds to IO addresses:
;   40h-47h (100q-100q)         - Serial Port 0 ?
;   50h-5fh (120q-137q)         - Serial Port 0 ?
;   d0h-dfh (320q-337q)         - Serial Port 0 ?

Are these all alternate addresses for serial port 0?
Is one of these the primary address?

Not sure on the first 2, but 320 is the documented address for the serial port.

 

; q3
; ROM address 0x80-0x8f, 0x98-0x9f, and 0x198-0x19f
; This corresponds to IO addresses:
;   40h-4fh (100q-117q)         - Serial Port 1
;   58h-5fh (130q-137q)         - Serial Port 1
;   d8h-dfh (330q-337q)         - Serial Port 1

Are these all alternate addresses for serial port 1?
Is one of these the primary address?

Not sure on the first 2, but 330 is the documented address.

 

; q2
; ROM addresses 0x1c8-1cf
; This corresponds to IO addresses:
;   e8h-efh (350q-357q)         - System Console USART

This one looks OK.

yes, the Console Serial port, but on the H89 it's a UART not USART. It uses a 8250 chip.

 

; q1
; ROM address 0x1d0-0x1d1, 0x1da-0x1db
; This corresponds to IO addresses:
;    f0h-f1h (360q-361q)        - Front panel trap
;    fah-fbh (372q-373q)        - 8251 trap

It looks like the H89 emulates the H8 front panel and i8251 in
an NMI handler?

Yes, those accesses causes a NMI that are handled my the monitor ROM, not sure what would happen if those were accessed under CP/M when the monitor ROM is mapped out and is RAM instead.

 

; q0
; ROM address - 0x58-0x59, 0x5b-0x5f, 0x1d2
; This corresponds to IO addresses:
;    38h-39h (070q-071q)        - what is this?
;    3bh-3fh (073q-077q)        - what is this?
;    f2h     (362q)             - DIP Switch and Clock Control

Some of the IO addresses 

overlap which concerns me. I would have
expected that the IO addresses be unique but I'm guessing that there is
additional IO decoding on the IO cards.

Not sure what those first 2 addresses are, but 0xf2 is the documented 'General Purpose Port'. Reads are the value of the dips switch, and writes control various things. From my emulator source code:

    /// Enable Single Step Interrupt
    static const BYTE gpp_SingleStepInterrupt_c = 0x01;

    /// Enable the Timer Interrupt
    static const BYTE gpp_EnableTimer_c         = 0x02;

    /// Disable the ROM and map the RAM to the lower 8k.
    static const BYTE gpp_DisableROM_c          = 0x20;

    /// Side-select for the floppy drive (appears to be just for Hard-sectored controllers).
    static const BYTE gpp_SideSelect_c          = 0x40;

    /// Third party add-on for speed control
    static const BYTE gpp_4MHz_2MHz_Select_c    = 0x10;

The Magnolia Microsystem's 128k add-on also used various bits which conflict with third-party speed control. Which is one of the reasons I liked Norberto's plan to have another port be the speed control.

 

The mapping between PROM addresses and IO addresses is odd because the
designers used PROM address A5 as a chip enable signal (see schematic).
If you remove A5, the PROM address and the decoded IO address are the same.

Do you mean if A5 wasn't a '1', that the PROM chip would not be active?

 

I would appreciate some comments to help me understand what I am seeing.

Thanks -

Rob.

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[Glenn Roberts]

The H888/89/90 configuration guide might be helpful in deciphering switch and I/O settings…

 

http://sebhc.lesbird.com/documentation/hardware/HZ89/H-88-89-90_Cnf.zip

 

-          Glenn

 

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Mark Garlanger

Sent: Saturday, July 06, 2013 3:33 PM
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[Norberto Collado]

Power-up H89A prototype board, but somehow /IRQ at pin 20 on the CPU is always high. Any ideas?

 

[Norberto Collado]

Here is the system ROM/RAM schematics and let me know if you see any issues. If /IRQ on Z80 PIN 20 is not asserted, then I’m assuming that it is not reading properly the System ROM or cannot read/write from System RAM. At least I see the /CS on both the ROM and the RAM being asserted.

 

As long /IRQ is not enabled, then it cannot write to the H19 terminal.

 

L

 

 

 

System RAM

 

[Rob Doyle]

On 7/6/2013 12:33 PM, Mark Garlanger wrote:
> Which monitor listing are your looking at? (MTR-88, MTR-89, or MTR-90)

MTR-89.

What should I be looking at?

> On Sat, Jul 6, 2013 at 1:42 PM, Rob Doyle <radi...@gmail.com
> <mailto:radi...@gmail.com>> wrote:
>
> I'm working on the IO Map decoder for Norberto and I'm not sure what
> I'm seeing. I'm try to document and check the device against the
> monitor listing and there is a bunch of decoded IO that I can't find
> in the monitor. Any help would be appreciated.
>
> I know absolutely nothing about H8/H89 hardware...
>
> ; q7
> ; ROM address 0xdc - 0xdf
> ; This corresponds to IO addresses:
> ; 7ch-7fh (174q-177q) - Floppy Disk
>
> This looks OK - but I also see floppy addresses (170q-171q) in the
> monitor listing which doesn't seem to be decoded...
>
>
>
> 0x7c - 0x7f is the default for the hard-sectored controller. and I
> believe any controller that is in the far right slot (Z-89-47 and Z-89-67).

Yes. This the Q6 output below.

> 0x78 - 0x7b is the default for the soft-sectored controller (Z-89-37) or
> if the other controllers (Z-89-47 or Z-89-67) is on the left slot on the
> right side.

That makes sense. This output goes to the right slot so it is the soft-
sectored controller.

>
> ; q6
> ; ROM address 0xd8 - 0xdf
> ; This corresponds to IO addresses:
> ; 78h-7fh (170q-177q) - Cassette?
>
> This one looks like it goes to the cassette device but the monitor
> listing says the cassette address is 370q-377q and it doesn't match....
>
>
> I'll have to check, but I would assume it would be 0x78-0x7b.

The Configuration Guide says cassette is not supported with this PROM.
This output drives the 'IO_CASS_L' net which goes to the left slot. I
assumed that was the cassette but IO range matches soft sectored controller.

That makes sense now.

> ; q5
> ; ROM address 0x80 - 0x97 and 0x1c0 - 0x1c7
> ; This corresponds to IO addresses:
> ; 40h-57h (100q-127q) - Printer?
> ; e0h-e7h (340q-347q) - Printer?
>
> This looks like printer (IO_LP netname). Is one of these the primary
> printer address and the other an alternate printer address?
> I don't see printer addresses in the monitor listing...
>
>
>
> Don't think the first one is anything.
> But the Octal - 340-347 is one of the serial ports on the 3 port serial
> board. The other 2 start at Octal 320 and 330.

Is there a schematic or manual for the triple serial port thingy?
The config guide calls it a H-88-3, HA-88-3, or Z-89-11

Yes exactly. A5 is low when any output is decoded. Half of the chip
is used to generate a second chip enable for the PROM.

[Rob Doyle]

On 7/6/2013 1:36 PM, Glenn Roberts wrote:
> The H888/89/90 configuration guide might be helpful in deciphering

> switch and I/O settings�
>
> http://sebhc.lesbird.com/documentation/hardware/HZ89/H-88-89-90_Cnf.zip
>

Thanks. That's a huge help.

It mentions that there are TWO ROM decoders chips available (444-43 and
444-61) available. I'm using 444-61

Is there any reason NOT to support both decoder types in the PAL?

I think I could just add another input to select between the two - the
part should be large enough. Norberto could add a jumper plug to the board.

Does anyone have a ROM image for a 444-43 IO Decode ROM?

Rob.

[Mark Garlanger]

On Sun, Jul 7, 2013 at 12:14 AM, Rob Doyle <radi...@gmail.com> wrote:

On 7/6/2013 12:33 PM, Mark Garlanger wrote:

Which monitor listing are your looking at? (MTR-88, MTR-89, or MTR-90)

MTR-89.

What should I be looking at?

The MTR-90 is the one needed for both the Z-89-67 and Z-89-37 controllers,
otherwise you are limited to just the hard-sector controller and the Z-89-47.

 

On Sat, Jul 6, 2013 at 1:42 PM, Rob Doyle <radi...@gmail.com

<mailto:radi...@gmail.com>> wrote:

    I'm working on the IO Map decoder for Norberto and I'm not sure what
    I'm seeing.   I'm try to document and check the device against the
    monitor listing and there is a bunch of decoded IO that I can't find
    in the monitor.   Any help would be appreciated.

    I know absolutely nothing about H8/H89 hardware...

    ; q7
    ; ROM address 0xdc - 0xdf
    ; This corresponds to IO addresses:
    ;   7ch-7fh (174q-177q)         - Floppy Disk

    This looks OK - but I also see floppy addresses (170q-171q) in the
    monitor listing which doesn't seem to be decoded...



0x7c - 0x7f is the default for the hard-sectored controller. and I
believe any controller that is in the far right slot (Z-89-47 and Z-89-67).

Yes.  This the Q6 output below.

On Q6, you said it starts at 0x78, but for the far right slot, it's only 0x7c - 0x7f.

 

0x78 - 0x7b is the default for the soft-sectored controller (Z-89-37) or
if the other controllers (Z-89-47 or Z-89-67) is on the left slot on the
right side.

That makes sense. This output goes to the right slot so it is the soft-
sectored controller.

I think 0x78 - 0x7b is for the left one on the right side, not the right most slot.

 

    ; q6
    ; ROM address 0xd8 - 0xdf
    ; This corresponds to IO addresses:
    ;   78h-7fh (170q-177q)         - Cassette?

    This one looks like it goes to the cassette device but the monitor
    listing says the cassette address is 370q-377q and it doesn't match....


I'll have to check, but I would assume it would be 0x78-0x7b.

The Configuration Guide says cassette is not supported with this PROM.
This output drives the 'IO_CASS_L' net which goes to the left slot.  I assumed that was the cassette but IO range matches soft sectored controller.

That makes sense now.

Yes, only the MTR-88 supports the cassette controller.

 

    ; q5
    ; ROM address 0x80 - 0x97 and 0x1c0 - 0x1c7
    ; This corresponds to IO addresses:
    ;   40h-57h (100q-127q)         - Printer?
    ;   e0h-e7h (340q-347q)         - Printer?

    This looks like printer (IO_LP netname). Is one of these the primary
    printer address and the other an alternate printer address?
    I don't see printer addresses in the monitor listing...



Don't think the first one is anything.
But the Octal - 340-347 is one of the serial ports on the 3 port serial
board. The other 2 start at Octal 320 and 330.

Is there a schematic or manual for the triple serial port thingy?
The config guide calls it a H-88-3, HA-88-3, or Z-89-11

I think it may be up on Les's site, if not, we can scan it.
The H-88-3 was the first 3-port serial board, the HA-88-3 was an updated version of it.

The Z-89-11, has a parallel port, and 2 serial ports (one with the 8250, and one
with a different serial port.

 

    The mapping between PROM addresses and IO addresses is odd because the
    designers used PROM address A5 as a chip enable signal (see schematic).
    If you remove A5, the PROM address and the decoded IO address are
    the same.


Do you mean if A5 wasn't a '1', that the PROM chip would not be active?

Yes exactly.   A5 is low when any output is decoded.   Half of the chip
is used to generate a second chip enable for the PROM.

Hmm, strange.

 

    I would appreciate some comments to help me understand what I am seeing.

    Thanks -

    Rob.

    --

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[Norberto Collado]

Hello Rob,

The design is based on the MTR-90 Monitor to support the hard drive Z67 and
the soft sector controller Z37.

Thanks for all your help,

Norberto

-----Original Message-----
From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of
Rob Doyle
Sent: Saturday, July 06, 2013 10:15 PM
To: se...@googlegroups.com
Subject: Re: [sebhc] H89 IO Map - was H89 on a Veroboard!

[Norberto Collado]

Status:

 

Now using the MMS 2732A part and now pin 20 on the CPU is working. Somehow my new 27C1001 decoding circuit is not working. With the MMS Monitor, on the serial port I get some funny characters and then it clears the screen. The last character that I see is the ?2h before it clears. This is an indication that is transmitting fine and that it is getting the correct response from the H19 terminal. After that nothing happens, so I do not get the MMS: prompt. Typing characters on the H19 terminal causes no interrupts on pin 30 on the 8250 serial port controller.

 

Next steps is to use the MTR90 to see if that helps and check SW501 circuit.

 

Also during the wire-wrapping I found some many mistakes with the H89A schematics. I have been using both the Engineer Schematics and the H89A Schematics along with the H89 board to verify proper connections. I’m creating my own schematics as I go along. Also using the H1000 schematics to help out as well.

 

Norberto

[Norberto Collado]

Status:

 

Inserted MTR90 IC and still no “B:” prompt. Also on SW501, if I set to “0 – OFF state” switch 5, it starts to perform the memory test. I can see on the H19 display the self-test. The memory test is very stable and no issues so far (over 500 passes). Here are some pictures. So far the only mistake is with the 27C1001 decoding circuitry.

 

Can anyone help me in figuring out why I do not get the B”:” prompt when SW501-5 is on?

 

So far here is what is working;

 

1.       MTR90 ROM

2.       SW501 circuit

3.       RAM test is displaying 377377 octal which is 64K, so it is working.

4.       8250 Serial port

5.       444-83 - OTP

6.       444-66 - OTP

7.       444-61 – OTP

8.       Z80, bus address buffers & data bus

 

List to test:

 

1.       MTR90 Boot Menu

2.       Bank select

3.       Interrupts

4.       Single – Step and 2ms clock (I’m adding logic to either select 2ms or 1ms clocks)

 

Soon, I shall be able to convert a normal H19 terminal into an H89A computer.

 

Thanks,

 

Norberto

[Glenn Roberts]

Wow. Amazing work Norberto!

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Norberto Collado

Sent: Sunday, July 07, 2013 3:54 PM
To: se...@googlegroups.com

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[Dave McGuire]

Seconded. This is very, very cool.

-Dave

On 07/07/2013 04:18 PM, Glenn Roberts wrote:
> Wow. Amazing work Norberto!
>
> *From:*se...@googlegroups.com [mailto:se...@googlegroups.com] *On Behalf
> Of *Norberto Collado
> *Sent:* Sunday, July 07, 2013 3:54 PM
> *To:* se...@googlegroups.com
> *Subject:* RE: [sebhc] H89 on a Veroboard!
>
> Status:
>
> Inserted MTR90 IC and still no �B:� prompt. Also on SW501, if I set to
> �0 � OFF state� switch 5, it starts to perform the memory test. I can

> see on the H19 display the self-test. The memory test is very stable and
> no issues so far (over 500 passes). Here are some pictures. So far the
> only mistake is with the 27C1001 decoding circuitry.
>

> Can anyone help me in figuring out why I do not get the B�:� prompt when

> SW501-5 is on?
>
> So far here is what is working;
>
> 1.MTR90 ROM
>
> 2.SW501 circuit
>

> 3.RAM test is displaying 377377 octal which is 64K, so it is working.

>
> 4.8250 Serial port
>
> 5.444-83 - OTP
>
> 6.444-66 - OTP
>

> 7.444-61 � OTP
>
> 8.Z80, bus address buffers & data bus

>
> List to test:
>
> 1.MTR90 Boot Menu
>
> 2.Bank select
>
> 3.Interrupts
>

> 4.Single � Step and 2ms clock (I�m adding logic to either select 2ms or

> 1ms clocks)
>
> Soon, I shall be able to convert a normal H19 terminal into an H89A
> computer.
>
> Thanks,
>
> Norberto
>
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>
>

--
Dave McGuire, AK4HZ
New Kensington, PA

[Norberto Collado]

So far, the only thing that I can do is run the H89 memory test and is still passing with the MTR90 Monitor. Still cannot get the “B:” prompt.

 

Here is an update to the ROM schematic.

 

 

[Norberto Collado]

So far what I found is that the console interrupt is on INT3 L line. My H89A schematic shows on INT5 L line. I corrected such issue, but still no ”B:” prompt. Also I increased the freq to 4MHZ and the board failed to run the memory self-test. What  can tell is that I have schematics that might have a wiring mistake so it will take time to figure it out. I will proceed to print the schematics in Les’ website because the ones I have might not be correct.

 

Norberto

[dwight elvey]

Is it hanging at a particular address or has it just lost and
jumping out of the ROM code entirely?
If you don't have a scope or analyzer, you can hook
a switch to the wait line to freeze the processor
to look at the address line. From there, you may be able to figure
what it is waiting on.
Dwight

 

---

From: norberto...@koyado.com
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!
Date: Sun, 7 Jul 2013 22:29:51 -0700

So far what I found is that the console interrupt is on INT3 L line. My H89A schematic shows on INT5 L line. I corrected such issue, but still no ”B:” prompt. Also I increased the freq to 4MHZ and the board failed to run the memory self-test. What  can tell is that I have schematics that might have a wiring mistake so it will take time to figure it out. I will proceed to print the schematics in Les’ website because the ones I have might not be correct.

 

Norberto

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[Norberto Collado]

The only sections on the board that are not fully tested are the interrupts and the 2ms counter. I do have the scope to debug the board and do not have a logic analyzer.

 

I will scope out this area to find out if any wiring errors.

 

Norberto 

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/BLU178-W3531E2F7C931B3E0FE503CA3780%40phx.gbl.

[dwight elvey]

It might be a problem with a missing interrupt but I really think
you should do the WAIT pin. It will tell you what code is hanging
and from that what is missing.
Dwight

 

---

From: norberto...@koyado.com
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Mon, 8 Jul 2013 16:31:19 -0700

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/20130708163119.1321cca37f09b4ab87c5049afdc8ceaa.233b63964f.wbe%40email09.secureserver.net.

[Norberto Collado]

I found that U557 pin 11 is always low. I see the CPU interrupt line asserted, but B-IORQ is always high, so the interrupt is never serviced. I took out the U506 flip-flop and now on power-on I get the single beep on the H19 terminal. If I power-on both the H19 terminal and the H89 proto board at the same time, then I get the double beep as the original H89 system does.

 

This brings me a step closer to the H89 prompt.

 

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/BLU178-W375459BD875C48A8462D96A3790%40phx.gbl.

[Norberto Collado]

After reviewing the H-88-89-90_configuration_Guide, it references that U562 must be a 74S132 instead of the 74LS132. I updated to the 74S132 part and now the memory test, it is running when the CPU clock is at 4MHz. Now 2/4MHz are working fine, but still no “B:” prompt.

 

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/005401ce7c59%2428418840%2478c498c0%24%40koyado.com.

[Norberto Collado]

Definitively something wrong with the interrupts logic, but cannot find any wiring issue. Also I tied the 2ms clock to the CPU WAIT signal and it still doing the same thing, so it is not a timing issue. In this mode, the memory self-test runs but at a low rate without any issues.

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/005d01ce7c63%24cb58bd00%24620a3700%24%40koyado.com.

[dwight elvey]

Hi
 I don't think you understood my comment about the WAIT signal.
I meant that you should connect a physical switch to it, such that you'd
ground the pin.
The idea is that you'd let it run until your sure it has reach the point it
hangs. You'd then switch the WAIT pin to ground.
This stops the processor with the addresses set to some location.
You then use your scope or meter to read the address.
Hopefully it is someplace in the ROM. You look at the ROM
code and then note what it was looping on and waiting for.
I suspect it is an interrupt related issue but it helps to know which
it is expecting.
By looking at the location in the boot code where it stopped, you
can better trace down what it hung on.
Dwight

 

---

From: norberto...@koyado.com
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Mon, 8 Jul 2013 23:26:32 -0700

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/006601ce7c6d%24418a3860%24c49ea920%24%40koyado.com.

[dwight elvey]

I don't know why it is double posting?
Anyway, the reason it is not servicing the interrupt is
most likely that the interrupts are turned off in the code.
That is why it is important to see where in the code it
is.
Dwight

 

---

From: dke...@hotmail.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Tue, 9 Jul 2013 06:20:29 -0700

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/BLU178-W44EC7209164812DC29024FA3790%40phx.gbl.

[j bensadon]

Hi Norberto,

I've recently bought a cheap Logic Analyzer from Aliexpress.
I bought an 8 channel Salaea for $20 delivered.  Worth every penny.

I suggest you search around for the 16 channel Salaea.

:)J

---

From: norberto...@koyado.com
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Mon, 8 Jul 2013 16:31:19 -0700

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/20130708163119.1321cca37f09b4ab87c5049afdc8ceaa.233b63964f.wbe%40email09.secureserver.net.

[dwight elvey]

I don't think he needs anything more than the scope.
There are two reasons for the interrupt being turned off.
One is that he is in a section of code that needs to turn the interrupts
off for determinism.
The other is that an interrupt was generated that didn't get the correct
vector address and has not executed a IRET to reset the interrupt enable.
This is why I want him to see where in the code it is hanging.
Dwight

---

From: jben...@hotmail.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Tue, 9 Jul 2013 23:41:11 +0000

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/SNT145-W8F83ED5BCE40C014A7EFABB790%40phx.gbl.

[Norberto Collado]

Hi,

 

Thanks for the info and I will order the 16 channel Salaea Logic Analyzer. The price is great!

 

Thanks a lot!

[Mark Garlanger]

I never saw that site. Have you ordered many things from Aliexpress? The prices almost look too good to be real.

Thanks,

  Mark

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/SNT145-W8F83ED5BCE40C014A7EFABB790%40phx.gbl.

[Norberto Collado]

Hello Dwight,

 

I bought a switch to do the test tonight. This will be the test procedure and feel free to change if needed;

 

1. Power-up board

2. Wait

3. Enable wait switch

4. Capture with the scope the state of all the 16 address lines.

5. Disabled wait switch and wait

6. Enable wait switch

7. Capture with the scope the state of all the 16 address lines.

8. Power down board

9. Remove 2ms interrupt IC

10. Power-on board

11. Wait for the beep

12. Enable wait switch

13. Capture with the scope the state of all the 16 address lines.

14. Disable wait switch

15. Enable wait switch and wait

16. Capture with the scope the state of all the 16 address lines.

16. Send out data for review

 

Thanks,

 

Norberto

-------- Original Message --------
Subject: RE: [sebhc] H89 on a Veroboard!
From: dwight elvey <dke...@hotmail.com>

Date: Tue, July 09, 2013 5:28 pm
To: "se...@googlegroups.com" <se...@googlegroups.com>

I don't think he needs anything more than the scope.
There are two reasons for the interrupt being turned off.
One is that he is in a section of code that needs to turn the interrupts
off for determinism.
The other is that an interrupt was generated that didn't get the correct
vector address and has not executed a IRET to reset the interrupt enable.
This is why I want him to see where in the code it is hanging.
Dwight

---

From: jben...@hotmail.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Tue, 9 Jul 2013 23:41:11 +0000

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/BLU178-W6B5D6505E04C196104C8CA37A0%40phx.gbl.

[Glenn Roberts]

There are some real caveats about the site

 

http://www.trustpilot.com/review/www.aliexpress.com

 

the deals do look “too good to be true” on some stuff…

 

 

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Mark Garlanger

Sent: Tuesday, July 09, 2013 9:02 PM
To: se...@googlegroups.com

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/CAAjkm79ZoO%2B5djNwXFd3hC0fmi6o7PKcUagDiDTm66PVgBHLog%40mail.gmail.com.

[Mark Garlanger]

The 8-channel "Saleae" logic analyzers are as low as $3.33.  But on Saleae's site, that is $149.99. I 'chatted' with one of the sellers that was selling it for about $8, I asked if it was an official Saleae, since it didn't look like the ones on there site. He said it was not official, but was his "DIY" item. But the picture looked identical to other sellers on the Aliexpress site. I asked if it was totally compatible with the Saleae's software or if it had different software. He said it was totally compatible.

For $8, I may just try it.

Mark

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/004c01ce7d0e%245cdd6370%2416982a50%24%40gmail.com.

[Dave McGuire]

All of these, including the Saleae, are derivatives of a "hobbyist"
design (quoted because the line is very fine these days) that floated
around several years ago. Doing this in an FPGA borders on the trivial,
so someone did it. ;) It has been cloned over and over and over. I'd
say it'll work just fine, or at least as well as the Saleae does.

These are by no means real test instruments, but they can be handy if
the job is simple enough. I keep one (one of the clones) in my desk
drawer in my office, for quick-and-dirty "is this I2C bus doing what
it's supposed to be doing?" type of debugging when I'm working on
firmware. If something looks really fishy, I go over to the lab and use
real equipment.

For $3.33, or even $8, or even $49.95 (what I paid for mine), this is
a no-brainer if you ask me.

-Dave

On 07/09/2013 10:13 PM, Mark Garlanger wrote:
> The 8-channel "Saleae" logic analyzers are as low as $3.33. But on
> Saleae's site, that is $149.99. I 'chatted' with one of the sellers that
> was selling it for about $8, I asked if it was an official Saleae, since
> it didn't look like the ones on there site. He said it was not official,
> but was his "DIY" item. But the picture looked identical to other
> sellers on the Aliexpress site. I asked if it was totally compatible
> with the Saleae's software or if it had different software. He said it
> was totally compatible.
>
> For $8, I may just try it.
>
> Mark
>
>
>
> On Tue, Jul 9, 2013 at 8:39 PM, Glenn Roberts <glenn.f...@gmail.com

> <mailto:glenn.f...@gmail.com>> wrote:
>
> There are some real caveats about the site____
>
> __ __
>
> http://www.trustpilot.com/review/www.aliexpress.com____
>
> __ __
>
> the deals do look �too good to be true� on some stuff�____
>
> __ __
>
> __ __
>
> __ __
>
> *From:*se...@googlegroups.com <mailto:se...@googlegroups.com>
> [mailto:se...@googlegroups.com <mailto:se...@googlegroups.com>] *On
> Behalf Of *Mark Garlanger
> *Sent:* Tuesday, July 09, 2013 9:02 PM
> *To:* se...@googlegroups.com <mailto:se...@googlegroups.com>
> *Subject:* Re: [sebhc] H89 on a Veroboard!____
>
> __ __

>
> I never saw that site. Have you ordered many things from Aliexpress?
> The prices almost look too good to be real.
>

> Thanks,____
>
> Mark____
>
> __ __

>
> On Tue, Jul 9, 2013 at 6:41 PM, j bensadon <jben...@hotmail.com

> <mailto:jben...@hotmail.com>> wrote:____

>
> Hi Norberto,
>
> I've recently bought a cheap Logic Analyzer from Aliexpress.
> I bought an 8 channel Salaea for $20 delivered. Worth every penny.
>
> I suggest you search around for the 16 channel Salaea.
>
> :)J
>
> ____
>

> ------------------------------------------------------------------------
>
> From: norberto...@koyado.com <mailto:norberto...@koyado.com>
> To: se...@googlegroups.com <mailto:se...@googlegroups.com>
> Subject: RE: [sebhc] H89 on a Veroboard!____
>
> Date: Mon, 8 Jul 2013 16:31:19 -0700____

>
> The only sections on the board that are not fully tested are the
> interrupts and the 2ms counter. I do have the scope to debug the

> board and do not have a logic analyzer. ____
>
> ____
>
> I will scope out this area to find out if any wiring errors.____
>
> ____
>
> Norberto ____

>
> -------- Original Message --------
> Subject: RE: [sebhc] H89 on a Veroboard!
> From: dwight elvey <dke...@hotmail.com
> <mailto:dke...@hotmail.com>>
> Date: Mon, July 08, 2013 6:37 am
> To: "se...@googlegroups.com <mailto:se...@googlegroups.com>"
> <se...@googlegroups.com <mailto:se...@googlegroups.com>>____
>
> Is it hanging at a particular address or has it just lost and
> jumping out of the ROM code entirely?
> If you don't have a scope or analyzer, you can hook
> a switch to the wait line to freeze the processor
> to look at the address line. From there, you may be able to figure
> what it is waiting on.
> Dwight
>
> ____
>

> ------------------------------------------------------------------------

>
> From: norberto...@koyado.com
> <mailto:norberto...@koyado.com>
> To: se...@googlegroups.com <mailto:se...@googlegroups.com>
> Subject: RE: [sebhc] H89 on a Veroboard!
> Date: Sun, 7 Jul 2013 22:29:51 -0700____
>
> So far what I found is that the console interrupt is on INT3 L
> line. My H89A schematic shows on INT5 L line. I corrected such

> issue, but still no �B:� prompt. Also I increased the freq to

> 4MHZ and the board failed to run the memory self-test. What can
> tell is that I have schematics that might have a wiring mistake
> so it will take time to figure it out. I will proceed to print

> the schematics in Les� website because the ones I have might not
> be correct.____
>
> ____
>
> Norberto____

>
>
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--

[Norberto Collado]

Hello Dwight,

 

You nailed the issue with your comment about getting the incorrect vector address and that was the case. I went back to the proto board and found that I never wired the output of U558 to the Z80 data bus. I added the connections and now I get the “H:” prompt. J Cool!!!

 

Thanks for all your feedback and support to guide me into finding the issue.

 

I tested some of the MTR90 commands without any issues. Tonight I shall sleep better.

 

Next steps is to enable the H17 controller to boot HDOS and CP/M from the 5.25” floppy drive. I do have some spares IC’s that Ken gave me a while back.

Then add the second serial port, USB port and then finally the Z67 controller to have a fully functional system. Also as a stretch goal, I will add the Z37 controller.

 

Thanks, thanks, thanks, thanks, thanks, …….

 

Norberto

 

 

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of dwight elvey
Sent: Tuesday, July 09, 2013 5:28 PM
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

 

I don't think he needs anything more than the scope.

[Dave McGuire]

This is fantastic, congratulations!

-Dave

On 07/10/2013 01:01 AM, Norberto Collado wrote:
> Hello Dwight,
>
> You nailed the issue with your comment about getting the incorrect
> vector address and that was the case. I went back to the proto board and
> found that I never wired the output of U558 to the Z80 data bus. I added

> the connections and now I get the �H:� prompt. JCool!!!

>
> Thanks for all your feedback and support to guide me into finding the issue.
>
> I tested some of the MTR90 commands without any issues. Tonight I shall
> sleep better.
>
> Next steps is to enable the H17 controller to boot HDOS and CP/M from

> the 5.25� floppy drive. I do have some spares IC�s that Ken gave me a

> while back.
>
> Then add the second serial port, USB port and then finally the Z67
> controller to have a fully functional system. Also as a stretch goal, I
> will add the Z37 controller.
>

> Thanks, thanks, thanks, thanks, thanks, ��.
>
> Norberto
>
> *From:*se...@googlegroups.com [mailto:se...@googlegroups.com] *On Behalf
> Of *dwight elvey
> *Sent:* Tuesday, July 09, 2013 5:28 PM
> *To:* se...@googlegroups.com
> *Subject:* RE: [sebhc] H89 on a Veroboard!

>
> I don't think he needs anything more than the scope.
> There are two reasons for the interrupt being turned off.
> One is that he is in a section of code that needs to turn the interrupts
> off for determinism.
> The other is that an interrupt was generated that didn't get the correct
> vector address and has not executed a IRET to reset the interrupt enable.
> This is why I want him to see where in the code it is hanging.
> Dwight
>

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>


--

[Glenn Roberts]

Amazing.  Great to see this very complex project come to life!

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[j bensadon]

I only ordered my 8 channel (wish I did the 16 channel) from them. 
No problem in my single order, it came about 3-4 weeks later as expected from China.
Searching the site now, there's some very cheap deals, I can't believe it either.
I don't work for that site and can't endorse it with my single purchase, but it's not a lot of money.
PS. The site looks to be legitimate, they sent me some follow up requests for feedback.

There is another site that took my $50 and never delivered the product.  I don't mind black listing them.
But  I usually don't post black lists. 

Josh

---

Date: Tue, 9 Jul 2013 20:01:46 -0500
Subject: Re: [sebhc] H89 on a Veroboard!
From: garl...@gmail.com
To: se...@googlegroups.com

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/CAAjkm79ZoO%2B5djNwXFd3hC0fmi6o7PKcUagDiDTm66PVgBHLog%40mail.gmail.com.

[j bensadon]

Wow, after reading all that stuff about Alibaba, I will count myself lucky to have gotten an honest deal.

I see a lot of these Salaea Logic Analyzers on Ebay too.   I've heard of scams on Ebay but have not been "bitten" yet.

My main advice was how useful this cheap logic analyzer was.  It samples at up to 24 Megasamples per second, that gives you a 40nSec resolution, good enough to capture any glitch you might see on these 8 bit systems.   It really helped me out to track down a logic error in a wait state circuit I was putting together for an 8080A cpu.  I was able to follow along the Clock, Sync, DBIN, etc lines and fixed my logic.  It's funny how 8 channels get used very quickly when you trace the CPU activity.  I'll be upgrading to the 16 channel soon.

:)J

---

From: glenn.f...@gmail.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Tue, 9 Jul 2013 21:39:47 -0400

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/004c01ce7d0e%245cdd6370%2416982a50%24%40gmail.com.

[j bensadon]

Oh, one more point.  I think these cheap deals are for knock offs, aka copies, aka clones.

I didn't realize it when I bought mine.   Sorry, I should have said this earlier.  I was more focused on ends rather than means.

---

Date: Tue, 9 Jul 2013 21:13:18 -0500

Subject: Re: [sebhc] H89 on a Veroboard!

From: garl...@gmail.com
To: se...@googlegroups.com

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/CAAjkm78pfK8wsoiC%3DAHoWKJOv2iRjLaWdFVcR9uZX%2BWvB_mN4A%40mail.gmail.com.

[j bensadon]

Sweet!  It's a great feeling to conquer these problems!

---

From: norberto...@koyado.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Tue, 9 Jul 2013 22:01:43 -0700

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[Mark Garlanger]

No problem. They looked like they weren't the official Saleae ones, but since Dave mentioned that all of these are based off a hobbyist's design from years ago, I don't feel bad for getting one of the cheap ones, since it was 'stolen' from that company.

Thanks for the info. I really didn't want to spend $150 on it.

Mark

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/SNT145-W135F7DC85EA63D963F00299BB7A0%40phx.gbl.

[dwight elvey]

Just curious, who's software does it use? Is it a rip-off or is it newly created
software.
It is obvious that the major cost in the development is the creation of the software
and not the small chunk of hardware.
Dwight

---

From: jben...@hotmail.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Wed, 10 Jul 2013 17:35:20 +0000

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/SNT145-W135F7DC85EA63D963F00299BB7A0%40phx.gbl.

[Dave McGuire]

On 07/10/2013 02:30 PM, dwight elvey wrote:
> Just curious, who's software does it use? Is it a rip-off or is it newly
> created
> software.

There are three or four programs out there to drive these units. They
are all open source, just like the design of the hardware.

> It is obvious that the major cost in the development is the creation of
> the software and not the small chunk of hardware.

I must disagree here. The hardware itself is simple, but the FPGA
programming is a lot of work, much more so than the (very simple)
software to drive the unit.

-Dave

[j bensadon]

I have never done FPGA programming, but I would agree with Dave since I have had experience writing this kind of software.  My software was to display a 4 channel oscilloscope from data gathered by a PIC processor and sent to the PC via RS-232 at 38,400 baud.  Time resolution was 1ms, Voltage range/resolution 0-5V in 128 steps.

I had my software running in about 1 week.  The software for this analyzer is better, but I would say it's no more than 1 month's work.

> Date: Wed, 10 Jul 2013 14:34:54 -0400
> From: mcg...@neurotica.com

> To: se...@googlegroups.com
> Subject: Re: [sebhc] H89 on a Veroboard!
>

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[Norberto Collado]

My plan for the new H89 is to keep the board size small as much as possible. Then stack on top the H17 controller, the Z67, the serial port, and the Z37. Similar to the attached picture.

 

I will appreciated any feedback before I start working on the board layout.

 

Norberto

 

[Norberto Collado]

I replaced the 27C32 EPROM with a single 27C64 EPROM with the MTR90 and the H17 FW. On power-on nothing works, so it seems that is not reading the EPROM properly. 

 

The only difference is that the 27C32 is 150ns and the 27C64 is 70ns, besides having the A12 address line.

 

Any ideas?

 

Thanks,

 

Norberto

[jmcg...@windstream.net]

70ns exceeds the 150ns spec and is not the problem.  I did not compare pinouts; but, sometimes the pinouts and especially the logic levels of other control signals like CS versus /CS happen.  If you haven't already done this I'd review the pinouts for both chips.  Otherwise no reason in hardware that it should not work.  After that I'd look at the EPROM contents especially if you combined more than one EPROM contents into the new 64K chip.

 

Joe

 

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[j bensadon]

Every time I have a head scratching problem, I try adding another decoupling capacitor.

It seems to fix most electronic and marital problems. (joke)

:)J

---

From: norberto...@koyado.com
To: se...@googlegroups.com

Subject: RE: [sebhc] H89 on a Veroboard!

Date: Fri, 12 Jul 2013 00:03:37 -0700

[Jack Rubin]

Norby,

 

Sorry if I’m not keeping up with you, but I’m not sure about the final terminal output – will you be feeding the H19 terminal board from your serial port or will there be yet another layer that does H89/H19 terminal emulation so that you could use a PC keyboard and LCD monitor to eliminate the CRT? Or maybe add Vince Briel’s PockeTerm as a layer?

 

Great work!

 

Best,

Jack

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Norberto Collado
Sent: Friday, July 12, 2013 1:19 AM
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

 

My plan for the new H89 is to keep the board size small as much as possible. Then stack on top the H17 controller, the Z67, the serial port, and the Z37. Similar to the attached picture.

---

No virus found in this message.
Checked by AVG - www.avg.com
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[j bensadon]

Oh, btw, I said decoupling capacitors because a 70nS device is likely to cause more rail noise than 150ns.

I'm guessing you've already verified the EPROM contents and have done something with the A12 line etc.
Also, just for sanity sake, tried another 27C64 chip? etc.  Sorry for not keeping up with the conversation, but I'm guessing you are just writting the 27C32 contents to the 27C64?  Or is there more?

---

From: norberto...@koyado.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Fri, 12 Jul 2013 00:03:37 -0700

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[Norberto Collado]

Adding a PC keyboard is easy to do for me. Adding video is a new area for me because I never play with it. I will like to do my own hardware video design. The pockterm seems to be the easy path right now. The main board will have a jumper to select a connection to the H19 terminal or to the Pockterm board. I do have the pockterm board to enable such functionality and it will be another layer for this project. Also I will add the HSFE board to the H17 controller to support 3.5" floppy drives.

Norberto

-------- Original Message --------
Subject: RE: [sebhc] H89 on a Veroboard!

From: Jack Rubin <j...@ckrubin.us>
Date: Fri, July 12, 2013 6:51 am
To: "se...@googlegroups.com" <se...@googlegroups.com>

Norby,

 

Sorry if I’m not keeping up with you, but I’m not sure about the final terminal output – will you be feeding the H19 terminal board from your serial port or will there be yet another layer that does H89/H19 terminal emulation so that you could use a PC keyboard and LCD monitor to eliminate the CRT? Or maybe add Vince Briel’s PockeTerm as a layer?

 

Great work!

 

Best,

Jack

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Norberto Collado

Sent: Friday, July 12, 2013 1:19 AM

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

My plan for the new H89 is to keep the board size small as much as possible. Then stack on top the H17 controller, the Z67, the serial port, and the Z37. Similar to the attached picture.

 

I will appreciated any feedback before I start working on the board layout.

 

Norberto

 

---

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[Norberto Collado]

I will check it out tonight. However I do have the 128K RAM connected and it is working fine. I ran memory test last night using a 5MHz osc without any issues.

Norberto

-------- Original Message --------
Subject: RE: [sebhc] H89 on a Veroboard!

From: j bensadon <jben...@hotmail.com>
Date: Fri, July 12, 2013 7:16 am
To: "se...@googlegroups.com" <se...@googlegroups.com>

Oh, btw, I said decoupling capacitors because a 70nS device is likely to cause more rail noise than 150ns.

I'm guessing you've already verified the EPROM contents and have done something with the A12 line etc.
Also, just for sanity sake, tried another 27C64 chip? etc.  Sorry for not keeping up with the conversation, but I'm guessing you are just writting the 27C32 contents to the 27C64?  Or is there more?

---

From: norberto...@koyado.com

To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

Date: Fri, 12 Jul 2013 00:03:37 -0700

I replaced the 27C32 EPROM with a single 27C64 EPROM with the MTR90 and the H17 FW. On power-on nothing works, so it seems that is not reading the EPROM properly. 

 

The only difference is that the 27C32 is 150ns and the 27C64 is 70ns, besides having the A12 address line.

 

Any ideas?

 

Thanks,

 

Norberto

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[geneb]

On Fri, 12 Jul 2013, Norberto Collado wrote:

> Adding a PC keyboard is easy to do for me. Adding video is a new area for me
> because I never play with it. I will like to do my own hardware video
> design. The pockterm seems to be the easy path right now. The main board
> will have a jumper to select a connection to the H19 terminal or to the
> Pockterm board. I do have the pockterm board to enable such functionality
> and it will be another layer for this project. Also I will add the HSFE
> board to the H17 controller to support 3.5" floppy drives.

Have you given any thought to just attaching a PockeTerm to it? It
currently has VT-100 support but I don't suppose adding H-19 to that would
be terribly difficult.

It's made by Vince Briel - he makes a number of really slick
retro-computerish things like the MicroAltair and MicroKIM.

http://www.brielcomputers.com/wordpress/?cat=25

You could add mounting holes to your new H-89 so the PockeTerm would live
on it light a daughterboard of sorts...

g.


--
Proud owner of F-15C 80-0007
http://www.f15sim.com - The only one of its kind.
http://www.diy-cockpits.org/coll - Go Collimated or Go Home.
Some people collect things for a hobby. Geeks collect hobbies.

ScarletDME - The red hot Data Management Environment
A Multi-Value database for the masses, not the classes.
http://scarlet.deltasoft.com - Get it _today_!

[Chris Elmquist]

I think it would be cool if the "base board" can have the same
functionality on it as the original H89 board has-- and then the daughter
boards end up being equiv to any plug-in boards we would normally add
to the H89 backplane.

So, I guess this means the serial port would need to be on the base
board but floppy, hard disk, etc. would be on the daughter boards that
stack on top.

I'm happy to provide the code for the AVR micro that goes in the HSFE
so that we can integrate that AVR directly into your H17 equiv design.

(And slightly off the topic, I have one of these coming,

http://www.ebay.com/itm/370843390871?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1439.l2649

to see if I can make it work with HSFE to give us "solid-state" 3.5"
floppies )

A long time ago we talked about modifying Vince's PocketTerm to do H19
modes but I'm not sure anyone has finished that effort yet. I never
got started myself even though I have had a PocketTerm here for a very
long time. I would agree that that is a pretty short path to getting
VGA video out with PC keyboard going in.

Chris

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[geneb]

On Fri, 12 Jul 2013, Chris Elmquist wrote:

>
>
> I'm happy to provide the code for the AVR micro that goes in the HSFE
> so that we can integrate that AVR directly into your H17 equiv design.
>

Now tht would be insanely cool. :)

> A long time ago we talked about modifying Vince's PocketTerm to do H19
> modes but I'm not sure anyone has finished that effort yet. I never
> got started myself even though I have had a PocketTerm here for a very
> long time. I would agree that that is a pretty short path to getting
> VGA video out with PC keyboard going in.
>

It probably wouldn't be that hard to craft up the H-19 character set as
well. H-80 with _color_ would just kick ass. :)

[Norberto Collado]

The plan is to integrate the Poketerm into the board. I do have the schematics and all the parts are available from Jameco.

 

Norbeto 

 

-------- Original Message --------
Subject: RE: [sebhc] H89 on a Veroboard!

From: geneb <ge...@deltasoft.com>
Date: Fri, July 12, 2013 7:37 am
To: se...@googlegroups.com

On Fri, 12 Jul 2013, Norberto Collado wrote:

> Adding a PC keyboard is easy to do for me. Adding video is a new area for me
> because I never play with it. I will like to do my own hardware video
> design. The pockterm seems to be the easy path right now. The main board
> will have a jumper to select a connection to the H19 terminal or to the
> Pockterm board. I do have the pockterm board to enable such functionality
> and it will be another layer for this project. Also I will add the HSFE
> board to the H17 controller to support 3.5" floppy drives.

Have you given any thought to just attaching a PockeTerm to it? It
currently has VT-100 support but I don't suppose adding H-19 to that would
be terribly difficult.

It's made by Vince Briel - he makes a number of really slick
retro-computerish things like the MicroAltair and MicroKIM.

http://www.brielcomputers.com/wordpress/?cat=25

You could add mounting holes to your new H-89 so the PockeTerm would live
on it light a daughterboard of sorts...

g.


--
Proud owner of F-15C 80-0007
http://www.f15sim.com - The only one of its kind.
http://www.diy-cockpits.org/coll - Go Collimated or Go Home.
Some people collect things for a hobby. Geeks collect hobbies.

ScarletDME - The red hot Data Management Environment
A Multi-Value database for the masses, not the classes.
http://scarlet.deltasoft.com - Get it _today_!

[Norberto Collado]

Found issue with pin 27 and pin 1 of the 27C64A which were low and needs to be asserted high. The board is reading properly the MTR90 and the H17 address space on same EPROM. I use the view command to display the EPROM contents without any issues at address 0x00 and 0x1800.

 

Now I believe I have a fully functional H89 proto board with a single EPROM and a single RAM IC’s. Thanks to the MTR-90 diagnostics I was able to flush out design and wiring issues.

 

Next step is to add the H17 support and boot HDOS, and run the diagnostics to verify that the whole design is correct before doing any PCB work.

 

Norberto J

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/20130712072614.1321cca37f09b4ab87c5049afdc8ceaa.c3f066324c.wbe%40email09.secureserver.net.

[Glenn Roberts]

Congratulations Norberto, quite an accomplishment!

 

Speaking of all night Heathkit projects I note the time stamp on your message is 3:33 AM !!!

 

-          Glenn

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/006001ce7f9b%2439241ed0%24ab6c5c70%24%40koyado.com.

[Norberto Collado]

Once you are in, it is hard to get out and times goes fast! J

 

I just enabled the H17 board to the H89 proto board and when I type Boot1 (in my case), it enables the floppy drive (light is on), does a  seek and then you can hear the drive doing retries and then the “H: “ prompt comes back (pictures attached). More troubleshooting to do. Not sure if it is related to the memory decoder for the H17 RAM….???? Feedback will be appreciated.

 

If I get the board to boot, then I’m almost done with the proto-board and I can move to layout.

 

The only item left to test are the H89 OTP’s using the GAL’s as a replacement. Right now I’m using the H89 original OTP’s which are not available anymore, except for the 444-83 that I still support to enable the H89-Z67 controller.

 

Norberto

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Glenn Roberts
Sent: Saturday, July 13, 2013 4:38 AM
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

 

Congratulations Norberto, quite an accomplishment!

[Dan Emrick]

Hi, Norberto,

The symptoms you describe can happen if a floppy boot track or system files are corrupted.  In your case,  I'm assuming you're testing with a known good floppy disk, but I thought I'd mention it.

- Dan

[Kenneth L. Owen]

Hi Norberto,

 

To better understand your issue, I have a few questions:

 

1.                   What driver are you using?  (Basic HDOS 2.0 distribution or HUG H17.DVD from HS Support Package Disks, etc.)

2.                   Single or double-sided floppy?

3.                   Have you run the sets for the installed driver?

4.                   Boot clock rate?  (H17 controller only works at 2 MHz.)

 

-- ken

 

---

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Norberto Collado
Sent: Saturday, July 13, 2013 1:58 PM
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

 

Once you are in, it is hard to get out and times goes fast! J

 

I just enabled the H17 board to the H89 proto board and when I type Boot1 (in my case), it enables the floppy drive (light is on), does a  seek and then you can hear the drive doing retries and then the “H: “ prompt comes back (pictures attached). More troubleshooting to do. Not sure if it is related to the memory decoder for the H17 RAM….???? Feedback will be appreciated.

 

If I get the board to boot, then I’m almost done with the proto-board and I can move to layout.

 

The only item left to test are the H89 OTP’s using the GAL’s as a replacement. Right now I’m using the H89 original OTP’s which are not available anymore, except for the 444-83 that I still support to enable the H89-Z67 controller.

 

Norberto

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Glenn Roberts
Sent: Saturday, July 13, 2013 4:38 AM
To: se...@googlegroups.com
Subject: RE: [sebhc] H89 on a Veroboard!

 

Congratulations Norberto, quite an accomplishment!

 

Speaking of all night Heathkit projects I note the time stamp on your message is 3:33 AM !!!

 

-          Glenn

 

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[Norberto Collado]

I was using an H17 CPM disk to boot from. I think it might be single side, but not sure.

I need to enable my second H89 with the H17 to verify the disk driver set.

I change the clock from 5MHz to 2MHz to ensure that the H17 can boot. 

Let me do more homework, but I need to verify that the H17 memory is working fine.

Thanks,

Norberto

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