Terry: when you boot using “universal” sequence can you tell if the Z67-IDE+ consistently reads the software boot code record (LED shows brief disk activity)? If not then the problem might be with PAM 37?; if yes then we could look at the software boot code. I disassembled and commented this a while back. Norberto has the listing on his site
http://koyado.com/Heathkit/HDOS_H67_Boot_Code_files/bootcf0b%20Listing.pdf
this is the first code loaded off the Z67 and it is what presents the boot image selection menu.
Since you have gotten this to run at least occasionally we know that at least those times the Z67 read worked.
Don’t know if you can spot anything in this code that would be an issue. Or could compare to the boot code in BOOT and/or the H37 boot to see what those do that this doesn’t?
Do we know that the PAM-37 is fully compatible with the board? Trionyx apparently sold their own firmware (below).
I also saw that the Trionyx board implements “software control of all three Z80 interrupt modes” (which the Heath and DG boards do not do). Could it be that the interrupt processing is somehow not being initialized properly (since you’re observing inconsistent failures)?
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You could also try replacing the Heathkit boot process with the Quickstor one which uses a different boot code. Ken Owen can probably help with any questions. He has a lot of info on Norberto’s site though, including some images that you can burn directly to a CF card…
http://koyado.com/Heathkit/Z67-IDE-plus.html
there’s a lot of stuff there and not that well organized but Ken or Norberto can probably help you figure it out.
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Hi Terry,
I have teamed with Norberto to try to give implementation support to the group members who are trying to implement the Z67-IDE and Z67-IDE+ on their Heaths.
I have increasingly been less active on the group over the past 10 years as my wife was not well, declining in health and needed me more that the group! She passed away in August of this year and I am trying to get back into things that had to fall by the wayside over the past 10 years.
Feel free to contact me directly for your needs. It may take me a bit to get back up to speed on things, but I will give you my best. My email addy is: tx83...@bellsouth.net
Sent from Mail for Windows 10
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Please try the following image and use the Windows tool to deploy it on CF#0.
Image: http://koyado.com/Heathkit/Z67-IDE-plus_files/H37_H67_Heath_HDOS_CPM_Drive0.zip
Tool: http://koyado.com/Heathkit/Z67-IDE-plus_files/Z67-IDE%20Windows%20Imaging%20Utility.zip
If booting from this image fails, then you have a corrupted PAM-37 monitor or a marginal broken CPU.
Make sure all the switches on the H67 are set to the “ON” position (DS1), to the right of the arrow on the switch.
Thanks,
Norberto
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Also I developed the Z67-IDE+ on the Trionyx CPU using the PAM-37 monitor.
Norby
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It seems like Trionyx did this a lot. I had a few of their memory boards and there were multiple patches applied over time. The temptation is to remove them but they were all bug fixes or enhancements, if you can track down the documentation…
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If you leave the system hung for at least 5 minutes, do you get any other information? Just curious.
If not, send me the Z67-IDE+ to check it out.
Address: Norberto, Collado, P. O. Box 988 Hillsboro, OR 97123-0988
Thanks,
Norberto
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Yes, type the “esc” command to enter the menu.
Norberto
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Any updates???
Thanks for the update! Please check your serial board to be configured properly. Also check your RS-232 handshaking signals as well. It seems to be stuck polling the serial port based on your description, but not sure. Have you seen on the Z67-IDE+ any watchdog timeout messages?
When you use the PAM-37+ image I gave you, do you see on the screen “H8 Initialized…” on power-on?
I will review your data tomorrow again. I can send you a modify FW for the microcontroller that will display the command and data read/written.
Thanks,
Norberto
Any updates???
Error! Filename not specified.
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Hi Terry,
I have been out of the loop for quite a while due to caring for my wife. Since I don’t remember the image file below, I can’t give you very specific instruction, you might want to pull the Z67 card and set all switches on. This will give you the SASIX boot menu if that image is using it. Also, you can try the command line: “Boot SS-0 <cr> If the image is using the SASIX Boot system it should boot partition 0 of the system.
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If HDOS QuikStor works fine, then you were using the wrong port #. Great news.
Norberto
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Hi Terry,
The SASIX boot screen needs the H-19 Terminal using VT-52 mode and the Heath enhancements. If you don’t have an H-19 Terminal, several on the group have H-19 emulators that they have developed. I believe George Farris has one that will work with the SASIX boot system. Contact him here in the group.
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On Nov 24, 2020, at 4:06 AM, Norberto Collado <norberto...@koyado.com> wrote:
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<New_Z67_board.pdf><H8-Z67-SD CONTROLLER.JPG>
Had a thought, and keep in mind I know nothing about this
microcontroller and it's SDK. But, does the SDCard library support
a partition table (e.g. MS-DOS boot sector (MBR), or more modern
forms) on the SDCard? And if so, do we want to use it? This would,
in theory, allow one to partition the huge SDCard into
"reasonably" sized partitions for HDOS or CP/M on the host, and no
longer be constrained by the 128M fixed segment size. It makes it
easier to update and backup images on the card from the host PC,
and provides the potential for less wasted space. Still, it's a
trade-off and I'm not sure if it is worth it.
And, of course, Glenn's comment about making sure one can
insert/remove the cards without disassembling the unit would be
essential.
--
For accessing SD cards from the front, the only solution I know is to use an extension which sells at Amazon.
If someone knows a better solution, please let us know.
Thanks,
Norberto
From: "se...@googlegroups.com" <se...@googlegroups.com> on behalf of Glenn Roberts <glenn.f...@gmail.com>
Reply-To: "se...@googlegroups.com" <se...@googlegroups.com>
Date: Tuesday, November 24, 2020 at 2:46 AM
To: "se...@googlegroups.com" <se...@googlegroups.com>
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The 128MB limit is because of CP/M supporting 8MB * 15 partitions + spares MB. HDOS uses 15MB if using Glenn changes. This allows me to divide a 4GB CF card into 128MB chunk sizes. What is a reasonably sized partition?
I know that the SCSI2IDE controller was tested with a Z80 using the SDCard MSDOS library and performance was very poor. With CF cards was much better.
https://www.retrobrewcomputers.org/doku.php?id=boards:other:scsi2ide:start
Thanks,
Norberto
From: "se...@googlegroups.com" <se...@googlegroups.com> on behalf of Douglas Miller <durga...@gmail.com>
Reply-To: "se...@googlegroups.com" <se...@googlegroups.com>
Date: Tuesday, November 24, 2020 at 4:20 AM
To: "se...@googlegroups.com" <se...@googlegroups.com>
Subject: Re: [sebhc] New Z67-SD Controller
Had a thought, and keep in mind I know nothing about this microcontroller and it's SDK. But, does the SDCard library support a partition table (e.g. MS-DOS boot sector (MBR), or more modern forms) on the SDCard? And if so, do we want to use it? This would, in theory, allow one to partition the huge SDCard into "reasonably" sized partitions for HDOS or CP/M on the host, and no longer be constrained by the 128M fixed segment size. It makes it easier to update and backup images on the card from the host PC, and provides the potential for less wasted space. Still, it's a trade-off and I'm not sure if it is worth it.
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Glenn,
I saw this board which shows that I need to extend the SD adapter out of the board to be access from the front. I will incorporate such change as we can do a 3D print case for it. See attached picture.
Norberto
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It may be better to just access the SDCard "raw", but I thought I'd ask. FYI, CP/M 3 does not have the 8M partition limitation, it can support a 256M drive (partition). It just seemed that getting out of the fixed-size segment might be worth exploring.
I'm not sure why the performance would be worse, seems to me that
the partition table should be read only once at power-up of the
Z67-IDE (or Z67-SDC as the case may be) - or rather at insertion
of the SDCard if supporting hotplug, so I don't think the Z80
comes into it at all. Keep in mind, I'm suggesting that the
microcontroller in the Z67-SDC use the MBR partition table, not
the Z80 (CP/M). I was thinking that each MS-DOS partition on the
SDCard be "exported" by the Z67-SDC as a raw disk, and CP/M /
QuickStore / HDOS, whatever might sub-partition it as needed. So,
instead of the fixed-size 128M "segments", the Z67-SDC just reads
the MBR partition information and uses those partitions instead of
the fixed segments. But, if the SDK you are using does not have
library support for MBR, it wouldn't make sense. And if the
microcontroller is limited in speed and/or memory, it also may not
make sense.
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That’s exactly what I was thinking. Thanks!
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The current Z67-IDE+ supports only the 128MB when using the switches to divide the CF card. If you leave the switches at “00”, then all 1GB range is available to the system. Today 256MB partitions are supported, but the user must avoid selecting such partition with the switches. So for 256MB, the user will select “00” and the next available partition will be “002” as “00”-> “01” will be used by CP/M3 OS. For this controller, I will use the 256MB range to divide the SD card as it makes sense to redo some of the Heath CP/M-HDOS images.
Please send me a CP/M3 256MB image to test with the current Z67-IDE controller. I want to see it any issues.
I will review about the MBR to understand on how that works. Yes, we need to use raw as it is a 20MHz 8bit CPU with 1KB of RAM. It is faster than the original SASI 10MB hard drive.
Thanks for the feedback,
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I was not aware that the Z67-IDE+ did not enforce the end of the segment. So, it is possible to corrupt later segments on a CF card?
I mis-quoted earlier, CP/M 3 supports drives of up to 512M each.
The MMS "master boot record" supports 8 (or maybe 9) partitions, so for CP/M 3 one could use 4+G of space on the card. I'll need to make sure my Z67-IDE+ emulation supports the above behavior, and then I can create and test a CP/M 3 image that uses more space.
It is sounding like maybe this new controller is not going to work well with MBR, even *if* the SDK contains code for it. It would make handling the "segments" on the host PC easier/safer, but it may not be practical to implement on the microcontroller. It also would not have the behavior of the old Z67-IDE+ segments, as you cannot access beyond the end of an MBR partition like you can with the segments.
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The Z67 uses the interface protocol defined in the MRX101D controller which was originally designed for Memorex 101 disk drives. This is what Norberto has emulated in his implementation. The interface specification is here
http://koyado.com/Heathkit/Z67-IDE_files/MRX101D.controller.pdf
It uses sectors that are 256 bytes in size. the “Class 0” command (I/O) data structure (p. 14) allows 21 bits for sector addressing and three bits for logical unit number. Norberto’s controller maps the logical unit number to the CF (or soon to be SD) card, so LUN 0 is card 0, LUN 1 is card 1, etc. (though this could presumably be changed via software to refer to portions of the same SD/CF card). Each card can have 2**21 sectors which is 2,097,152 sectors or 538,870,912 bytes ( ½ Gig). So without software changes to the IDE+ software you’re constrained to ½ G per SD/CF card. the thumbwheel switches let you extend that space by remapping it within the card in 128 Mbyte chunks, but for any given thumbwheel setting your limited to the ½ Gig aligned to any given 128 Meg boundary specified by the switch settings.
If we were to partition the card into 8 logical units (rather than have the LUN refer to the physical card slot) you could support up to 4 G per card, however currently the LUN is used to select different cards. Not sure how hard it would be to redefine sector size (e.g. to 512, 1024, etc.) but that might be another option.
Frankly ½ Gig is so much space from an HDOS/CP/M concern I’m not sure it’s worth spending a lot of time on.
Now how much of the ½ Gig is usable at the OS level is a function of the drivers and BIOS definitions. The Heath/Zenith HDOS drivers used a 2-byte sector addressing scheme (presumably more efficient than juggling 3-byte entities). With 2 bytes you can address at most 65,536 sectors or 16 megabytes.. I believe the Quickstor and CP/M drivers are smarter and can access more.
Norberto implemented a special feature of his firmware that uses a control byte to access the full ½ Gig address space. I use this in my “jukebox” software to access a whole swath of space that’s “invisible” to HDOS otherwise.
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right, I had neglected to consider the SASI protocol in
computations of usable space. CP/M 3's 512M per drive capacity
matches the SASI protocol max capacity per LUN, but not when you
put a bunch of "pseudo SASI drives" onto a single storage card
accessed via SASI.
The GIDE, and possible (direct) SDCard, interfaces should not have any such limitation.
Although, a 512M CP/M drive still has it's issues. Not least of
which, it probably needs an 8000-entry directory which would take
a long time to read on first access, let alone that that requires
a huge amount of directory HASH space (32K). Also, addressing that
much storage requires the use of fairly large allocation blocks,
so there is more wasted space (esp. for small files).
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It may be better to just access the SDCard "raw", but I thought I'd ask. FYI, CP/M 3 does not have the 8M partition limitation, it can support a 256M drive (partition). It just seemed that getting out of the fixed-size segment might be worth exploring.
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Hi Norberto,
The Z67-IDE (and IDE+) use the switches for multisystem boots. Unless there is a problem with the root data, if a system fails to boot, you can select another one which will boot and now have a way to recover the one that quit working.
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I'm not proposing any major changes. I simply thought that using
MBR might make things easier. If not, then I think things should
stay the same.
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Attached is latest Z67-SD PCB board. I made several changes based on feedback received and it looks better than before.
Thanks,
Norberto
From: "se...@googlegroups.com" <se...@googlegroups.com> on behalf of Norberto Collado <norberto...@koyado.com>
Reply-To: "se...@googlegroups.com" <se...@googlegroups.com>
Date: Wednesday, November 25, 2020 at 3:13 PM
To: "se...@googlegroups.com" <se...@googlegroups.com>
Subject: RE: [sebhc] New Z67-SD Controller
Thanks for the feedback!
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Joe: bottom line: this is a peripheral that works with both the H8 and H89!
Longer story:
Norberto is updating the design for his “Z-67” emulator. The Z-67 was a large, heavy and expensive accessory for the H8/H89 that provided for an 8” floppy drive and an 11 meg hard (what they then called “Winchester”) drive. The Z-67 was actually shown in catalogs (see below, Spring/Summer 1982) primarily as an H89 accessory at the time, but it can be used with either the H8 or H89. Norberto reverse engineered the SASI protocols and implemented the same functionality on a single board. His first generation of the device was in fact built on a card that could fit in the H8 chassis, or could be mounted externally in a 5-1/4” drive bay. His second generation was smaller and mounts in a 3-1/2” bay. They connect to the controller card in the computer via a SASI ribbon cable. Both those versions rely on Compact Flash drives as the solid-state storage medium. CF devices are expensive and somewhat difficult to obtain so Norberto is moving to the more common Secure Digital (SD) card plus a simpler design with new display features as well.
To talk to the Z67-IDE device your computer needs a SASI controller card. Norberto designed a Z67 interface card for the ’89 in 2015 – looks like he may still have a few available…
http://koyado.com/Heathkit/H89-Z67.html
He has recently updated his design for the H8 interface board
http://koyado.com/Heathkit/H8-H17-H37-H67-USB.html
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The terminology used here can be confusing. "Z67" might refer to
the SASI interface board, plugged into an H8 or H89 (different
boards). Or it might refer to the external cabinetry, power
supply, SASI controller, and harddisk. Or some combination of
those. Norberto (at al.) built a modern functional replacement for
the (now rare and/or obsolete) external components. This was the
Z67-IDE, then Z67-IDE+, and now (what I presume will be called)
the Z67-SDC.
The SASI interface board is really just a parallel port
specialized according to the SASI standard. The "SASI drives" are
really the combination of a SASI controller board (lots of
"smarts" - a CPU, firmware, etc) and one (or occasionally more)
harddisk drives. SASI is the predecessor of SCSI, and has the same
basic topology - very simple interface to the bus on computers
(initiators), complex controllers on the peripherals (targets),
high-level command structure to abstract-away hardware
differences.
In theory, the Z67-IDE(+) would work on any computer (non-Heathkit) that has a SASI interface. It replaces the fragile and difficult to repair/replace controller+harddisk combination.
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WOW, $5999.00 back in the 80’s!!! Today’s price per CPI is $20,098.92. A lot of money.
Thanks Glenn on such great feedback.
Norberto
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SDC for “Secure Digital Card”? Yes, I can do that. Z-67 named was used to honor the Heath Z-67 external storage solution per add from Glenn’s previous email.
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On Nov 28, 2020, at 2:32 PM, Norberto Collado <norberto...@koyado.com> wrote:
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Hi Norberto,
That sounds reasonable. Are you going to emulate SASI with 256-byte sectors, or 512? With 256 the SASI protocol can only address 512M (with 512 can address 1G).
Either way, 1G segments seems fine, even if half of that is inaccessible. I don't don't how available 2G, 4G, 8G, or 16G cards are, but those might suffer a bit of a loss by the larger segmentation. I'm assuming you'll just provide fewer segments in those cases, same as the CF card? I suspect we don't need to squeeze every byte out of a card, and that no one will likely need 16 segments, let alone 100.
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Just had a "hair-brained" thought... might be good to set that 256/512 switch well-recessed, so it can't be accidentally flipped. Or maybe even do something to embed the 256/512 setting on the media itself. I can't imagine a case where you'd want to flip that switch once you've put OS images on the disk. The drivers will need to know the sector size, I think. I can't imagine being able to switch on-the-fly without reinitializing software.
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Great feedback! I added an I2C NVRAM chip, so I can have that feature there.
NVRAM:
0x0000 = VD Settings (0-99)
0x0001 = 256/512 switch selection (0x00 = default = 256, 0x01 = 512 byte per sector.
0x……. = tbd (future expansion)
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I presume there will be port I/O access to read/write the NVRAM? (e.g.to query the sector size and other parameters)…
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Actually, I was thinking that the 256/512 setting needed to be on
the (each) SDCard. For example one could make an image based on
512-byte sectoring and one for 256, whichever one is insert then
gets the right setting. Otherwise, one has to label the card and
remember to flip the switch.
But, that would require some hi-jinks to figure out where on the
card to put it. So, not sure if it is practical. But, if it's
worth pursuing perhaps the group can come up with a nice solution.
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-------- Original Message --------
Subject: RE: [sebhc] New Z67-SD Controller
From: "Glenn Roberts" <glenn.f...@gmail.com>
Date: Fri, December 04, 2020 6:27 pm
To: <se...@googlegroups.com>
I presume there will be port I/O access to read/write the NVRAM? (e.g.to query the sector size and other parameters)…
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NVRAM:0x0000 = VD Settings (0-99)
0x0001 = SD#0 - 256 or 512 selection (0x02 = default = 256, 0x05 = 512 byte per sector.0x0002 = SD#1 - 256 or 512 selection (0x02 = default = 256, 0x05 = 512 byte per sector.To do this automatically by reading the SD card, a one sector will need to be reserved with such setting on the card; perhaps the last sector on a 1GB range, reserved and protected with the "2" or "5" value preloaded. I think this is overkill.Using the NVRAM setup will be easier. Also I'm adding the LCD and I can display NVRAM settings such as; "SD0: 256, SD1: 512....", so the user knows which slot to use. Or we can use a HDOS/CPM SASI commands to display NVRAM settings, or use the serial port to query the configuration as well.
Thanks,Norberto
-------- Original Message --------
Subject: Re: [sebhc] New Z67-SD Controller
From: Douglas Miller <durga...@gmail.com>
Date: Fri, December 04, 2020 6:36 pm
To: se...@googlegroups.com
Actually, I was thinking that the 256/512 setting needed to be on the (each) SDCard. For example one could make an image based on 512-byte sectoring and one for 256, whichever one is insert then gets the right setting. Otherwise, one has to label the card and remember to flip the switch.
But, that would require some hi-jinks to figure out where on the card to put it. So, not sure if it is practical. But, if it's worth pursuing perhaps the group can come up with a nice solution.
On 12/4/20 7:27 PM, Norberto Collado wrote:
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Updates on the Z67-SDC controller development:
HDOS
CP/M-CP/M3:
Added features:
Thanks,
Norberto
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MMS CP/M 3 images are built for the full 64K space, I don't think Norberto has the experience to run GENCPM and change that.
I'm curious, what would leaving extra space at the top of memory
give us?
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The problem Norberto is chasing is some timing issue inside the Z67-SDC. There is no problem on the Z67-IDE or (presumably) a Z67 with standard SASI drive. The OS does not crash in any of these cases.
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I think is time to revive the Z67-SDC controller. I have been thinking for a while (since March 28, 2021) in trying to understand the timing issue on the Z67-SDC board. I decided to add an 74AHCT123 to one of clocks as the HW is pulsing one of the clocks too fast and the H8 somehow misses it as it never replies that it was received. The main benefit of this board is that it uses SD media and parts are very inexpensive.
Hopefully we will have this board working properly soon.
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I still have my 1.1 version of the original IDE board – 12 years old now! A classic! A redesign/update would be good and will keep things going for another 10 or more years!
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After a year, finally I was able to run the Z67-SDc at 2/4/8/10 MHz at the HDOS OS level. The timing issue was related to the signal /ACK. I was pulsing such signal at 1us. With Terry S. help, he created a small board to adjust such signal timing. Today I did made additional HW changes to the board created by Terry and adjusted the /ACK clock to 35ns. Finally this fix allowed me to boot HDOS without any issues and run at 10MHz.
I have been stressing the SD card all day and so far no issues reading or writing to it. Very stable.
Here is a picture of the working board. As I’m scrapping such design for a better one, at least I got it to work, and a lot learned when trying to emulate an SCSI IC in software.
Thanks
Norberto
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On Jul 25, 2022, at 12:14 AM, norberto.collado koyado.com <norberto...@koyado.com> wrote:
After a year, finally I was able to run the Z67-SDc at 2/4/8/10 MHz at the HDOS OS level. The timing issue was related to the signal /ACK. I was pulsing such signal at 1us. With Terry S. help, he created a small board to adjust such signal timing. Today I did made additional HW changes to the board created by Terry and adjusted the /ACK clock to 35ns. Finally this fix allowed me to boot HDOS without any issues and run at 10MHz.
I have been stressing the SD card all day and so far no issues reading or writing to it. Very stable.
Here is a picture of the working board. As I’m scrapping such design for a better one, at least I got it to work, and a lot learned when trying to emulate an SCSI IC in software.
To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/SN6PR01MB3855654C1C6F79877FBA719BF7959%40SN6PR01MB3855.prod.exchangelabs.com.