CP/M3 CP/NET FT245 H8 Setup

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Norberto Collado

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Oct 27, 2018, 1:43:22 PM10/27/18
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Douglas,

I ran the Java from my Windows 10 laptop and it failed with errors. See attached file.

D:\FT245 CPNET>java -version
java version "1.8.0_191"
Java(TM) SE Runtime Environment (build 1.8.0_191-b12)
Java HotSpot(TM) Client VM (build 25.191-b12, mixed mode, sharing)

Thanks,
Norberto
CPNET_Java_errros.txt

Douglas Miller

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Oct 27, 2018, 2:44:59 PM10/27/18
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Ah, that's the RXTX package which is required to handle serial ports. Subtle documentation. You need to install from http://rxtx.qbang.org/wiki/index.php/Download. I'm not sure what it takes to install that on Windows. I hated using some third-party add-on like this, but JAVA refuses to define an interface and implementation for accessing serial ports.

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Dave McGuire

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Oct 27, 2018, 3:21:18 PM10/27/18
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On 10/27/2018 02:44 PM, Douglas Miller wrote:
> Ah, that's the RXTX package which is required to handle serial ports.
> Subtle documentation. You need to install from
> http://rxtx.qbang.org/wiki/index.php/Download. I'm not sure what it
> takes to install that on Windows. I hated using some third-party add-on
> like this, but JAVA refuses to define an interface and implementation
> for accessing serial ports.

It can't, as it would be very different between platforms. Don't
forget that Java runs on everything from Windows to IBM mainframes.
Device access varies greatly between platforms.

-Dave

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Douglas Miller

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Oct 27, 2018, 3:32:05 PM10/27/18
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So, the documentation for this really blows, but I've not found a better solution. I think what you need is the rxtx-2.2pre2-bins.zip package, which contains files for Windows, Linux, MAC-OSX. For my x86_64 linux system, I installed these files into these locations:

/usr/lib/jvm/java-8-openjdk-amd64/jre/lib/ext/RXTXcomm.jar
/usr/lib/jvm/java-8-openjdk-amd64/jre/lib/amd64/librxtxSerial.so

Where "java-8-openjdk-amd64" is the JAVA JDK/JRE I am using. For windows, you'd substitute a DLL for the ".so". I'm guessing you have win64? I believe Windows and Linux JAVA have similar directory structures *below* the JRE path. Basically, look for a place where other JAVA DLLs reside, and that's a good bet. There should be some "ext" (extensions) directory for the JAR.

It would be nice if multi-platform installation was not such a PITA.

Douglas Miller

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Oct 27, 2018, 3:38:08 PM10/27/18
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I didn't intend to start a discussion, but you and I have different
views of what can and can't be done. Serial implementations are
different, but the basics (the interface) of serial ports are the same.
Baud, async, stop bits, parity, etc. Might not cover every single piece
of hardware out there, but it would cover most. Would not have to be
anywhere near as complex/robust as the Unix/Linux abstraction.

Dave McGuire

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Oct 27, 2018, 4:09:13 PM10/27/18
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Sure, but the OS interfaces to those devices are very different. That
was really all I was trying to say. No user-level program will ever be
allowed direct access to the hardware, and even if it were, even that is
very different. On a PC or a Sun workstation, there are UARTs in the
I/O or memory address space, but on a mainframe these are accessed
through channel programs and CCWs...programs don't write to registers.

Just pointing out the difficulty here, nothing more. If it could have
been done better, it would have been.

-Dave

Douglas Miller

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Oct 28, 2018, 11:54:02 AM10/28/18
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I've updated your image, http://sebhc.durgadas.com/mms89/images/cpm3-x2h8-ft245r-rtc.z67ide.xz. I made some long-intended changes so that the MODULES.COM command will show RTC and RAM drivers as well. I also added SPDSBC.COM to your image, and made some more reasonable default modes (I hope) for the Z37 drives. I forgot to change step rate, but am not sure what your drives support anyway.

H8 Console initialized!

Z89/Z90 Loader v2.241  (c) 1982,1983 Magnolia Microsystems

 BNKBIOS3 SPR  EB00  1500
 BNKBIOS3 SPR  9100  2F00
 RESBDOS3 SPR  E500  0600
 BNKBDOS3 SPR  6300  2E00
 
 57K TPA

CP/M 3.104  (c) 1982,1983 DRI and MMS
A>spdsbc
You are running at  2 MHz.

A>modules

MODULES v3.101   (c) Magnolia Microsystems

Z89 Standard and interupt I/O v3.101
77320 SASI Interface (8 partitions) v3.104
Z89-37 Double Density Controller v3.102
X/2-H8 Tryonix 256K RAM and MMU v3.101
72421 RTC Driver v3.101

A>tpa
57.25K TPA

A>date
Sun 10/28/2018 10:35:57
A>

Hope it helps. Let me know if/when there's too much churn, and I can slow down updates to your image.

At some point, I am going to recreate this image from scratch, and I'll partition it into 8x 8M partitions so there is less wasted space. You can still choose how many of those partitions are available in CP/M, and what drive letters they have. I'll also setup CP/M 3 timestamps for the directories, unless you don't want that. I need to re-test my scripts for creating an image from scratch, and have now added the option to enable timestamps, so it will be a good exercise either way - just whether or not you want the image.

Douglas Miller

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Oct 28, 2018, 12:05:24 PM10/28/18
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I've been wondering about the FT245R and the need for CRC and other
protections one would ordinarily use for communications over RS-232. I
think the current CP/NET for FT245R is slower than it needs to be,
although we don't have any benchmarks on real hardware yet.

So, the FT245R has no UART (aside from the USB Serial I/O Engine, which
is not what I'm talking about) and so I suspect  there is no baud
setting that makes sense - it always runs as fast as the FIFOs and USB.
It also seems that USB protocol has it's own CRC mechanism and so the
transmission between the FT245R and the host PC is reliable (unless the
FT245R uses an un-protected protocol option).

My current CP/NET USB protocol is modeled after the "DRI recommended"
protocol for RS-232 async serial ports, i.e. all data is shipped in
ASCII and packets are CRC protected. This means that twice as many bytes
are transmitted, in addition to the overhead for CRC. If the FT245R (and
USB) support binary data transfers (I'm pretty sure they do), then I
should be able to cut the packet-on-wire size in half. And if the USB
handles integrity, is there a need to still manage CRC at the Z80 (and
host PC)? I guess it depends on whether we expect the Z80 or FT245R
FIFOs to introduce errors.

Opinions would be appreciated.

Thanks,

Doug

Norberto Collado

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Oct 28, 2018, 7:31:19 PM10/28/18
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This is great! Let me test this image and let’s make eventually such image the best it can be. The 8x 8M partitions along with three floppies + timestamp as the interrupt is available. I’m open to test any images you can make available to ensure proper operation with the H8.

 

Now that we have a working solution, I can start planning the new layout of the X2 controller along with the 256KB memory to support the H8.

 

Thanks for all your support!

 

Norberto

Norberto Collado

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Oct 28, 2018, 7:38:19 PM10/28/18
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I think we should add interrupt capability to the FT245, to avoid polling the port and that should improve your transfer rate. Or we could use the third PC16C550 modified to run at higher clock rates attached to the USB serial cable to the pc, and no need to use the FT245.
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Norberto Collado

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Oct 28, 2018, 7:47:15 PM10/28/18
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This image is working great. I can read my floppy drives without any issue. Also modules is working fine. Thanks for adding the SPDSBC.COM file.

 

Great job Douglas.

 

For the new X/2 layout, any recommendation for improvements on such design? For sure, I will be using the 74HCT series if available.

 

Thanks,

Norberto

Douglas Miller

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Oct 28, 2018, 7:51:30 PM10/28/18
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I don't think the FT245R is the bottle-neck - it's got to be faster than
any UART/RS-232 connection (running at some finite baud), I think. The
FT245R should be able to run as fast as the Z80 can stuff data into it -
I don't think the Z80 could ever keep up with the USB data rate. For
CP/NET, interrupts aren't much of a benefit. For the clients, there
isn't anything else to do when waiting for a response. Polling is
actually faster than interrupts, as the interrupt overhead just slows it
down. If we were running an MP/M server, we'd definitely need
interrupts, but with CP/NET on CP/M I'm not sure it will help. If we
decide to support asynchronous messages being sent to clients, then
interrupts might help. Although, probably in both cases we'd want a
"start of packet" interrupt and not a char-by-char (although a
char-by-char interrupt can usually be implemented as a start of packet).

I was looking to eliminate the overhead of converting data to hex-ascii,
and computing crc. But that creates a problem for maintaining
synchronization, as any sync-pattern could also exist in the data. I've
setup my simulator to (at least try and) run at 10MHz, and will see if I
get any improvement with the current protocol.

Douglas Miller

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Oct 28, 2018, 7:56:12 PM10/28/18
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You and I designed that 512K MMU last year, which I like. But if you're making an X/2-H8 I'm guessing you'll be maintaining software compatibility with that. I'll give it a little thought to see if there's a way to extend the X/2-H8 MMU without breaking compatibility. Being able to read and write different banks at the same time can be a big benefit to CP/M 3 (and even RAM-disk implementations). The ram-disk driver I did for the 512K MMU works quite nicely.

Norberto Collado

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Oct 29, 2018, 12:06:11 AM10/29/18
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I know we did work on the schematics for othe 512K MMU. Do you still have them? If not I know there are in the SEBHC website.

If the 512KB MMU is better, I can go that way and retire the X/2 design. 

Norberto

Norberto Collado

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Oct 29, 2018, 12:11:00 AM10/29/18
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The new Z80 supports up to 16MHZ. I got the Z80 system to work reliable up to 8 MHz. As I do not space on the board for a 10MHz oscillator, then I have to use 16MHz as the max speed. The issue is with the Z67-IDE and I need to debug further when running at 16MHz.

Norberto  

-------- Original Message --------
Subject: Re: [sebhc] CP/M3 CP/NET FT245 over USB performance
From: Douglas Miller <durga...@gmail.com>
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Norberto Collado

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Oct 29, 2018, 11:54:23 AM10/29/18
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I downloaded the 512Kb RAM PDF diagram that you provided to refresh my mind. So we can have a single IC for all of this; correct?

512Kx8 55 Nanoseconds DIP-32 Static RAM

Can you add the circuit for the following control lines; /Bank and Map as they come from the CPU based on your diagram. I need to know this as I'm ready for the Z80 final production board in case I need to add something unique.

Thanks,
Norberto
-------- Original Message --------
Subject: Re: [sebhc] CP/M3 CP/NET FT245 H8 Setup
From: Douglas Miller <durga...@gmail.com>
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Douglas Miller

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Oct 29, 2018, 6:13:06 PM10/29/18
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Yes, I was thinking there must 512Kx8 RAM chips these days.

The /BANK line is the I/O port select, so I guess that's be your "normal" I/O port decode circuit. This one uses 8 ports. So, Address lines A3-A7, /IORQ, /WR combine to make /BANK. The MAP signal originates at the FlipFlop, being a latched version of D7 during output operations. Maybe you've got an earlier schematic? Attached is the one I have...

I think you were planning to make ROM-disable be orthogonal to bank select, but I'm not sure. I assumed that bit 5 of port 362Q selected/disabled ROM regardless of what RAM was selected. Otherwise, you'll have to route that between CPU and RAM boards.

The MAP signal is used to ensure that the board RESETs to the "non banked" state, bypassing the MMU entirely. Only by writing "1" to bit 7 (on every output) will the MMU stay enabled.

ram512k.pdf
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