FPGA (again) and interfacing advice

[Les Bird]

Hi all,

A while back I brought up the topic of building a H8 CPU on a FPGA. Well, I'm back at it again. I discovered recently (actually Rob Doyle mentioned this in our last conversation) that I can actually "program" the FPGA using BDF files (like schematics) which I understand a lot better than the verilog language. For those who are curious you can layout a schematic and it will be converted to verilog and then the resulting compiled code uploaded to the FPGA. (see photo).

I have a question for the experts regarding interfacing to the H8 buss.

The H8 buss is +5V TTL. I have a DE0-NANO FPGA board with GPIO pins. My plan is to "plug" the FPGA into the buss by wiring up a harness from the GPIO bins to two 25-pin connectors that plug into the H8 buss. The FPGA board has 3.3V on the pins. Do I need to do anything special in between the GPIO pins and the H8 buss? I looked online but can't find a solid answer - some say it'll work fine, some say there potentially needs to be some conversion circuitry. Not sure which way to go.

Also, do we have a good schematic for the HA-8-6 Z80 board? The one I have on SEBHC is broken up into several PDFs. Wondering if we have one that is one piece so it's easier to read or maybe if someone can stitch the schematic together from SEBHC.

There are some real benefits to putting the Z80 CPU on a FPGA. First, we'll never have to worry about parts that are going obsolete and no longer available. Second, we can make tweaks to the board and simply upload the new design to the FPGA without having to get prototype boards made, debug, and then get final boards from the PCB house. Third, a LOT fewer parts that can go bad. Fourth, substantial cost savings - aside from what I mentioned earlier about no PCBs needed a DE0-NANO cost $120 from MOUSER - no parts to source - and it can be reprogrammed with new functionality/features at anytime.

Now that I learned about laying out schematics on the FPGA this has been a very enjoyable experience for me so far.

Les

[Dan Emrick]

Les,

I'm far from expert, but I face a similar issue trying to directly interface an Raspberry Pi (3.3V GPIO) to an H89, well actually an H89-SBC. 

From what I've discovered, the reason you see mixed answers is that "it depends."  That is, while most 5V inputs will go from zero to one at around 2 volts, the amount of load presented to the 3.3V drive and the current capability of that drive could make it unreliable.  This isn't as big a problem for strobes and status lines as it is for bi-directional data lines.  So far I have not found a reliable solution.  The direction sensing, bi-directional level converters I've tried have not performed to my satisfaction. 

In any case, I'd be careful applying 5V to a 3.3V input.  The device might tolerate it, but then again . . .

You might go back through the post about the FUJI board and the ESP-32 interfacing.

Here's hoping someone else has better guidance.

Dan 

[Les Bird]

Thanks Dan, I see in the other thread that Darrell used 2 diodes to drop the voltage from 5V down to 3.6V to interface to a ESP-32.

Wondering if that means I'd need 2 diodes per H8 buss pin...? That's a lot of diodes.

Les

[Les Bird]

Found this interesting article on DigiKey:

https://www.digikey.com/en/blog/logic-level-shifting-basics

[Les Bird]

And it looks like this little guy will do the trick. Will step up to 5V and step down to 3.3V and is bidirectional.

https://www.mouser.com/ProductDetail/SparkFun/BOB-12009?qs=WyAARYrbSnb%252BGYLWggQnjQ%3D%3D

Might do the trick for your Raspberry Pi Dan.

Les

[Douglas Miller]

My gut-reaction would be that the FPGA can't drive the H8 adequately anyway, the same way the 8080 chipset couldn't. Seems to me you need buffers of some sort (inverting at that, unless the FPGA is programmed for it), and so level-shifters are the right choice it would seem. The data bus will require bi-directional. There seems to be lots of them out there, although bidirectional are probably harder to find. But, I think you should be able to find actual ICs to that, rather than BOBs with discrete parts.

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[norberto.collado koyado.com]

Just use a 74LVC540 between the FPGA and the H8 interface. Apply 3v to this IC and it will translate between the H8 5v and 3v for the FPGA. It supports mixed-mode signal operations on all ports. This means 5v input and output with a 3.3 VCC.

Norberto 

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From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Les Bird <lesb...@gmail.com>
Sent: Wednesday, December 14, 2022 3:19:52 PM
To: SEBHC <se...@googlegroups.com>
Subject: [sebhc] Re: FPGA (again) and interfacing advice

 

[Dave McGuire]

On 12/14/22 18:42, Douglas Miller wrote:
> My gut-reaction would be that the FPGA can't drive the H8 adequately
> anyway, the same way the 8080 chipset couldn't. Seems to me you need
> buffers of some sort (inverting at that, unless the FPGA is programmed
> for it), and so level-shifters are the right choice it would seem. The
> data bus will require bi-directional. There seems to be lots of them out
> there, although bidirectional are probably harder to find. But, I think
> you should be able to find actual ICs to that, rather than BOBs with
> discrete parts.

I've used the TI TXB0104 and TXB0108 for 3.3V/5V level shifting in
many designs; they've performed very well for me.

-Dave

--
Dave McGuire, AK4HZ
New Kensington, PA

[Douglas Miller]

My other question, if I were doing this, would be whether these
level-translators suffice for bus drivers, too... or does one still need
something to drive the H8 bus? The data sheet is making my eyes glaze
over, but I don't see anything indicating a significant current capability.

[Dave McGuire]

Oooh. Yes, that's a good point. I've never used them as bus
drivers, only as interfaces between different logic families.

-Dave

[Les Bird]

Norby, Dave, Douglas, thanks for the replies.

Douglas, just taking a guess here but since the 5V voltage source is supplied from the buss I think it'll just use the current/voltage from the source so I would think it would be enough? In other words I think what it's doing is if the 3.3V side is above a certain threshold it just steps it up to the supplied 5V source/current and vis-a-versa stepping it down to the supplied 3.3V source/current.

Is that not how it works?

Les

[Les Bird]

Dave,

Looks like Adafruit has the TXB0108 on a breakout board so no need to do that SMD soldering ;)

https://www.mouser.com/ProductDetail/Adafruit/395?qs=GURawfaeGuC1aDMKJdj9pQ%3D%3D

Les

[Douglas Miller]

I believe that each "translator" has a current limit, and if I'm reading the datasheet correctly it is pretty small. There is a fair amount of current needed (by comparison) to drive multiple TTL inputs in the various H8 boards. Also, just the length of the traces requires some current to drive the signals quickly to "1" or "0". I believe these translators are meant for direct, proximal, connection of two low-power devices.

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[Les Bird]

Ah, got it.

So it sounds like what we need then is a PCB that the FPGA plugs into via the GPIO pins and this PCB will have additional circuitry on it to (1) translate the voltage and (2) drive the buss. I think I need to find my H8-7 breadboard now, where did I pack that thing? I found every H8 card I had in my boxes that I packed except for that one card.

Les

[Dan Emrick]

To the question from Douglas, I've not been successful trying to use the TXB0108 as a bus driver.  That's one of my big issues.

Dan

[Dave McGuire]

Yes, it's only a logic level translator. No substantial drive
capability.

-Dave

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[Peter Higgins]

Altera Cyclone-based FPGAs have been the basis of several projects for the S100 bus:

http://www.s100computers.com/My%20System%20Index%20Page.htm

Level translation (5V to 3.3V) is typically performed using the 74LVC245, which is powered by 3.3V, has a 3.3V drive output, but is designed to accept input from 5V logic.

You will see the S100 bus designs I linked to above also use the 74LVC245 for 3.3V to 5V logic translation and driving the bus. These designs power the 74LVC245 with 5V instead of 3V (which is above typical but within max specifications) however a standard 74LS245 works just as well since the logic "high" level produced by the 3.3V FPGA adequately meets the minimum logic high level for an LSTTL device.

[Peter Higgins]

Altera Cyclone-based FPGAs have been the basis of several projects for the S100 bus:

http://www.s100computers.com/My%20System%20Index%20Page.htm

Level translation (5V to 3.3V) is typically performed using the 74LVC245, which is powered by 3.3V, has a 3.3V drive output, but is designed to accept input from 5V logic.

You will see the S100 bus designs I linked to above also use the 74LVC245 for 3.3V to 5V logic translation and driving the bus. These designs power the 74LVC245 with 5V instead of 3V (which is above typical but within max specifications) however a standard 74LS245 works just as well since the logic "high" level produced by the 3.3V FPGA adequately meets the minimum logic high level for an LSTTL device.

On Wednesday, December 14, 2022 at 12:30:48 PM UTC-8 Les Bird wrote:

[Les Bird]

Good information Peter, thank you.

Les

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[Les Bird]

Well I sent my first PCB to JLCPCB (thanks Scott!). It's been a while since I made a PCB. Basically a DE0-NANO FPGA breakout board for the H8. $40 including shipping (with $10 new customer discount) for 5 boards. Pretty good prices. I'm using 74LVC245's to interface to the H8 BUSS and for each chip you can set a jumper for it to be incoming or outgoing (the LVC245s are bidirectional). Once you decide which pins on the FPGA are incoming you can then set the jumper on the 245 to match, same for outgoing. The default configuration for the board is for all GPIO-0 pins to be outgoing and all GPIO-1 pins to be incoming. I've wired up an optional configuration for the board to act as a CPU board replacement - the jumpers on the right side of the board by the edge connectors, if they are all jumpered then this configuration (CPU board) will be active. If not jumpered then you can wirewrap you're own setup from the outputs of the LVC245s to the pin headers at the edge connectors so this board can be configured to do just about anything. You can also decide to not use any of the LVC245s and work directly from the GPIO breakout pins.

And when I say it's configured as a CPU board if you jumper the right side I mean I have a default set of GPIO pins wired to all the appropriate pins on the H8 buss to look like a CPU board. The Google Sheet linked below has the current FPGA to H8 BUSS mapping:

https://docs.google.com/spreadsheets/d/1-CI0nU_hhu6U5jDEmocSR6qhjhgz6WzZZCHjXEHm33Y/edit?usp=sharing

This is V1.0 of the FPGA breakout board so we'll see if it works. It's all just a prototype right now.

Les

[norberto.collado koyado.com]

Congratulations Les on your first H8 FPGA board.  Nicely done!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird
Sent: Thursday, December 29, 2022 6:38 AM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Well I sent my first PCB to JLCPCB (thanks Scott!). It's been a while since I made a PCB. Basically a DE0-NANO FPGA breakout board for the H8. $40 including shipping (with $10 new customer discount) for 5 boards. Pretty good prices. I'm using 74LVC245's to interface to the H8 BUSS and for each chip you can set a jumper for it to be incoming or outgoing (the LVC245s are bidirectional). Once you decide which pins on the FPGA are incoming you can then set the jumper on the 245 to match, same for outgoing. The default configuration for the board is for all GPIO-0 pins to be outgoing and all GPIO-1 pins to be incoming. I've wired up an optional configuration for the board to act as a CPU board replacement - the jumpers on the right side of the board by the edge connectors, if they are all jumpered then this configuration (CPU board) will be active. If not jumpered then you can wirewrap you're own setup from the outputs of the LVC245s to the pin headers at the edge connectors so this board can be configured to do just about anything. You can also decide to not use any of the LVC245s and work directly from the GPIO breakout pins.

 

And when I say it's configured as a CPU board if you jumper the right side I mean I have a default set of GPIO pins wired to all the appropriate pins on the H8 buss to look like a CPU board. The Google Sheet linked below has the current FPGA to H8 BUSS mapping:

 

https://docs.google.com/spreadsheets/d/1-CI0nU_hhu6U5jDEmocSR6qhjhgz6WzZZCHjXEHm33Y/edit?usp=sharing

 

This is V1.0 of the FPGA breakout board so we'll see if it works. It's all just a prototype right now.

 

Les

 

 

On Friday, December 16, 2022 at 9:26:17 AM UTC-7 Les Bird wrote:

Good information Peter, thank you.

 

Les

 

 

On Thu, Dec 15, 2022 at 10:07 AM Peter Higgins <higgin...@gmail.com> wrote:

Altera Cyclone-based FPGAs have been the basis of several projects for the S100 bus:

http://www.s100computers.com/My%20System%20Index%20Page.htm

 

Level translation (5V to 3.3V) is typically performed using the 74LVC245, which is powered by 3.3V, has a 3.3V drive output, but is designed to accept input from 5V logic.

You will see the S100 bus designs I linked to above also use the 74LVC245 for 3.3V to 5V logic translation and driving the bus. These designs power the 74LVC245 with 5V instead of 3V (which is above typical but within max specifications) however a standard 74LS245 works just as well since the logic "high" level produced by the 3.3V FPGA adequately meets the minimum logic high level for an LSTTL device.

On Wednesday, December 14, 2022 at 12:30:48 PM UTC-8 Les Bird wrote:

Hi all,

 

A while back I brought up the topic of building a H8 CPU on a FPGA. Well, I'm back at it again. I discovered recently (actually Rob Doyle mentioned this in our last conversation) that I can actually "program" the FPGA using BDF files (like schematics) which I understand a lot better than the verilog language. For those who are curious you can layout a schematic and it will be converted to verilog and then the resulting compiled code uploaded to the FPGA. (see photo).

 

I have a question for the experts regarding interfacing to the H8 buss.

 

The H8 buss is +5V TTL. I have a DE0-NANO FPGA board with GPIO pins. My plan is to "plug" the FPGA into the buss by wiring up a harness from the GPIO bins to two 25-pin connectors that plug into the H8 buss. The FPGA board has 3.3V on the pins. Do I need to do anything special in between the GPIO pins and the H8 buss? I looked online but can't find a solid answer - some say it'll work fine, some say there potentially needs to be some conversion circuitry. Not sure which way to go.

 

Also, do we have a good schematic for the HA-8-6 Z80 board? The one I have on SEBHC is broken up into several PDFs. Wondering if we have one that is one piece so it's easier to read or maybe if someone can stitch the schematic together from SEBHC.

 

There are some real benefits to putting the Z80 CPU on a FPGA. First, we'll never have to worry about parts that are going obsolete and no longer available. Second, we can make tweaks to the board and simply upload the new design to the FPGA without having to get prototype boards made, debug, and then get final boards from the PCB house. Third, a LOT fewer parts that can go bad. Fourth, substantial cost savings - aside from what I mentioned earlier about no PCBs needed a DE0-NANO cost $120 from MOUSER - no parts to source - and it can be reprogrammed with new functionality/features at anytime.

 

Now that I learned about laying out schematics on the FPGA this has been a very enjoyable experience for me so far.

 

Les

 

 

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[norberto.collado koyado.com]

Also your layouts are so beautiful when compare to the ones I do. 😊

 

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[Les Bird]

Haha Norby, your board is orders of magnitude more complicated. So not a fair comparison. I do have a dilemma though, I forgot to add filter caps for the chips and I'll have to do some re-routing of the traces to fit them in. :(

Les

[Joseph Travis]

  Sweet and simple.  Clearly a practitioner of the KISS philosophy.  Nice work Les!  

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[norberto.collado koyado.com]

I noticed that, but for this first board pass should be fine. You can do 1-per IC or 1-per three IC’s. Please use 0.1uf as all my new boards uses this cap and we have a lot in stock to build out new boards.

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[Les Bird]

Hi all,

Just a quick update. My FPGA breakout board is at V1.4 now currently in production at JLCPCB. It's come a long way. I added the filter caps and some prototype areas along with pull up resistors and an optional spot for a 74LS148 interrupt decoder. If I ever get the FPGA Z80 CPU board working then that should open up support for the H37 controller. I've also added 2 sets of dip switches (4 and 8 switch) and an optional spot for a LED bar graph at the top for debugging or whatever.

Currently I'm just trying to get the FPGA Z80 CPU to work with the front panel. I think it's close but it's not there yet. The ROM and RAM are integrated into the FPGA design and with the DE0-NANO there's even 32mb of SDRAM that I hope to tap into in the future. Will keep you all posted as I make more progress with it.

The 74LVC245s work well as an interface to the H8 buss. I'm getting good signals to the buss (3.3v to 5.0v) measured on the front panel and from the buss (5.0v to 3.3v).

V1.4 layout:

[norberto.collado koyado.com]

Very nice Les!  Thank you!

 

😊

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird
Sent: Friday, January 27, 2023 7:29 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Hi all,

 

Just a quick update. My FPGA breakout board is at V1.4 now currently in production at JLCPCB. It's come a long way. I added the filter caps and some prototype areas along with pull up resistors and an optional spot for a 74LS148 interrupt decoder. If I ever get the FPGA Z80 CPU board working then that should open up support for the H37 controller. I've also added 2 sets of dip switches (4 and 8 switch) and an optional spot for a LED bar graph at the top for debugging or whatever.

 

Currently I'm just trying to get the FPGA Z80 CPU to work with the front panel. I think it's close but it's not there yet. The ROM and RAM are integrated into the FPGA design and with the DE0-NANO there's even 32mb of SDRAM that I hope to tap into in the future. Will keep you all posted as I make more progress with it.

 

The 74LVC245s work well as an interface to the H8 buss. I'm getting good signals to the buss (3.3v to 5.0v) measured on the front panel and from the buss (5.0v to 3.3v).

 

V1.4 layout:

 

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[Mark Garlanger]

Les,

    Are you using an existing z80 fpga implementation? If so, would it happen to be this one - https://opencores.org/projects/a-z80 ?

Mark

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[Les Bird]

Mark, I looked at that one but no I'm not using that one, I'm using the one from the S100 FPGA Z80 project here:

http://s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm

Which is based on Grant Searle's FPGA Z80 core which is based on the T80s FPGA Z80 core from here:

https://opencores.org/projects/t80

The project you linked to is set up to turn a FPGA into a Z80 CPU so that you can plug it into a Z80 socket but what I'm doing is turning a FPGA into a Z80 CPU "board" with RAM and ROM and an interface to the H8 buss via FPGA simulated 74LS540s. The T80s core that is used on the S100 Z80 FPGA card and that Grant Searle modified is set up to do just what I'm looking for.

Les

[Les Bird]

I should probably rephrase that. The A-Z80 can be used as a core for a complete project. The default set up for the A-Z80 is to send all the Z80 signals straight to GPIO pins so that it can simulate a real Z80 CPU. It can, however, be modified to be the core of a complete FPGA system like what they did with the ZX Spectrum project, however, the S100 Z80 FPGA project was much easier to get started with since it was already set up to interface to a S100 buss so I went with that one instead.

Les

[norberto.collado koyado.com]

On this Z80 FPGA version, can we get at least 1MB of RAM?? Minimum 512KB.

Get Outlook for iOS

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From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Les Bird <lesb...@gmail.com>

Sent: Monday, January 30, 2023 10:40:07 AM

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[Les Bird]

The DE0-NANO FPGA board has 32mb available. So 1mb is a drop in the bucket. haha.

For starters I'm just trying to get built-in 32 or 64k (on the FPGA) to work then I'll tap into the 32mb SDRAM and get that working later.

Les

[norberto.collado koyado.com]

Cool! 

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From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Les Bird <lesb...@gmail.com>

Sent: Monday, January 30, 2023 12:47:40 PM

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[norberto.collado koyado.com]

Just curious how much the FPGA board costs with such RAM capacity?

Get Outlook for iOS

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From: norberto.collado koyado.com <norberto...@koyado.com>
Sent: Monday, January 30, 2023 1:09:51 PM
To: se...@googlegroups.com <se...@googlegroups.com>

[Peter Higgins]

This is the DE0-Nano board:

https://www.adafruit.com/product/451

Available from multiple vendors including Digi-Key and  Mouser for $115.

One of the contributors to the S100Computers Google Group has recently developed an FPGA development module for use with future S100 board designs. It uses the Efinix T35 FPGA core (with 180K of its own embedded RAM) and 64Mx16 of DDR3 RAM onboard. It costs under $100.

[norberto.collado koyado.com]

Very nice and thank you!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Peter Higgins <higgin...@gmail.com>
Date: Monday, January 30, 2023 at 2:39 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

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[Les Bird]

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

[norberto.collado koyado.com]

WOW, Les! I’m impressed.

 

Great job in getting this new design working. Congratulations.

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird

Sent: Friday, February 3, 2023 6:46 AM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

 

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

 

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

 

 

 

On Monday, January 30, 2023 at 10:13:34 PM UTC-7 Norby wrote:

Very nice and thank you!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Peter Higgins <higgin...@gmail.com>
Date: Monday, January 30, 2023 at 2:39 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

This is the DE0-Nano board:

https://www.adafruit.com/product/451

Available from multiple vendors including Digi-Key and  Mouser for $115.

 

One of the contributors to the S100Computers Google Group has recently developed an FPGA development module for use with future S100 board designs. It uses the Efinix T35 FPGA core (with 180K of its own embedded RAM) and 64Mx16 of DDR3 RAM onboard. It costs under $100.

 

On Monday, January 30, 2023 at 1:11:16 PM UTC-8 Norby wrote:

Just curious how much the FPGA board costs with such RAM capacity?

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[Richard Davis Jr.]

Les,

This is really neat!

Congrats.

Rick

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/b15084e1-c358-4127-bc27-5e17dbdb49e7n%40googlegroups.com.

[Les Bird]

Thanks Norby and Rick!

I almost gave up on this project. Quartus (the FPGA design software) is not the easiest piece of software to use and seems quite buggy but after pushing through a couple of weird Quartus bugs I was able to make some good progress with the FPGA layout design. Also the new 1.4 PCB fixed a couple issues I was having with the earlier boards. I received the new boards yesterday and after building it and plugging it in it immediately booted to the front panel so that was very exciting to see. Months of work is starting to pay off finally. Still lots to do but this is good progress.

Les

[norberto.collado koyado.com]

As I use Quartus a lot @Intel to flash the Server FPGA’s/CPLD, just let me know how I can help.

 

I have my own USB Blaster II to program FPGA’s as I was planning to develop a board to learn FPGA, but never got to it.

 

Which one you are using to update the FPGA?

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird

Sent: Friday, February 3, 2023 10:00 AM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Thanks Norby and Rick!

 

I almost gave up on this project. Quartus (the FPGA design software) is not the easiest piece of software to use and seems quite buggy but after pushing through a couple of weird Quartus bugs I was able to make some good progress with the FPGA layout design. Also the new 1.4 PCB fixed a couple issues I was having with the earlier boards. I received the new boards yesterday and after building it and plugging it in it immediately booted to the front panel so that was very exciting to see. Months of work is starting to pay off finally. Still lots to do but this is good progress.

 

Les

 

On Friday, February 3, 2023 at 9:23:20 AM UTC-7 rickdav...@gmail.com wrote:

Les,

 

This is really neat!

Congrats.

 

Rick

 

 

On Fri, Feb 3, 2023 at 9:46 AM Les Bird <lesb...@gmail.com> wrote:

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

 

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

 

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

 

 

 

On Monday, January 30, 2023 at 10:13:34 PM UTC-7 Norby wrote:

Very nice and thank you!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Peter Higgins <higgin...@gmail.com>
Date: Monday, January 30, 2023 at 2:39 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

This is the DE0-Nano board:

https://www.adafruit.com/product/451

Available from multiple vendors including Digi-Key and  Mouser for $115.

 

One of the contributors to the S100Computers Google Group has recently developed an FPGA development module for use with future S100 board designs. It uses the Efinix T35 FPGA core (with 180K of its own embedded RAM) and 64Mx16 of DDR3 RAM onboard. It costs under $100.

 

On Monday, January 30, 2023 at 1:11:16 PM UTC-8 Norby wrote:

Just curious how much the FPGA board costs with such RAM capacity?

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[Les Bird]

Norby,

The DE0-NANO has a built-in USB Blaster II so you can just program it directly.

I'm using Quartus Prime Lite V22.1std.

Would you like to get one of my FPGA boards? Let me know and I'll put it in the mail for you. You can get a DE0-NANO from Mouser for $115 along with the 74LVC245s (need 10 of them). Everything else to build the board is standard issue passives (2 resistors, ten 0.1uf filter caps, 2 LEDs and lots of jumpers and header pins). Pretty easy build.

Les

[norberto.collado koyado.com]

Thanks Les, but I have several boards in the queue to assemble and test. Also, I’m getting more boards from the pcb shop today. 

In addition, I need to build out new shiny H8 chassis which includes new H8 backplane + new front panel + new H37/H67 + new H17 + the list goes on. 

The H89 boards to finish..,

Also, I’m fixing Erick H8 system.

Once I’m done and nothing to do then I can get your FPGA board.

Thanks,

Norberto 

Get Outlook for iOS

---

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Les Bird <lesb...@gmail.com>
Sent: Friday, February 3, 2023 1:10:45 PM

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/e491528e-cb20-40aa-bc95-52dc89a31616n%40googlegroups.com.

[Peter Higgins]

Les - having already built a half dozen different FPGA-based boards for the S100 bus... if you are looking to have someone else try out a build of one of your FPGA boards for the H8 I am very interested in building one.

[Frank Madison]

Les, 

 

In case you have not yet figured out your keyboard problem, let me mention a problem I once found that may provide guidance.  The keys on the front panel do not have pull-downs.  They rely on 74xx TTL having current-mode inputs.  I tried using 74HCxx to replace a keyboard IC, and it did not work.  You may have to program your FPGA inputs to activate a pull-down resistors if they are available on the device that your are using.

 

Regards

 

Frank

Sent: Friday, February 03, 2023 at 7:46 AM
From: "Les Bird" <lesb...@gmail.com>

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/b15084e1-c358-4127-bc27-5e17dbdb49e7n%40googlegroups.com.

[norberto.collado koyado.com]

Yes, you are correct. The old FP keyboard inputs to the IC are floating as they are TTL, internally they will decode as a “1” level. A 74HCT will decode internally as a “0” and it won’t work. I fixed this on the new front panel, so you can use either IC 74LS or 74HCT. Also, same issue reported by Scott on the H17 74LS30 and fixed that as well as he was using the 74HCT family.

 

In Les case, based on the schematic, it could be his FPGA having issues reading on port 360Q that enables pin 1,19 on IC113, as long he is using the 74LS family for the line encoder IC.

 

As the FP LEDs are operational the FPGA writes are working.

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Frank Madison
Sent: Friday, February 3, 2023 10:06 PM
To: se...@googlegroups.com
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Les, 

 

In case you have not yet figured out your keyboard problem, let me mention a problem I once found that may provide guidance.  The keys on the front panel do not have pull-downs.  They rely on 74xx TTL having current-mode inputs.  I tried using 74HCxx to replace a keyboard IC, and it did not work.  You may have to program your FPGA inputs to activate a pull-down resistors if they are available on the device that your are using.

 

Regards

 

Frank

Sent: Friday, February 03, 2023 at 7:46 AM
From: "Les Bird" <lesb...@gmail.com>
To: "SEBHC" <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

 

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

 

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

 

 

 

 

On Monday, January 30, 2023 at 10:13:34 PM UTC-7 Norby wrote:

Very nice and thank you!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Peter Higgins <higgin...@gmail.com>
Date: Monday, January 30, 2023 at 2:39 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

This is the DE0-Nano board:

https://www.adafruit.com/product/451

Available from multiple vendors including Digi-Key and  Mouser for $115.

 

One of the contributors to the S100Computers Google Group has recently developed an FPGA development module for use with future S100 board designs. It uses the Efinix T35 FPGA core (with 180K of its own embedded RAM) and 64Mx16 of DDR3 RAM onboard. It costs under $100.

 

On Monday, January 30, 2023 at 1:11:16 PM UTC-8 Norby wrote:

Just curious how much the FPGA board costs with such RAM capacity?

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[Les Bird]

Peter, sure thing. DM me your address and I'll get one out to you.

Les

[Les Bird]

Frank,

Thanks for the tip. I did get it working but weirdly enough it was due to the Z80 core not running quick enough. I think the problem was it kept getting interrupted by the 2ms front panel interrupt and wasn't able to poll the keypad quick enough. Here's what I discovered, running the Z80 core at 2.08Mhz would not get any IOR to the front panel or it would get them but on very rare occasions. Once I bumped up the core speed to 4Mhz I started to get some activity on the keypad but it was not reliable. I bumped up to 5Mhz and it worked perfectly. I was getting reliable IOR on the front panel and inputting the "your h8 is up and running" test program worked fine.

I tried a bunch of things to work around this. For example, running the core at 5Mhz and outputting 2Mhz to the BUSS but that didn't work at all.

I think what I'm going to do is change out the core from T80s to maybe the A-Z80 to see if it operates better.

On the front panel I measured 49khz from the M1 line but it should be at a solid 249khz (based on real Z80 card). The INT1 (pin C on front panel) should be at a steady 500hz but I was seeing it bounce around from 420 to 508hz. So it seems like there are different timings when using the T80s core.

[norberto.collado koyado.com]

WOW! Will this be challenging to be able to boot from the H17 board due to the timing constants?

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird
Sent: Saturday, February 4, 2023 7:15 AM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

Frank,

 

Thanks for the tip. I did get it working but weirdly enough it was due to the Z80 core not running quick enough. I think the problem was it kept getting interrupted by the 2ms front panel interrupt and wasn't able to poll the keypad quick enough. Here's what I discovered, running the Z80 core at 2.08Mhz would not get any IOR to the front panel or it would get them but on very rare occasions. Once I bumped up the core speed to 4Mhz I started to get some activity on the keypad but it was not reliable. I bumped up to 5Mhz and it worked perfectly. I was getting reliable IOR on the front panel and inputting the "your h8 is up and running" test program worked fine.

 

I tried a bunch of things to work around this. For example, running the core at 5Mhz and outputting 2Mhz to the BUSS but that didn't work at all.

 

I think what I'm going to do is change out the core from T80s to maybe the A-Z80 to see if it operates better.

 

On the front panel I measured 49khz from the M1 line but it should be at a solid 249khz (based on real Z80 card). The INT1 (pin C on front panel) should be at a steady 500hz but I was seeing it bounce around from 420 to 508hz. So it seems like there are different timings when using the T80s core.

 

 

On Friday, February 3, 2023 at 11:06:29 PM UTC-7 Frank_M wrote:

Les, 

 

In case you have not yet figured out your keyboard problem, let me mention a problem I once found that may provide guidance.  The keys on the front panel do not have pull-downs.  They rely on 74xx TTL having current-mode inputs.  I tried using 74HCxx to replace a keyboard IC, and it did not work.  You may have to program your FPGA inputs to activate a pull-down resistors if they are available on the device that your are using.

 

Regards

 

Frank

Sent: Friday, February 03, 2023 at 7:46 AM
From: "Les Bird" <lesb...@gmail.com>

To: "SEBHC" <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

 

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

 

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

 

 

 

 

On Monday, January 30, 2023 at 10:13:34 PM UTC-7 Norby wrote:

Very nice and thank you!

 

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Peter Higgins <higgin...@gmail.com>
Date: Monday, January 30, 2023 at 2:39 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

This is the DE0-Nano board:

https://www.adafruit.com/product/451

Available from multiple vendors including Digi-Key and  Mouser for $115.

 

One of the contributors to the S100Computers Google Group has recently developed an FPGA development module for use with future S100 board designs. It uses the Efinix T35 FPGA core (with 180K of its own embedded RAM) and 64Mx16 of DDR3 RAM onboard. It costs under $100.

 

On Monday, January 30, 2023 at 1:11:16 PM UTC-8 Norby wrote:

Just curious how much the FPGA board costs with such RAM capacity?

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[Frank Madison]

Les,

 

I'm glad to hear that you have the problem figured out.  It would be nice if there were a Z80 core that was not only behaviorly the same as the Zilog device, but was electronically the same (providing the same timing). 

 

I've often thought of using programmable logic to combine all the "glue logic" on the H8.  Since that logic is mostly combinatorial rather than synchronous, timing would not be an issue.

 

I've been following your progress.  Keep up the good work.

 

Frank

 

 

Sent: Saturday, February 04, 2023 at 8:15 AM

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/a1bb5b0d-48f8-40a1-ab15-74de4473d023n%40googlegroups.com.

[Les Bird]

After lots of tuning I've made some good progress with the FPGA Z80 card. As shown in the screen shots I'm getting a solid 508Hz on the 2MS interrupt with the Z80 pushing 2.08MHz to the H8 BUSS and the Z80 core running at 25MHz.. On the M1 line I'm getting 347KHz which is a lot higher then the standard Z80 which is 249KHz. Might need to do some additional tweaking to get it down to where it needs to be. The front panel keypad is working perfectly and the LED display is rock solid.

I still have a lot to do but I'm thrilled with the results so far. It is currently running the 1K PAM8GO ROM.

[Les Bird]

Another pic of the display

[norberto.collado koyado.com]

Great Job Les!  I always said, nothing like the real hardware. When I did try to emulate the SASI bus with software on my first Z67-IDE controller, it was hard to get the correct timing under software. I was not able to get it run over 4MHz. The instructions, I had to pick the right ones with lower cycle times to maintain the correct timing. I almost spend a year on such controller to get it to work.

 

Then I decided to use the SASI controller to the job on the Z67-IDE+ and I got it running within weeks. The positive was that it was capable to boot up to 16MHz. Now with the Z180, it makes it easy to maintain such speeds.

 

Once more time I decided to do SASI under software control on the Z67-SD controller using new and cheaper microcontroller. It failed even to boot consistently at 2MHz. A total failure.

 

Now the new Z67-SD controller I will use again SASI controller to be able to maintain the necessary throughput.

 

On your FPGA design is not that easy, but it will take time and effort.

 

Keep the pictures coming…

 

Thanks,

Norberto

 

From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Les Bird

Sent: Tuesday, February 7, 2023 5:48 PM
To: SEBHC <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

 

After lots of tuning I've made some good progress with the FPGA Z80 card. As shown in the screen shots I'm getting a solid 508Hz on the 2MS interrupt with the Z80 pushing 2.08MHz to the H8 BUSS and the Z80 core running at 25MHz.. On the M1 line I'm getting 347KHz which is a lot higher then the standard Z80 which is 249KHz. Might need to do some additional tweaking to get it down to where it needs to be. The front panel keypad is working perfectly and the LED display is rock solid.

 

I still have a lot to do but I'm thrilled with the results so far. It is currently running the 1K PAM8GO ROM.

 

 

 

 

On Saturday, February 4, 2023 at 8:06:14 PM UTC-7 Frank_M wrote:

Les,

 

I'm glad to hear that you have the problem figured out.  It would be nice if there were a Z80 core that was not only behaviorly the same as the Zilog device, but was electronically the same (providing the same timing). 

 

I've often thought of using programmable logic to combine all the "glue logic" on the H8.  Since that logic is mostly combinatorial rather than synchronous, timing would not be an issue.

 

I've been following your progress.  Keep up the good work.

 

Frank

 

 

Sent: Saturday, February 04, 2023 at 8:15 AM

From: "Les Bird" <lesb...@gmail.com>
To: "SEBHC" <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

Frank,

 

Thanks for the tip. I did get it working but weirdly enough it was due to the Z80 core not running quick enough. I think the problem was it kept getting interrupted by the 2ms front panel interrupt and wasn't able to poll the keypad quick enough. Here's what I discovered, running the Z80 core at 2.08Mhz would not get any IOR to the front panel or it would get them but on very rare occasions. Once I bumped up the core speed to 4Mhz I started to get some activity on the keypad but it was not reliable. I bumped up to 5Mhz and it worked perfectly. I was getting reliable IOR on the front panel and inputting the "your h8 is up and running" test program worked fine.

 

I tried a bunch of things to work around this. For example, running the core at 5Mhz and outputting 2Mhz to the BUSS but that didn't work at all.

 

I think what I'm going to do is change out the core from T80s to maybe the A-Z80 to see if it operates better.

 

On the front panel I measured 49khz from the M1 line but it should be at a solid 249khz (based on real Z80 card). The INT1 (pin C on front panel) should be at a steady 500hz but I was seeing it bounce around from 420 to 508hz. So it seems like there are different timings when using the T80s core.

 

 

 

On Friday, February 3, 2023 at 11:06:29 PM UTC-7 Frank_M wrote:

Les, 

 

In case you have not yet figured out your keyboard problem, let me mention a problem I once found that may provide guidance.  The keys on the front panel do not have pull-downs.  They rely on 74xx TTL having current-mode inputs.  I tried using 74HCxx to replace a keyboard IC, and it did not work.  You may have to program your FPGA inputs to activate a pull-down resistors if they are available on the device that your are using.

 

Regards

 

Frank

Sent: Friday, February 03, 2023 at 7:46 AM
From: "Les Bird" <lesb...@gmail.com>

To: "SEBHC" <se...@googlegroups.com>
Subject: Re: [sebhc] Re: FPGA (again) and interfacing advice

Very excited to report that the FPGA Z80 CPU board is starting to show some life! :)

 

I'm using the PAM8GO ROM for starters and then I'll move on to XCON8 once I get PAM8GO working.

 

It is not reading the keypad though so I'll have to debug that but I'm excited to see that it is communicating with the front panel and displaying the PC address on the LEDs. I'm getting clean INT1's from the front panel finally (previously I was not able to get any INT1's) so this is a big step forward.

 

 

 

 

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/aa1f77f1-1ce4-4244-a408-643c02c3ec77n%40googlegroups.com.

[Frank Madison]

Les,

 

I'm only curious: whose Z80 core are you using, and which FPGA have you chosen?

 

My apologies if you have already explained these earlier.

 

Regards,

 

Frank

 

 

Sent: Tuesday, February 07, 2023 at 6:48 PM

To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/aa1f77f1-1ce4-4244-a408-643c02c3ec77n%40googlegroups.com.

[Les Bird]

Thanks Norberto.

I've been spending a lot of time trying to get this to work and it is a constant learning experience. I finally got the board design where it needs to be and now I'm trying to get the software side to work reliably and consistently. I'm making progress but still lots to do. I can totally understand what you're saying about nothing like the real hardware. This is more of a personal project to see if I can get it to work. I'll keep at it and see how far I can take it.

Les

[Les Bird]

Frank,

I am using the T80s core on a Terasic DE0-NANO. This is what it looks like when it's mounted on the board.

Les

[Les Bird]

For those who are following my H8FPGA project I created a GitHub repo here: https://github.com/lesbird/H8FPGA

There's some details about the project along with pictures and all of the current Quartus FPGA source files.

Les

[Frank Madison]

Les,

 

Thanks for sharing your progress.  Your layout looks very clean.

 

I see that you changed Z80 cores.  The beauty of configurable logic is that your can retain hardware while updating or improving firmware.

 

Opencores has a cycle-by-cycle compliant Z80 core.  I think that most of their cores have license fees, though.

 

Best of luck,

 

Frank Madison

 

 

Sent: Friday, February 10, 2023 at 9:47 PM

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