Scaling beyond 130nm dead or alive?
Andrew
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
Uncle Al
90 nm architecture is in commercial production. Pentiums pass 4 GHz
for Christmas. Don't get all excited; Intel CPUs are shit. AMD's
Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
and 64-bit chips with 100% x86 compatiblity. Everything you have is
already obsolete. It's only a matter of time unitl Win-64 and the
Blue Screen of Death breaks Mach 1.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
The Ghost In The Machine
In sci.physics, Uncle Al
<Uncl...@hate.spam.net>
wrote
on 5 May 2004 19:19:22 GMT
<c7ben...@enews4.newsguy.com>:
>
> Andrew wrote:
>>
>> In two related articles from www.physnews.com they seem to claim completely
>> different things:
>>
>> One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
>> 65 nm" http://www.physorg.com/news52.htm
>> And another "Scaling dead at 130-nm, says IBM technologist"
>> http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
>>
>> I'm really confused!!! One say we will never go over 90nm, and at the same
>> time Intel spends a lot of money to build a factory for 65nm!
>>
>> Your comments.
>
> 90 nm architecture is in commercial production. Pentiums pass 4 GHz
> for Christmas. Don't get all excited; Intel CPUs are shit. AMD's
> Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
> and 64-bit chips with 100% x86 compatiblity. Everything you have is
> already obsolete. It's only a matter of time unitl Win-64 and the
> Blue Screen of Death breaks Mach 1.
>
I think the viruses/worms/malware already did... :-)
When I first started employment I remember cleaning tapeups.
I'd be surprised if there are any left.
[ Sci.nanotech Moderator's Note: Since this has gone off-topic for sci.nanotech
the followup-to header has been set to exclude said group. -JimL ]
--
#191, ewi...@earthlink.net -- insert random "technological innovation" here
It's still legal to go .sigless.
John Larkin
I think that the point is that simple scaling - "die shrinks" - are no
longer feasible, as they were in the past. Time was, when you got
better process resolution, you could just crank the optics to reduce
an existing mask set. The physics has changed nonlinearly, so new
device designs are needed to exploit sub-100 nm features. Several
people have 90 nm stuff in production, but it ain't easy. At 50 nm and
down, whole new devices, finfets or something, will be needed.
John
Mark Thorson
John Larkin wrote:
> I think that the point is that simple scaling - "die shrinks" - are
> no longer feasible, as they were in the past.
Not to mention that smaller feature size is not the major driver of
so-called "Moore's Law". Crystal defect density has been the major
driver in recent years. Moore's Law says the number of transistors
per device doubles every two years. Scaling down the linear dimension
by 2 increases the transistor density by 4, but that's hard to do.
Decreasing the defect density allows you to build larger chips
that can be manufactured with acceptable yield. Feature size
may hit a law-of-physics stumbling block, but that will not happen
to advances in reducing defect density. Until we have single chips
the size of dinner plates, there will be room for improvement based
on defect density alone, which is the major driver for Moore's Law.
John Larkin
Good point. It's easier to cool a bigger chip, too.
Of course the other problem is: how much engineering does it take to
design a working billion-gate chip, and then who wants it?
Electronics is just about 100 years old, approaching a mature
industry.
John
Andrew
Right, I agree that Moore's Law can be driven by other factors than scaling.
But then I don't understand what they mean saying "65 nm technology
(process)", or even "45 nm", look here http://www.physorg.com/news74.html -
"East Fishkill, N.Y. and Seoul, Korea - March 5, 2004 - Samsung Electronics
joins a strategic semiconductor technology development partnership with IBM,
Chartered Semiconductor Manufacturing and Infineon. Initially, the four
companies will focus on 65 nanometer (nm) technology and will expand, over
time, to include 45 nm process development."
Do they mean something like "equivalent device size"? Like for gate
dielectric thicknesses. Or 45 nm is a real FET size?
"Mark Thorson" <nos...@sonic.net> wrote in message
news:c7gbk...@enews4.newsguy.com...
Phil Hobbs
Except that you can't cool them, and they'll tear the solder balls right out
of the module as they heat up. Maybe we can use elastic silicon ;-)
Cheers,
Phil Hobbs
Richard Henry
"Mark Thorson" <nos...@sonic.net> wrote in message
news:c7gbk...@enews4.newsguy.com...
> Moore's Law says the number of transistors
> per device doubles every two years.
Various sources cite 1 year, 18 months or two years, and target number of
devices, "complexity", power consumption and reliability as the factors and
objectives.
http://www.google.com/search?sourceid=navclient&ie=UTF-8&oe=UTF-8&q=moore%27s+law
Moore's paper appeared in 1965, when he was with Fairchild Electronics, in
Electronics Magazine, when that was still a meaningful publication.
Gordon D. Pusch
Phil Hobbs <pcdhSpamM...@us.ibm.com> writes:
Long before we reach that point, we will probably be forced to transition
from dissipative logic to reversible logic. (The only computing operations
that _have_ to generate heat are I/O operations.)
Nanotech will probably also require reversible logic, in order to avoid
cooking itself...
For links to reversible computing and its relation to nanotechnology,
see <http://www.zyvex.com/nanotech/reversible.html>.
For one group that has performed some excellent experimental research into
reversible computing, including building some prototype devices, see:
<http://www.elis.rug.ac.be/ELISgroups/solar/projects/computer.html>.
-- Gordon D. Pusch
perl -e '$_ = "gdpusch\@NO.xnet.SPAM.com\n"; s/NO\.//; s/SPAM\.//; print;'
lee_p...@yahoo.com
Maybe not so obvious from the eye catching title but the EE Times text
moderates it a little to say that "_traditional_ scaling" is dead. So
it depends on what you mean traditional scaling.
What do we mean by scaling anyways? Dennard from IBM set up some
"rules" way back in the 20th century saying CMOS designs can be
"scaled" by simultaneous and correlated reduction in things like oxide
thickness, length, width, supply voltages, junction depth, and doping.
The idea being that you can take any CMOS VLSI chip, multiply
everything by the magic scaling number, run it through newer tools and
{POOF} like a cookie recipe: you get the same design at lower cost
per chip. The magic number is traditionally set at 71% shrink (e.g.
65nm/90nm) per generation to area shrinks by half a la Moore's law.
Truth is it doesn't quite worked out quite so neatly. And each
generation it's getting harder to pretend that "scaling" applies at
all. Parameters "scale" unevenly -- at "65nm" maybe only one
parameter is actually equal or less than 65nm -- in spite of what the
"rules" say it should be. I get the sense that the IBM guy is talking
about these rules being dead rather than CMOS being dead.
Just FYI, these 90/65/45 nm "node" values are becoming something of a
marketing gimic... like CPU clock speed. For example read:
http://www.eet.com/showArticle.jhtml?articleID=18311172
But better believe that if Intel spends $2B, there is still some
economic sensibility to it. *Something(s)* about the new process will
be 65-ish nm or smaller. To make economic sense it will be also be
faster or cheaper or more complex or some other definition of
"better". In the end, the rules that count {for this scope of
discussion anyways} are economic rather than physical.
-Lee
"Andrew" <andr...@yahoo.com> wrote in message
news:<c7b3o...@enews3.newsguy.com>...
Phil Hobbs
Yeah, I know--I work in the building where reversible computing was invented,
many moons ago. If CMOS is really running into a brick wall, though,
there'll be enough blood on the landscape that we may all be out of work
before reversible computing becomes practical (if that ever happens).
There's a _lot_ of work going on just now on how to cool next-generation CMOS
without circulating water right to the chip level. People are even talking
about cutting channels into the back surface of the chips, to run cooling
water. I don't think things are quite that desperate, but we're clearly in a
new ballgame.
Cheers,
Phil Hobbs
Mark Thorson
Richard Henry wrote:
> Moore's paper appeared in 1965, when he was with Fairchild Electronics,
> in Electronics Magazine, when that was still a meaningful publication.
That's Fairchild Camera and Instrument, not Fairchild Electronics.
Andrew
<lee_p...@yahoo.com> wrote in message
news:c7hl1...@enews2.newsguy.com...
>
> Truth is it doesn't quite worked out quite so neatly. And each
> generation it's getting harder to pretend that "scaling" applies at
> all. Parameters "scale" unevenly -- at "65nm" maybe only one
> parameter is actually equal or less than 65nm -- in spite of what the
> "rules" say it should be. I get the sense that the IBM guy is talking
> about these rules being dead rather than CMOS being dead.
This is exactly my question. Are those 65 or 45 nm real CMOS dimensions or
that are fake "equivalent" numbers, that only represent higher computer
power?
If second is the case, then some definitions for "equivalency" must already
be revealed, but I've never heard about that yet.
Mark Thorson
John Larkin wrote:
> Of course the other problem is: how much engineering does it take
> to design a working billion-gate chip, and then who wants it?
That's like asking "Who would ever need more than 64K of RAM?".
John Larkin
On 8 May 2004 06:00:23 GMT, Phil Hobbs
<pcdhSpamM...@us.ibm.com> wrote:
>
>Yeah, I know--I work in the building where reversible computing was invented,
>many moons ago. If CMOS is really running into a brick wall, though,
>there'll be enough blood on the landscape that we may all be out of work
>before reversible computing becomes practical (if that ever happens).
>There's a _lot_ of work going on just now on how to cool next-generation CMOS
>without circulating water right to the chip level. People are even talking
>about cutting channels into the back surface of the chips, to run cooling
>water. I don't think things are quite that desperate, but we're clearly in a
>new ballgame.
>
>Cheers,
>
>Phil Hobbs
>
>
I wish somebody would start mass-producing cheap bulk monocrystalline
diamond, preferably the single-isotope kind.
John
John Larkin
Nothing grows exponentially forever. The problem in today's
electronics industry is increasingly the difficulty of finding a
"killer ap" to absorb the incredible amount of compute and storage
capacity now available. Most people haven't bothered to install 2G of
ram in their PCs, even though it's now cheaper than 64K was a decade
or so ago. My 700 MHz Dell has 128M of ram, and works fine, even for
circuit simulation and CAD use.
Huge-capacity nanotech data storage (if it ever works) may just be in
time for the tail end of a boom, when nobody has a really good use for
it. Storing lots of violent movies might be cool, but is hardly any
sort of boon to humanity.
John
Mark Thorson
John Larkin wrote:
> Huge-capacity nanotech data storage (if it ever works) may just
> be in time for the tail end of a boom, when nobody has a really
> good use for it. Storing lots of violent movies might be cool,
> but is hardly any sort of boon to humanity.
You will need it to run a) the latest release of Windows, and
b) to be able to run any two Adobe tools simultaneously. :-)
Uncle Al
John Larkin wrote:
>
> On 8 May 2004 06:00:23 GMT, Phil Hobbs
> <pcdhSpamM...@us.ibm.com> wrote:
>
> >
> >Yeah, I know--I work in the building where reversible computing was invented,
> >many moons ago. If CMOS is really running into a brick wall, though,
> >there'll be enough blood on the landscape that we may all be out of work
> >before reversible computing becomes practical (if that ever happens).
> >There's a _lot_ of work going on just now on how to cool next-generation CMOS
> >without circulating water right to the chip level. People are even talking
> >about cutting channels into the back surface of the chips, to run cooling
> >water. I don't think things are quite that desperate, but we're clearly in a
> >new ballgame.
> I wish somebody would start mass-producing cheap bulk monocrystalline
> diamond, preferably the single-isotope kind.
Kilo crystals? We're working on it. 6 months or never.
Machinist, "Hell, I can drill through the old reactor head. Keep the
new blank."
The old head started as T-316SS that had been heated to 800+ C for a
total of nearly 200 hours. It contained molten Devil Solvent all that
time. It's an inch+ thick, too. The head wasn't barrier-plated.
What could happen to an inch of 316SS? We ruined TiN-coated drill
bits trying to get into it.
Machinist, "Do you still have the blank head?"
We had a big pure copper pipe endcap as spill containment in the
reactor, for the inner pot that held Devil Solvent. Copper shatters
like glass after Devil Solvent, which is no big deal if it sits
there. Turns out Devil Solvent also vapor-transports at temp, so
spill containment is moot. The copper endcap expanded 8% in all
dimensions. We can't imagine what is in there with the metal. It
still looks like its mates, but it's bigger.
The chemistry and now the engineering seem to be under control. We're
going for a third and final set of runs. Chemical precursor
progressively reacts to elemental carbon under local energetic
conditions. Diamond persists in molten Devil Solvent, graphite
furiously (oh yes indeed - no densified graphite containment) erodes
away. Boron doping to give Type IIb blue diamond that phosphoresces
red for 60-90 seconds after 254 nm UV excitation. If we make diamond
it we'll find it - like everything else we do, working in the dark.
--
Uncle Al
http://www.mazepath.com/uncleal/qz.pdf
http://www.mazepath.com/uncleal/eotvos.htm
(Do something naughty to physics)
Mark Thorson
Phil Hobbs wrote:
> Except that you can't cool them, and they'll tear the solder balls right out
> of the module as they heat up. Maybe we can use elastic silicon ;-)
Close. The connections will be compliant, as in packages
pioneered by Tessera (http://www.tessera.com).
To connect to a whole wafer, you might use spring-based
probes, like FormFactor does (http://www.formfactor.com).
Of course, why a wafer the size of a dinner plate need to
have any large number of connections? If it has a video
output, stereo output, couple of USB plugs, and a few
other things, that can be done in a small number of pins.
You could put them in the center, like is done now for
flip-chip, to minimize solder ball stress caused by temperature
cycling and CTE mismatch. By then, of course, we won't
be using lead-based solder anymore. Raising this issue
is like proving airplanes are impossible because physical
laws dictate a minimum power-to-weight ratio for steam
engines.
John Larkin
Once we do have slabs of diamond in the McMaster catalog, how will we
machine it? For semiconductor heat spreaders, all we'd really need is
little blocks of the stuff, maybe no holes at all, so we could buy
standard sizes. But what's a good way to, say, machine holes in the
stuff? I did a motion-control thing (a magnetic field mapper) on a big
slab of granite, and that was bad enough.
Isotopically pure diamond would have a thermal conductivity/dielectric
constant ratio about 400:1 better than, say, BeO; makes me salivate
just thinking about it.
Let me know when you have samples available.
John
Uncle Al
John Larkin wrote:
>
> On 9 May 2004 02:32:29 GMT, Uncle Al <Uncl...@hate.spam.net> wrote:
>
> >
> >> I wish somebody would start mass-producing cheap bulk monocrystalline
> >> diamond, preferably the single-isotope kind.
> >
> >Kilo crystals? We're working on it. 6 months or never.
[snip]
> Once we do have slabs of diamond in the McMaster catalog, how will we
> machine it?
Laser it.
> For semiconductor heat spreaders, all we'd really need is
> little blocks of the stuff, maybe no holes at all, so we could buy
> standard sizes. But what's a good way to, say, machine holes in the
> stuff? I did a motion-control thing (a magnetic field mapper) on a big
> slab of granite, and that was bad enough.
If diamond goes cheap, big blocks of the stuff - silicon-on-diamond;
or at least the back plane of the chip package. Big heat spreader
brazed to the base of your heatsink.
> Isotopically pure diamond would have a thermal conductivity/dielectric
> constant ratio about 400:1 better than, say, BeO; makes me salivate
> just thinking about it.
>
> Let me know when you have samples available.
It's completely speculative at this point. Experimental reduction to
practice is finally straightforward. Our rational target is
abrasive. Cheap diamond dust fill for thermally conductive epoxy
might be attractive. Growing diamond by chemical synthesis out of
molten salt has a potential yield in excess of one carat/hr-cm^2.
Imagine a meter^2 sheet lowered into a vat. 24 hrs later you pull out
100 kg of diamond (both sides plus edges). Even if it is only
abrasive it beats the heck out of any other process - material
throughput, energy costs. So, we'll look.
Bulk carburundum synthesis is not any good for Moissanite gems. Our
process might never threaten de Beers. "8^>)
Mark Thorson
John Larkin wrote:
> Once we do have slabs of diamond in the McMaster catalog, how
> will we machine it? For semiconductor heat spreaders, all we'd
> really need is little blocks of the stuff, maybe no holes at all,
> so we could buy standard sizes. But what's a good way to, say,
> machine holes in the stuff?
Would >90% diamond be good enough? You can get
epoxy molding compound for plastic-packaged
integrated circuits from Sumitomo Bakelite
that is >90% silica. A diamond-filled polymer can
be cast and cured. It might be machinable.
John Larkin
Filled epoxies aren't especially good thermal conductors and, unless
the particle size is really small, they enforce a gap that wrecks
thermal performance. The value of chunky monochrystalline diamond
would be as a heat spreader between a chip and the main aluminum or
copper heat sink. Sub-50 nm CMOS chips will probably have outrageous
power densities, and the hotter they run the slower they run.
Right now, about the best you can do (dry) is to use a solid copper
heat sink, machined very flat, and clamp the IC package down with a
bit of silicone grease in the gap. You'd probably do the same if the
heatsink were diamond, unless the silicon were truly bonded to the
diamond somehow.
The nano-channel air-cooling thing (as mentioned in another post here)
seems preposterous to me, another case of wild extrapolation without a
hint of calculation.
Seems like, in the end, all problems are thermal problems.
John
Uncle Al
The thermal density of future chips is appalling. We are staring down
100+ watts in an area the size of a postage stamp. The damning volume
is the millimeter or two between the chip and its thermal sink. You
need a heat spreader (diamond; or Moissanite as less good, less
expensive fallback), a cold plate, and a way to get rid of all that
heat.
Frank refrigeration (FREON!) works, but that is adding 300-500 watts
to your box plus the noise. Peltier coolers work, but you would
conservatively need 4X refrigeration power, and two or three stages
multiplying that, and you'd have to dump (way more!) Peltier heat.
Water + antifreeze is marginal (viscosity), and you are back to the
refrigerator. Or plumb the CPU package itself and blow through cold
Freon, or make it the inside of a heat pipe. This is potentially
tough on the leads from turbulence and summed mechanical trauma.
Enviro-whiner hydrochlorofluorocarbons instead of a Freon would give
you a MTBF of about 6 months from corrosion, and the stuff is
intensely tumorigenic by inhalation.
Now worry mismatched thermal coefficients of expansion and condensing
moisture in humid climates. A kilowatt box left on 24/7 gets
expensive.
A solid or sintered diamond package gets you at least 4X the thermal
conductivity of copper. Silicon-on-diamond would be grand if clean
monocrystal slabs of diamond were cheaply available. Diamond dust
wholesales for about $(US)1/gram. If it dropped by a factor of 100,
$10/kg, it would edge into being attractive. Processed sheets of
diamond a millimeter or two thick at less than $1/cm^2 would be nice.
We need a rapid, economic route to synthesize bulk diamond. CPUs to
monster travelling wave tube amplifiers, bulk monocrystal diamond is
the stuff of an advanced civilization. Arguments about the gem
market are small stuff by comparision.
John Larkin
On 10 May 2004 16:00:31 GMT, Uncle Al <Uncl...@hate.spam.net> wrote:
>A solid or sintered diamond package gets you at least 4X the thermal
>conductivity of copper. Silicon-on-diamond would be grand if clean
>monocrystal slabs of diamond were cheaply available. Diamond dust
>wholesales for about $(US)1/gram. If it dropped by a factor of 100,
>$10/kg, it would edge into being attractive. Processed sheets of
>diamond a millimeter or two thick at less than $1/cm^2 would be nice.
"Thin heat spreader" is sort of an oxymoron, no? What we need is a
cube or cylinder of diamond embedded in a copper heatsink, to spread
the heat laterally.
John
Gordon D. Pusch
Uncle Al <Uncl...@hate.spam.net> writes:
> The thermal density of future chips is appalling. We are staring down
> 100+ watts in an area the size of a postage stamp. The damning volume
> is the millimeter or two between the chip and its thermal sink.
> You need a heat spreader (diamond; or Moissanite as less good, less
> expensive fallback), a cold plate, and a way to get rid of all that heat.
As I've noted earlier, a =FAR= better solution is to simply start using
reversible logic. The only computing operations that _have_ to generate
heat are the I/O operations.
Furthermore, even using CMOS logic, substantial opportunities for reducing
the heat that is dissipated exist (for example, google on "hot-clock seitz").
An excellent set of lecture notes on reduced energy-dissipation computing
may be found at: <http://www.cs.caltech.edu/~cs181/97-98/181a/lectures/14.ps>.
Molecular electronics will almost certainly have to use mostly or entirely
reversible logic to avoid cooking itself. Nanotech will likewise almost
certainly have to use reversible logic. (Note to Drexlerians: "Rod logic"
is =NOT= reversible, and I do not see a particularly rosy future for it.)
Quantum computers must _NECESSARILY_ be reversible, since irreversiblity
would violate the unitarity of the q-comp's evolution operator.
Additional references on reversible computing, including its relevance to
nanotech:
<http://www.cise.ufl.edu/~mpf/rc/home.html>
<http://www.cise.ufl.edu/research/revcomp/writing.html>
Eivind Kjorstad
Gordon D. Pusch wrote:
> Uncle Al <Uncl...@hate.spam.net> writes:
> As I've noted earlier, a =FAR= better solution is to simply start
> using reversible logic.
I don't think there's anything "simply" about that proposition. It's
akin to countering an argument about the pollution from coal
power-plants with "a =FAR= better solution is to simply start using
fusion."
Fact is, noone has a *clue* how we would do that. There's research
underway, and quite a bit of theorethical stuff has been done, but this
far, in the real world, I'm not aware of even a two-bit adder using
reversible logic existing in the lab.
Yes, it's possible we'll still solve it in 10 or 20 years. Or maybe
it'll be another one of those technologies that in 10 or 20 years will
still be 10 or 20 years away, time will show.
> The only computing operations that _have_ to
> generate heat are the I/O operations.
That is true in the same way that an elevator deosn't _have_ to spend
energy.
> Furthermore, even using CMOS logic, substantial opportunities for
> reducing the heat that is dissipated exist (for example, google on
> "hot-clock seitz"). An excellent set of lecture notes on reduced
> energy-dissipation computing may be found at:
> <http://www.cs.caltech.edu/~cs181/97-98/181a/lectures/14.ps>.
That, however is something we *do* know how to do. It's only that it
hasn't made economical sense yet. We know how to make considerably more
computing-pro-watt than we do in the typical desktop-machine, the only
reason we don't is that it doesn't pay. For example, the typical
laptop-processor has considerably more computing-power pro/watt, and
there's no reason we couldn't use those processors everywhere.
Computing-power goes up. Heat-generation also goes up. However, the
heat-generation goes up a lot less than the Computing-power.
> Molecular electronics will almost certainly have to use mostly or
> entirely reversible logic to avoid cooking itself. Nanotech will
> likewise almost certainly have to use reversible logic.
I'm not sure thats true. You should remember that when you are small,
you have a huge surface-to-volume ratio, that makes it easier to get
rid of heat. Also, diamond ain't exactly the poorest heat-conductor on
the planet.
Consider this;
Let's say todays cpus aproximate 100 watts in a 1cm**3 cube. Such a cube
has a surface of 6cm**2, so they need to, on the average, lose 16
watts/cm**2, tricky, but workable.
That power-density in a bigger machine is however hard to imagine.
Consider a 1m**3 machine with the same power-density. It'd use 100
million watts and have a surface of 6m**2, so it would need to lose, on
the average 1600w/cm**2 trough that surface to avoid cooking itself.
Scaling the thing up by a factor of 100 in each dimension gives you 100
times the cooling-problem. (since surface goes up with dimension**2 and
volume with dimension**3)
Similarily, if we where to somehow shrink the current day cpu with 2
orders of magnitude, from 1cm to 0.1 mm (I'm aware that that would
involve crashing into other physical contraints) then the
cooling-problem would decrease by a factor of 100. Or put another way,
a 0.1mm cube could have *100* times the power-density of a current-day
cpu, and still be faced with a cooling-problem no worse than that of
the cpu.
Excess heat is a problem in large structures much more than in small
ones.
Sincerely,
Eivind Kjrstad
mme...@cars3.uchicago.edu
>
>Consider this;
>
>Let's say todays cpus aproximate 100 watts in a 1cm**3 cube. Such a cube
>has a surface of 6cm**2, so they need to, on the average, lose 16
>watts/cm**2, tricky, but workable.
>
>That power-density in a bigger machine is however hard to imagine.
>Consider a 1m**3 machine with the same power-density. It'd use 100
>million watts and have a surface of 6m**2, so it would need to lose, on
>the average 1600w/cm**2 trough that surface to avoid cooking itself.
>
>Scaling the thing up by a factor of 100 in each dimension gives you 100
>times the cooling-problem. (since surface goes up with dimension**2 and
>volume with dimension**3)
>
>Similarily, if we where to somehow shrink the current day cpu with 2
>orders of magnitude, from 1cm to 0.1 mm (I'm aware that that would
>involve crashing into other physical contraints) then the
>cooling-problem would decrease by a factor of 100. Or put another way,
>a 0.1mm cube could have *100* times the power-density of a current-day
>cpu, and still be faced with a cooling-problem no worse than that of
>the cpu.
>
>Excess heat is a problem in large structures much more than in small
>ones.
>
generation, per unit volume, in the Sun and in the human body.
Mati Meron | "When you argue with a fool,
me...@cars.uchicago.edu | chances are he is doing just the same"
John Larkin
>Yes, it's possible we'll still solve it in 10 or 20 years. Or maybe
>it'll be another one of those technologies that in 10 or 20 years will
>still be 10 or 20 years away, time will show.
A recent trend in technology forecasting - especially popular in
nanotech journalism - is to assign the number of years it will take to
commercialize any discovery. "Impossible" generally maps to about
10-15 years, and "really, stupidly impossible" stretches out to maybe
30.
John
Phil Hobbs
nanotechnology, while initially thin, appears to have run its course so I
am setting the "Followup-to" to exclude sci.nanotech. Posters are welcome to
re-include sci.nanotech if they think their response is topical here.
Now on with Phil Hobbs interesting reply.... -JimL ]
We obviously don't live in the same world. People where I work actually have
to do this stuff for real, and it isn't anything like as simple as you make
out. Even with perfectly matched CTEs, just the *gradients* due to a
100W/cm**2 power dissipation level make everything want to roll up into a
ball. Talking as though the interconnect were just a matter of plugging a
keyboard and USB cable into a wafer-scale device shows very little
understanding of the problems of the day.
Interconnect densities are currently above 3000 leads per module, and heading
up--one high performance design study I'm aware of needs over 7000, just to
get all the terabits-per-second off the module. (Current products are around
1 Tb/s total off-board I/O for a board with one module on it, and it's going
to go much higher.) Just powering the thing takes 100 amps per square
centimetre of chip surface, from a 1-V power supply, whose total impedance
has to be well below *1 milliohm* at all frequencies of interest. Power,
ground, and bypass caps have to be sprinkled *very* uniformly across the face
of the chip, just to avoid logic errors due to power and ground bounce.
Spring clips and so on lead to scrubbing action at connector surfaces, which
is a reliability headache. You can't simply suspend a dinner-plate-sized
module on legs near the centre, because it won't stand shock testing, and has
to hold up a big copper plate heat sink. And so on and so on.
These things can be overcome--comparable ones in the past were--but in real
engineering, it has to be cheap and reliable as well as everything else.
Huge chips are probably not the most cost-effective solution.
Cheers,
Phil Hobbs
Advanced Optical Interconnect
IBM T.J. Watson Research Center
Yorktown Heights NY
Fleetie
"Uncle Al" <Uncl...@hate.spam.net> wrote
> 90 nm architecture is in commercial production. Pentiums pass 4 GHz
> for Christmas. Don't get all excited; Intel CPUs are shit. AMD's
> Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
> and 64-bit chips with 100% x86 compatiblity. Everything you have is
> already obsolete. It's only a matter of time unitl Win-64 and the
> Blue Screen of Death breaks Mach 1.
Ah, I haven't been here in this newsgroup for over a year, I think.
But it's great to see Dr. Schwartz is still here putting out the
word!
And yes, it's appalling how bad Intel CPUs are at FP. I wrote a
little noddy benchmark proggy just after I got this Athlon 2000
a couple of years ago. Very roughly it whooped an equivalently-
clocked Pentium by about a factor of THREE! Even writing this I
have difficulty believing that, but such is my memory. In a way,
I hope I'm wrong about it.
"How long do we wait until 64 bit and Windows are mature enough to be
worth buying?", I wonder.
Martin
--
M.A.Poyser Tel.: 07967 110890
Manchester, U.K. http://www.fleetie.demon.co.uk
Mark Thorson
> And yes, it's appalling how bad Intel CPUs are at FP. I wrote a
> little noddy benchmark proggy just after I got this Athlon 2000
> a couple of years ago. Very roughly it whooped an equivalently-
> clocked Pentium by about a factor of THREE! Even writing this I
> have difficulty believing that, but such is my memory. In a way,
> I hope I'm wrong about it.
This reminds me of someone I knew who bought a new machine.
He wrote a little benchmark and set it for a miilion iterations.
POW! It came right back. "Gee, that's pretty fast," he thought.
(This was in the days of 386 machines.)
Then he set it for 10 million iterations. POW! It came right back.
Now he knew something was wrong. He popped the object code into the
debugger, and he discovered his compiler had realized no products of the
loop were being examined, and it removed the loop from his program.
Perhaps you are observing a difference in the compilers used
for Intel vs. AMD machines?
Uncle Al
MS C++ compilers (and apparently other Mickeycrap compilers)
automatically default long_double_precision in source code to
double_precision executables. No flags, no warnings, no
documentation. This gives a considerable speed advantage over
properly compiled source code, albeit with some sacrifice of meaning
(all of it) in the data.
In running parity divergence calculations on large lattices
(10^12-10^18 atoms) we found a single Intel 3.2 GHz Xeon throughput
40-60% less/clock cycle than a single 2.8 GHz AMD Opteron-244, both
running under Linux. Running parallel, we had 16 Opteron-848s pulling
an honest 4+ GFLOPS each continuous (40 days of donated access
overall), plus incredible bursts when it was lattice growth only. The
G5 processor farm at Virginia Tech probably would have done better,
but it wasn't free. You'd need some dozens of Xeons in parallel to
compete. Xeons have tiny CPU caches, memory controller off CPU, and
no coherent HyperTransport. Running Xeons in parallel is a bad joke.
Hint: If you are doing serious crunching, it isn't the compiler.
Russell Wallace
(Gordon D. Pusch) wrote:
>Long before we reach that point, we will probably be forced to transition
>from dissipative logic to reversible logic. (The only computing operations
>that _have_ to generate heat are I/O operations.)
(I posted this earlier on comp.arch, but perhaps someone here may know
the answer...)
On thermodynamic grounds it's expected that reversible computing could
reduce heat dissipation - very relevant today since heat dissipation
is becoming an important limiting factor on the performance of
computers.
At first glance, though, it would seem that running most algorithms on
a reversible computer would just replace the consumption of power to
erase N words of memory, with the consumption of N words of memory -
which means you quickly end up running out of memory and have to
switch to irreversible mode and erase used memory cells after all, so
no gain.
But on http://www.kuro5hin.org/story/2003/9/8/14125/70302 I found the
following claim:
"The actual limitations of reversible computing are small:
The number of bits input to the computation must be the same as the
number of bits that the computation outputs. Call this N.
The number of bits that a reversible computation needs to remember at
any point is also N.
Given a irreversible computation with Ni input bits and No output
bits, it is possible to produce a reversible computation with N not
greater than Ni + No."
Does anyone know of any examples of how this might be done with
practical algorithms? (Google shows me lots of articles on how to
reversibly do the equivalent of NAND, but I'm interested in how to
reversibly do things like sorting, matrix multiplication or alpha-beta
minimax.)
--
"Sore wa himitsu desu."
To reply by email, remove
the small snack from address.
Paweł Kasprzak
You're right about the movies. But if you try to install and run some 3D
software or just some graphic tools commonly used on the market, you'll see
the reason of installing some extra RAM etc.
Also I bet new Windows would kill your mashine even if "system requirements"
would let you run the installation at all. Ordinary word processing software
shouldn't take this much of your CPU, right? Try to find the version of MS
word that could be launched from your old trusty 386 machine. Were those
version bad? Raising our hardware requirements is part of the game. The days
when guys cared for memory used by the codes they developed are all gone.
Uytkownik "John Larkin" <jjla...@highlandSNIPtechTHISnologyPLEASE.com>
napisa w wiadomoci news:c7jl7...@enews3.newsguy.com...
John Baliga
These numbers are characteristic dimensions of features (DRAM half-pitch,
etc.). Essentially, you can think of these numbers as the gate width.
There does not seem to be any reason not to be able to make things this
small. The big problem is the on-chip wiring. About now, there is about 9
layers of thin, skinny copper wiring on top-of-the-line chips (I say
top-of-the-line in terms of manufacturing acheivement, not performance).
At some point, you would be making tiny transistors buzzing away like crazy
that are farther apart from each other than was the case in the previous
generation, because the wiring would limit the performance too much if they
were spaced closer together. The cost advantage of puting more transistors
per unit area would disappear, and the cost would go up fast.
This is why people are looking at 3D ICs and such: interconnection.
---> Insert shameless plug for the article I wrote in the March 2004 issue
of IEEE Spectrum. The money keepers need to understand this stuff before the
engineers have a chance to do what they need to do. <---
John Baliga
jba...@triton.edu
"Andrew" <andr...@yahoo.com> wrote in message
news:c7gu...@enews4.newsguy.com...
>
> Right, I agree that Moore's Law can be driven by other factors than
scaling.
> But then I don't understand what they mean saying "65 nm technology
> (process)", or even "45 nm", look here
http://www.physorg.com/news74.html -
> "East Fishkill, N.Y. and Seoul, Korea - March 5, 2004 - Samsung
Electronics
> joins a strategic semiconductor technology development partnership with
IBM,
> Chartered Semiconductor Manufacturing and Infineon. Initially, the four
> companies will focus on 65 nanometer (nm) technology and will expand, over
> time, to include 45 nm process development."
>
> Do they mean something like "equivalent device size"? Like for gate
> dielectric thicknesses. Or 45 nm is a real FET size?
>
>
>
> "Mark Thorson" <nos...@sonic.net> wrote in message
> news:c7gbk...@enews4.newsguy.com...
Uncle Al
is, in the opinion of the moderator, not topical for that group so the
group has been removed from the Newsgroups line. -JimL ]
John Baliga wrote:
>
> These numbers are characteristic dimensions of features (DRAM half-pitch,
> etc.). Essentially, you can think of these numbers as the gate width.
>
> There does not seem to be any reason not to be able to make things this
> small. The big problem is the on-chip wiring. About now, there is about 9
> layers of thin, skinny copper wiring on top-of-the-line chips (I say
> top-of-the-line in terms of manufacturing acheivement, not performance).
>
> At some point, you would be making tiny transistors buzzing away like crazy
> that are farther apart from each other than was the case in the previous
> generation, because the wiring would limit the performance too much if they
> were spaced closer together. The cost advantage of puting more transistors
> per unit area would disappear, and the cost would go up fast.
>
> This is why people are looking at 3D ICs and such: interconnection.
>
> ---> Insert shameless plug for the article I wrote in the March 2004 issue
> of IEEE Spectrum. The money keepers need to understand this stuff before the
> engineers have a chance to do what they need to do. <---
>
> John Baliga
> jba...@triton.edu
Current architecture is 130 nm. 90 nm will be on the shelves and all
the rage by Christmas. Intel boasts of one more turn of the Moore's
Law screw with a new dielectric, the new fab being built.
AMD is already 64-bit hardware and OS, showing the incredible
advantages of coherent HyperTransport in clustered CPUs plus memory
management on CPU (3 GHz) rather than mobo (0.8 GHz). The Apple G5 is
winner hardware, with two CPUs and an adequate (i.e., Unix not
Windows) operating system. Intel chips cannot be efficiently
parallelized or clustered. Windows has *never* worked.
A CPU that is thick rather than areal has truly nasty heat removal
challenges.
Andrew
Dear John,
Thank you for that answer.
I do agree with you about interconnection problem.
But it also sounds from your post like this interconnection problem is
the only problem that exists and as you write, "there does not seem to
be any reason not to be able to make things this small".
I cannot agree on that.
I've intentionally looked to International Technology Roadmap for
Semiconductors web-site http://public.itrs.net/
They have a list of Grand Challenges for the near (<=2007) and
long-term (beyond 2008)
On the first place they set low gate leakage current saying that
high-k must already be implemented in 2005 (to me they already are,
look for instance here http://www.physorg.com/news80.html)
Then they say about large area substrates (300 mm).
Then there are several problems with lithography listed, as
mask-making and process control.
And finally we come to interconnect, which is also a great challenge.
See the whole list of challenges here
http://public.itrs.net/Files/2002Update/2002Update-GrandChallenges.pdf
Best regards,
Andrew
"John Baliga" <jba...@triton.edu> wrote in message
news:<c8c41...@enews1.newsguy.com>...
Robert I. Eachus
I thought about not posting this to the nanotech group, since it talks
mostly about semiconductor technology. But I can't really say it is not
about nanotechnology, since it discusses how the semiconductor industry
is reaching the nanoscale. I did eliminate sci.physics and
sci.materials though...
lee_p...@yahoo.com wrote:
> Just FYI, these 90/65/45 nm "node" values are becoming something of a
> marketing gimic... like CPU clock speed. For example read:
> http://www.eet.com/showArticle.jhtml?articleID=18311172
>
> But better believe that if Intel spends $2B, there is still some
> economic sensibility to it. *Something(s)* about the new process will
> be 65-ish nm or smaller. To make economic sense it will be also be
> faster or cheaper or more complex or some other definition of
> "better". In the end, the rules that count {for this scope of
> discussion anyways} are economic rather than physical.
Hmmmm. Looking at the article on Sony's "90 nm" chip, the 0.13 micron
AMD Slegehammer and Clawhammer CPUs have twice as many transistors
(103.5 million) in almost exactly twice the chip area (193 sq mm).
Looks to me like Sony got caught with their pants down. But Intel is
now shipping Prescott and Dothan made using their 90 nm process. The
Prescott is running pretty hot, but for reasons that seem to be
architectural not a property of the process. The Dothan processor
delivers about the same performance, but at one fifth the power
requirements.
AMD should introduce its 90 nm version of Hammer in a few months. IBM is
also in the same tier of semiconductor companies. But I don't expect
Sony to be able to manufacture a "real" 90 nm chip before next year.
As for the original topic, yes, the point of the IBM speaker was not
that there is a brick wall at 90 nm, but that from here on down each new
scale factor will require complete redesigns, not just applying scaling
factors. In fact, that is exactly the problem that Intel ran into with
Prescott. You can read the Intel technical documentation if you want
further details, but they changed the entire technology of the integer
engine--it isn't really CMOS. Since the RAE runs at twice the clock
speed of the rest of the chip, Intel did this to be able to get to 4 GHz
and beyond (8 GHz for the RAE). But it does make the chip pretty hot.
Dothan at 2 GHz is much cooler--but does about 60% more work per clock
cycle than Prescott. So a 2 GHz Dothan on average performs the same as
a 3.2 GHz Northwood or Prescott.
I don't expect Intel to ever release the 65 nm sucessor to Prescott, but
there will also be several 65 nm successors to Dothan, some aimed at the
desktop. So in effect, the redesign of Banias (Pentium-M) that is
Dothan succeeded, the redesign of Northwood that is Prescott is
marginal. We will see this sort of thing at every successful
semiconductor company from here on forward. But my guess is only a
dozen or so semiconductor companies will ever have a successful 90 nm
design. This will include AMD, IBM, Intel, and TI, plus a few of the
DRAMuri. The number may drop to about eight or less at 65 nm. The fab,
process development, and design costs are just getting too high. Even
trying to manufacture 90 nm parts at merchant fabs such as Chartered,
UMC and TSMC is causing lots of problems for "fabless" semiconductor
companies.
Notice that I am definitely not predicting "the end of Moore's Law."
Just that only a few companies will continue to build chips at the
bleeding edge. In a few years though, there will be only a few new chip
designs per year that will be made in sufficient volume to justify the
development costs. This is what has killed the Alpha and PA-RISC
architectures and will kill SPARC and Power. Not a real problem though.
Sun is migrating to AMD's Hammer, as is Cray. There are also top
supercomputers right now that use Intel Xeon chips, and PowerPC chips.
In the future there will be only a few CPU architectures available,
perhaps only one. It is hard to name that one right now, not because it
is hard to define, but because the name is changing in several ways.
AMD originally called it x86-64, but it is usually now called AMD64.
Intel, of course, wouldn't use that name, and tried IA32e, and seems to
have settled on EM64T. In any case, Intel's version has only a few
minor differences from AMD's. AMD is adding the SSE3 instructions while
Intel will eventually add the NX bit, so they will converge even more.)
I can't say for sure where other players in the game will drop out. But
AMD is building a new fab, Fab 36 adjacent to Fab 30 in Dresden, that is
planned to manufacture chips at the 65, 45, and 35/32 nm process nodes.
Intel has also build a facility (D1D) for 65 nm development, and
should be on board at least through 35 nm. Recent developments in
lithography mean that 35 nm should be doable with ArF (193 nm) excimer
lasers. (The two key developments for the future are immersion lenses
with high Numerical Aperature, and radially polarized optics. The 65 nm
node is reachable with current resolution enhancement techniques such as
OPC and AAPS. Immersion lenses should reach 45 nm easily and perhaps 35
nm. The radial polarization may not be necessary for 35 nm and make it
possible to reach 25 nm with ArF lasers.
Beyond that EUV will be needed, say in 2012. Prototype hardware exists,
but this will be another significant jump in fab costs. (EUV fabs will
process wafers in vaccuum, because air strongly attenuates EUV light.)
Will even half a dozen companies build EUV fabs? Or will some other new
technique be discovered to put EUV off further? Don't know. But about
then molecular electronics should be emerging as well, and it may bypass
lithography altogether.
--
Robert I. Eachus
"The terrorists rejoice in the killing of the innocent, and have
promised similar violence against Americans, against all free peoples,
and against any Muslims who reject their ideology of murder. Their
barbarism cannot be appeased, and their hatred cannot be satisfied.
There's only one way to deal with terror: We must confront the enemy and
stay on the offensive until these killers are defeated." -- George W. Bush
Robert V Hill
Diamond and other material advancement are the way to go. Reversible logic
will solve almost 0% of the heat problems in todays CPUs. Most heat build up
in CPU is leakage, not bit creation. Ideally we would want to build A CPU
with 0 leakage. Once we can do that and heat is still a problem then we will
have to move to Reversible logic.
"Gordon D. Pusch" <g_d_pusch_remo...@xnet.com> wrote in message
news:c7png...@enews1.newsguy.com...
>
> Uncle Al <Uncl...@hate.spam.net> writes:
>
> > The thermal density of future chips is appalling. We are staring down
> > 100+ watts in an area the size of a postage stamp. The damning volume
> > is the millimeter or two between the chip and its thermal sink.
> > You need a heat spreader (diamond; or Moissanite as less good, less
> > expensive fallback), a cold plate, and a way to get rid of all that
heat.
>
> As I've noted earlier, a =FAR= better solution is to simply start using
> reversible logic. The only computing operations that _have_ to generate
> heat are the I/O operations.
>
> Furthermore, even using CMOS logic, substantial opportunities for reducing
> the heat that is dissipated exist (for example, google on "hot-clock
seitz").
> An excellent set of lecture notes on reduced energy-dissipation computing
> may be found at:
<http://www.cs.caltech.edu/~cs181/97-98/181a/lectures/14.ps>.
Diamond and other matirol
Uncle Al
Robert V Hill wrote:
>
> Diamond and other material advancement are the way to go. Reversible logic
> will solve almost 0% of the heat problems in todays CPUs. Most heat build up
> in CPU is leakage, not bit creation. Ideally we would want to build A CPU
> with 0 leakage. Once we can do that and heat is still a problem then we will
> have to move to Reversible logic.
Nobody can make electrically usable n-doped diamond. Anyone who can
will have a key patent on the future. I'm a little surprised all the
folks looking at lithium, nitrogen, and phosphorus dopants have not
considered magnesium or titanium. One doe well to address the new
problem, not old solutions to other problems.
Biff Bubster
Uncle Al <Uncl...@hate.spam.net> wrote in message
news:<c8lvs...@enews3.newsguy.com>...
> Robert V Hill wrote:
> >
> > Diamond and other material advancement are the way to go. Reversible logic
> > will solve almost 0% of the heat problems in todays CPUs. Most heat build up
> > in CPU is leakage, not bit creation. Ideally we would want to build A CPU
> > with 0 leakage. Once we can do that and heat is still a problem then we will
> > have to move to Reversible logic.
>
> Nobody can make electrically usable n-doped diamond. Anyone who can
> will have a key patent on the future. I'm a little surprised all the
> folks looking at lithium, nitrogen, and phosphorus dopants have not
> considered magnesium or titanium. One doe well to address the new
> problem, not old solutions to other problems.
N-type diamond is a difficult problem and confuses a lot of people.
Here are the design requirements:
a) Must be a substitutional dopant.
b) Must be shallow.
The physics behind boron and nitrogen doping of diamond is that they
have NEGATIVE energies of incorporation into the diamond lattice. In
other words it is energetically favorable to replace a carbon atom
with a nitrogen or boron atom. The host lattice will not be strained.
In the past, various clowns have tried other materials and reported
their results in Applied Physics Letters Science etc. The problem is
that because these other atoms are in some sense larger than carbon
when inserted in the diamond lattice they have positive energies of
incorporation and thus either deform the host sites and/or are not
substitutional. When experimenters measure n-type behavior in diamond,
what they are seeing is n-type behavior of the defects created.
Usually, no mobility measurements are reported. Low mobilities usually
confirm this. One could introduce a dopant that engineers a high
mobility n-type defect but that is another story and almost an
oxymoron.
Finally in regards to magnesium and titanium, any potential dopant
needs some surface mobility during growth. Since Mg and Ti form
carbides, (Ti an especially strong one) I have a feeling above a
certain doping level that they will form inclusions similar to V in
SiC. If Mg and Ti don't fit in the diamond lattice and have zero
surface mobility during epitaxy all you will create IMHO is carbide
inclusions in the diamond
Uncle Al
Well put! Good research but not optimistic technology. Titanium's
multiple valence states and strong bonding to hydrogen suggest it is
rather more optimistic than you expect in a CVD (e.g., volatile
titanium alkyls, alkoxides, bulky acacs, or titanocene derivatives as
plasma dopants) or equivalent environment. Incorporation of titanium
hydride in short duration HPHT diamond synthesis (or annealing of
existing diamond in geodynamic conditions re Novatek in Utah) would be
an interesting experiment. Aluminum getter in the solvent alloy to
remove nitrogen - though titanium may do that as well.
Titanium can be a very small atom in an appropriate lattice electronic
environment. It's an unlikely n-dopant but not impossible.
The difference between true n-dopants for diamond and induced lattice
defects as n-dopant centers is a critical observation. The vast bulk
of n-doped diamond electronics literature is grandiloquent bombastic
ivory tower swill - all of it predicting a wonderful future of CPUs
cooking at 400 C and loving it. Dielectrics and wiring therein wll be
the subject of further studies.
1) Obtain sustrate.
2) Accelerated ion-bombard.
3) Thermally anneal.
4) Make measurements.
5) Publish.
If only the Periodic Table had more entries.
Fleetie
Biff Bubster
You have indirectly pointed out the one possibility to bipolar diamond
electronics. There was an APL paper demonstrating a true diamond PN
junction diode operating at around 500C. A p-type homoepi layer grown
on a Sumitomo nitrogen doped HPHT substate. At 500C, the temperature
is high enough to demonstrate donor behavior from the deep nitrogen
level.
Biff Bubster
You have indirectly alluded to the one way to make bipolar diamond
devices, high temperatures. If I recall correctly there was an APL
paper demonstrating a high temperature bipolar PN diode using an
p-type(boron) homoepi layer grown on an HPHT Sumitomo nitrogen doped
diamond substrate. The temperature of the device was +500C. The
results were decent, but at such high tempertures you run into another
problem which is carrier mobilities. At room temperature hole
mobilities are hugh, but no n-type substitutional dopant and at the
temperatures where nitrogen starts contributing electrons the mobility
drops.
Uncle Al
>
> Uncle Al <Uncl...@hate.spam.net> wrote in message
> news:<cafss...@enews4.newsguy.com>...
> > Biff Bubster wrote:
> > > Uncle Al <Uncl...@hate.spam.net> wrote in message
> > > news:<c8lvs...@enews3.newsguy.com>...
> > > > Robert V Hill wrote:
> > > N-type diamond is a difficult problem and confuses a lot of people.
> > >
> > > Here are the design requirements:
> > >
> > > a) Must be a substitutional dopant.
> > >
> > > b) Must be shallow.
> > >
> > > The physics behind boron and nitrogen doping of diamond is that they
> > > have NEGATIVE energies of incorporation into the diamond lattice. In
> > > other words it is energetically favorable to replace a carbon atom
> > > with a nitrogen or boron atom. The host lattice will not be strained.
> > > In the past, various clowns have tried other materials and reported
> > > their results in Applied Physics Letters Science etc. The problem is
> > > that because these other atoms are in some sense larger than carbon
> > > when inserted in the diamond lattice they have positive energies of
> > > incorporation and thus either deform the host sites and/or are not
> > > substitutional. When experimenters measure n-type behavior in diamond,
> > > what they are seeing is n-type behavior of the defects created.
> > > Usually, no mobility measurements are reported. Low mobilities usually
> > > confirm this. One could introduce a dopant that engineers a high
> > > mobility n-type defect but that is another story and almost an
> > > oxymoron.
[snip]
> > The difference between true n-dopants for diamond and induced lattice
> > defects as n-dopant centers is a critical observation. The vast bulk
> > of n-doped diamond electronics literature is grandiloquent bombastic
> > ivory tower swill - all of it predicting a wonderful future of CPUs
> > cooking at 400 C and loving it. Dielectrics and wiring therein wll be
> > the subject of further studies.
> >
> > 1) Obtain sustrate.
> > 2) Accelerated ion-bombard.
> > 3) Thermally anneal.
> > 4) Make measurements.
> > 5) Publish.
> >
> > If only the Periodic Table had more entries.
>
> You have indirectly alluded to the one way to make bipolar diamond
> devices, high temperatures. If I recall correctly there was an APL
> paper demonstrating a high temperature bipolar PN diode using an
> p-type(boron) homoepi layer grown on an HPHT Sumitomo nitrogen doped
> diamond substrate. The temperature of the device was +500C. The
> results were decent, but at such high tempertures you run into another
> problem which is carrier mobilities. At room temperature hole
> mobilities are hugh, but no n-type substitutional dopant and at the
> temperatures where nitrogen starts contributing electrons the mobility
> drops.
A hot chip has poor MTBF. Metallizations will fail, dopants will
diffuse, differing CTEs will break connections. New small
architecture chips use exotic low epsilon dielectrics instead of
straight SiO2 - fluorinated silica, porous silica, carbon-containing
silica (methyl groups; usually burned out after deposition). They
don't like high temps.
Diamond n-p junctions are demonstrated to work as expected. A usable
n-doped diamond is nowhere near reduction to practice. That suggests
everybody is doing it wrong - one cannot find a needle in a haystack
if it isn't in there. A chemist would then shout "umpolung!" and do
something different. All this work is being pursued by engineers who
will instead "optimize" the response surface. One would do better to
make it the topic of a high school science fair and get some original
thought plus a few goofs in there.
The whole of Zieglar-Natta polyolefin catalysis traces back to a dirty
autoclave. Nobody knows the name of the technican whose sloppy
technique obtained the now $trillion discovery. The discoveries of
saccharin and aspartame were contingent upon chemists accidentally
tasting their work being performed in other venues. In a properly
managed world they would have all been discharged for cause -
incompetence and insubordination - and the inventions rewarded to more
deserving folk adherent to Korporate Kulture.
Uncle Als says, "Discovery does not reside within a PERT chart."