Open inputs in TTL circuits
H. C. Bowman
Hello netters--
I need to put some diagnostic features into a project, and I need some
advice. If I have a TTL device (let's say a 74150 1 of 16 data selector)
and an input is left open, will that input look high or low? Is the
open condition sufficiently predictable that I can design without pull-up
resistors (not needed otherwise).
Next, if I use a 26LS32C differential receiver (I couldn't get the 26LS32AC)
I know that the output is undefined when the input is left open. What's
the most clever way to have a predictable output when this condition
occurs? Is there a better way than two pulling resistors?
Many thanks!
--Cliff
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| I'm pretty sure the world *isn't* fair... If it | (501) 968-2232 |
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CX...@psuvm.psu.edu
this behavior is consistent enough that pull-ups probably aren't necessary.
(In fact, the only TTL chips I've ever encountered whose inputs floated
low were duds.)
Christopher Webster (cx...@psuvm.psu.edu)
VLSI Laboratory
Penn State Harrisburg
Tom Biggs
>
>I need to put some diagnostic features into a project, and I need some
>advice. If I have a TTL device (let's say a 74150 1 of 16 data selector)
>and an input is left open, will that input look high or low? Is the
>open condition sufficiently predictable that I can design without pull-up
>resistors (not needed otherwise).
pick up noise from any nearby switching, so pull it up!
>
>Next, if I use a 26LS32C differential receiver (I couldn't get the 26LS32AC)
>I know that the output is undefined when the input is left open. What's
>the most clever way to have a predictable output when this condition
>occurs? Is there a better way than two pulling resistors?
>
Can't think of anything simple other than getting one of the parts where the output
goes high when the input is left open. I don't know the part numbers off hand,
but I know TI and Linear Technology have parts that do this.
SOH KAM YUNG
: Hello netters--
: I need to put some diagnostic features into a project, and I need some
: advice. If I have a TTL device (let's say a 74150 1 of 16 data selector)
: and an input is left open, will that input look high or low? Is the
: open condition sufficiently predictable that I can design without pull-up
: resistors (not needed otherwise).
: [stuff abt 26LS327C deleted...sorry, I never used it before]
In general, it is safest to tie all unused inputs to either Vcc
(possibly via a pull up resistor) or to ground.
DO NOT FLOAT IT!!! In most cases, the output may vary unpredictably
between 1 and 0.
Ex: I accidentally left the SET and RESET pins on a flip-flop
unconnected in a project and I wasted an hour trying to figure out
why the output was jumping between 1 and 0 before realising I forgot
about those @#$#$% pins.
Soh Kam Yung,
engp...@nusunix.nus.sg
j...@cmkrnl.com
Yep. Use a pull-up or pull-down resistor if you want to be able to easily
pull the input "the other way" for testing; otherwise you can tie direct to
Vcc or ground.
--- Jamie Hanrahan, Kernel Mode Systems, San Diego CA
Internet: j...@cmkrnl.com Uucp: uunet!cmkrnl!jeh CIS: 74140,2055
richard.b.dell
Except for noise immunity and current draw. A floating TTL input
is not 'pulled' as high as one with a pullup resistor, and contributes
more leakage current to the input transistor. This changes the thresholds
of the device, increases the quiescent current, etc.
An open input like this is a prime candidate for a high speed noise spike
to capacitively couple into it, causing the possibility of a glitch in your
circuit. It floats at (don't quite remmber) something like 2 volts or less,
and with a nominal TTL threshold of 1.3 volts, and the input being relatively
high impedance, the possibility of such a glitch is much higher than if it
was pulled high, and sitting at 5 volts.
Many inputs may be tied to one pullup resistor, so the added cost is small.
It is also good engineering practice, especially as one moves on to CMOS.
I used to frequently bail out a friend who was well versed in TTL, and used
to leaving inputs floating high, when he started moving to CMOS circuits.
He also had problems with his TTL circuits as he started using faster clocks,
leading to strongers glitches. Funny thing was ... he didn't find it
strange when he put small capacitors on outputs to filter out glitches
that shouldn't have been there in the first place.
Richard Dell
ken thompson
)A TTL input that's left unconnected behaves like a logic one (high), and
)this behavior is consistent enough that pull-ups probably aren't necessary.
)(In fact, the only TTL chips I've ever encountered whose inputs floated
)low were duds.)
FAST parts from Farchild and others are TTL and they float low.
Tie all unused inputs of all logic families to something, anything.
This avoids oscillations and decreased noise imunity.
--
Ken Thompson N0ITL Disk Array Hardware Development Peripheral Products Division NCR Corp. an AT&T company 3718 N. Rock Road Wichita,Ks 67226 (316) 636-8783 Ken.Th...@wichitaks.ncr.com
Mark Hydick
>>A TTL input that's left unconnected behaves like a logic one (high), and
>ktho...@donald.WichitaKS.NCR.COM writes:
>FAST parts from [Fairchild] and others are TTL and they float low.
>Tie all unused inputs of all logic families to something, anything.
>This avoids oscillations and decreased noise [immunity].
I'll concur with CX...@psuvm.psu.edu. including the bit about floating inputs
from some failed devices being other than approximately +1.9 Volts.
I have always seen floating TTL inputs interpreted as a logic high.
I have always used this feature when breadboarding all but the most
demanding circuits and have never had it fail me (bread boarding high speed
stuff would fail for reasons other than leaving a TTL input open).
If you read a data book from nearly any TTL logic family, including
FAST, and look at the input structure, it's obvious why this happens
(Hint: You need to sink CURRENT out of the input to achieve a logic low).
The above applies to LSTTL devices also although I believe the float
voltage is slightly different.
You do, as others mentioned, take a big hit in noise immunity by floating
inputs. But if they are "don't cares" like the parallel inputs to
a counter or shift register and you're never using the parallel load
function... who cares?
I can't recall which devices but there are some specialized functions
(must be either very specialized or obsolete devices 'cause I haven't
seen one in the last eight years) in which the input structure is
different than the typical TTL input.
Now that I think about the original posters question a bit more...
If he's wanting a reliable, professional design...
why doesn't he get in touch with the manufacturers of the proposed devices,
talk to their applications engineers, get (and READ) data books, etc, etc?
You know. RTFM (Unless you're one of the paranoid types who believes the
manufacturers goal in life is to trick you with all the data and design
rules contained therein and otherwise make your life difficult by making
their parts difficult to use.).
Sorry. Started to climb the soap box again. Sorry.
Now CMOS is another matter altogether. Don't float their inputs
unless you want to use it as an electrometer ;-) .
CX...@psuvm.psu.edu
are left unconnected, you are all quite correct. However, for diagnostic
purposes (like a static functionality check), pull-ups aren't required.
[Even so, there's at least 250mV of leeway between the voltage at which an
open S or LS TTL input sits (around 2V) and the linear portion of the
gate's transfer function, over the entire military temperature range.]
Once the circuit's DC operation is fully verified then, of course, tie all
unused inputs high or low as appropriate. But don't parallel several inputs
of a multi-input gate, as this only makes things worse for the gate that has
to drive them.
BTW, ktho...@donald.WichitaKS.NCR.COM writes:
> Fast parts from Farchild and others are TTL and they float low.
I don't believe that for one minute! I'll have to get some 74F, AS, and
ALS parts and test this...
Josef Moellers
>In article <1993May22.0...@nuscc.nus.sg>, engp...@nusunix1.nus.sg (SOH KAM YUNG) writes:
>> H. C. Bowman (h...@netcom.com) wrote:
>> : I need to put some diagnostic features into a project, and I need some
>> : advice. If I have a TTL device (let's say a 74150 1 of 16 data selector)
>> : and an input is left open, will that input look high or low? Is the
>> : open condition sufficiently predictable that I can design without pull-up
>> : resistors (not needed otherwise).
>> : [stuff abt 26LS327C deleted...sorry, I never used it before]
[ ... ]
>Yep. Use a pull-up or pull-down resistor if you want to be able to easily
>pull the input "the other way" for testing; otherwise you can tie direct to
>Vcc or ground.
I was told long ago that inputs are more sensitive to over-voltage than
the chip itself. Therefore, if You tied any input to Vcc and Your Vcc
varied a little, the chip might get ddamaged even if the specified range
is not exceeded. Therefore: Always use a pull-up. You can share one with
several inputs, though.
--
| Josef Moellers | c/o Siemens Nixdorf Informationssysteme AG |
| USA: molle...@sni-usa.com | Abt. STO-XS 113 | Riemekestrasse |
| !USA: molle...@sni.de | Phone: (+49) 5251 835124 | D-4790 Paderborn |
Tom Gardner
|inputs. But if they are "don't cares" like the parallel inputs to
|a counter or shift register and you're never using the parallel load
|function... who cares?
One second order effect you can get is that a floating input can "think" it
is high, low, high, low etc, whether due to a true oscillation or just due
to noise pickup. These changes can alter the state of internal nodes and hence,
even if the "noisy" inputs does not propagate to the outputs, they can still
caused increased power consumption and can act as a _generator_ of noise.
Best to tie all logic inputs to a valid logic level, unless the device data
sheet says this is not required.
greg deuerling
>Standard practice has been to pullup or pulldown unused inputs to power or
>ground. Most databooks explicity recommend *against* leaving inputs floating
>to maximize switching speed and noise immunity as many of you have pointed
>out already.
>
>There are secondary benefits in pulling unused inputs high or low instead
>of tying them directly to power or ground. The main one is testability.
>Many mfrs use automatic test equipment on their boards. These machines
>basically force a current/voltage on various nodes on the boards under
>test. If a pin is tied directly to power or ground, there is no way
>that node can ever be toggled, and the logic downstream will most likely
>be precluded from any possibility of being exercised.
>
>A pullup/pulldown resistor is not only good engineering practice, but
>also a cheap means of guaranteeing reliable functionality in the long
>term.
I think most chip manufactures recommend that you pull a signal line high
or low with a spare gate of the logic family you are using. They also do
not reccomend that you tie a pin directly to +5. In some families this
can shorten the life of the part. In fact I have seen 74S74's die in the
matter of weeks by doing this. If I remember right, LS is the only TTL
family that this does not affect.
Kinda goes to show you that even some of the most simplist things can
really give you nightmares.
gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
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= P.O.Box 500 MS#368 Batavia, Il 60510 1(708)840-4629 =
= Computer R&D Group =
= g...@fncrd6.fnal.gov =
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Aaron Lung
Standard practice has been to pullup or pulldown unused inputs to power or
ground. Most databooks explicity recommend *against* leaving inputs floating
to maximize switching speed and noise immunity as many of you have pointed
out already.
There are secondary benefits in pulling unused inputs high or low instead
of tying them directly to power or ground. The main one is testability.
Many mfrs use automatic test equipment on their boards. These machines
basically force a current/voltage on various nodes on the boards under
test. If a pin is tied directly to power or ground, there is no way
that node can ever be toggled, and the logic downstream will most likely
be precluded from any possibility of being exercised.
A pullup/pulldown resistor is not only good engineering practice, but
also a cheap means of guaranteeing reliable functionality in the long
term.
aaron
Dave Horsfall
h...@netcom.com (H. C. Bowman) writes:
| If I have a TTL device (let's say a 74150 1 of 16 data selector)
| and an input is left open, will that input look high or low? Is the
| open condition sufficiently predictable that I can design without pull-up
| resistors (not needed otherwise).
As I recall from my ancient history lessons :-), TTL inputs are open
emitters of NPN transistors with the bases tied high, thus will float
high (minus a PN drop).
--
Dave Horsfall (VK2KFU) VK2KFU @ VK2RWI.NSW.AUS.OC PGP 2.2
da...@esi.COM.AU ...munnari!esi.COM.AU!dave available
Henry Spencer
>I think most chip manufactures recommend that you pull a signal line high
>or low with a spare gate of the logic family you are using. They also do
>not reccomend that you tie a pin directly to +5. In some families this
>can shorten the life of the part. In fact I have seen 74S74's die in the
>matter of weeks by doing this. If I remember right, LS is the only TTL
>family that this does not affect.
Hmm, the National 74F databook (the first TTL databook with a "Design
Considerations" section that came to hand on my shelf) explicitly states
that unused inputs may be tied directly to ground or Vcc. The Philips
(aka Signetics) FAST book agrees. A slightly old TI ALS/AS databook also
agrees, with the proviso that you make sure Vcc never ever exceeds 5.5V.
(All, incidentally, state firmly that you should never let them float.)
--
SVR4 resembles a high-speed collision | Henry Spencer @ U of Toronto Zoology
between SVR3 and SunOS. - Dick Dunn | he...@zoo.toronto.edu utzoo!henry
Henry Spencer
>> Fast parts from Farchild and others are TTL and they float low.
>
>I don't believe that for one minute! I'll have to get some 74F, AS, and
>ALS parts and test this...
The Philips 74F databook specifically states that parts with NPN inputs
float low.
A Myles
: Hmm, the National 74F databook (the first TTL databook with a "Design
: Considerations" section that came to hand on my shelf) explicitly states
: that unused inputs may be tied directly to ground or Vcc. The Philips
: (aka Signetics) FAST book agrees. A slightly old TI ALS/AS databook also
: agrees, with the proviso that you make sure Vcc never ever exceeds 5.5V.
: (All, incidentally, state firmly that you should never let them float.)
: --
: SVR4 resembles a high-speed collision | Henry Spencer @ U of Toronto Zoology
: between SVR3 and SunOS. - Dick Dunn | he...@zoo.toronto.edu utzoo!henry
I've never actually seen why in a data book, but does anyone know why
you need a 1K or so resistor when tying unused i/ps to Vcc or risk damage?
The only reason I can think of is that the i/p -ve overvoltage protection
diodes might break down at 5.5V _if_ they use the eb diffusions to make the
diodes and fuse/crater the junction if the current is not limited. I can
see that this would result in smaller diode geometries and reduced
leakage to ground. Don't know about Schottky breakdown in LS/S though...
More sinister, but less likely(?), is that if the eb junctions break
at about 3.4V (negelecting back Vceo which could then be even less...)
you would have a very low resistance path through the i/p device
phase-splitter and totem-pole sink to ground.
Has anyone measured this or does anyone who works on a TTL 'fab know?
I would finally like to know the raison-d'etre for this common "rule of
thumb" with TTL
Thanks.
Andy.
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Integrated Systems Group (the boys to entertain yoooou) (Caledonia)031 650 5665
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CX...@psuvm.psu.edu
> The Philips 74F databook specifically states that parts with NPN inputs
> float low.
Well, there are 3 varieties of NPN input used in 74F logic, two of
which are quasi-differential and are capable of floating *either* high or
low. However, these inputs are used only in a few parts where a moderately
high input impedance is needed. All of the most commonly used 74F, AS, and
ALS parts float high; this is obvious from their schematics, and I've since
verified this in the lab.
Cary Mednick
>you need a 1K or so resistor when tying unused i/ps to Vcc or risk damage?
>
max spec of LS is +7Vdc, but the max input voltage is only 5.5Vdc. The
resistor allows the chip to survive a power transient up to 7.0 volts with
out destroying the input (if the input was tied directly to VCC). The
current drop accross the resistor ensures that the input stays below
5.5Vdc.
I seem to remember that the earlier TTL has Vinmax = Vccmax. LS changed
this spec. Newer families such as F logic again allow Vinmax = VCCmax.
--
-------------------
Cary Mednick c...@chinet.chinet.com
-------------------
Tom Barrett
>I've never actually seen why in a data book, but does anyone know why
>you need a 1K or so resistor when tying unused i/ps to Vcc or risk damage?
Even with a well-regulated power supply, the reason why most people
use pull-ups and pull-downs is for testability. For example, if a
F244 is to be enabled all the time, then instead of grounding the
enables pull them low with a resistor (low enough to give a good VIL,
but high enough to be overdriven by a board tester), or better yet use
a free inverting gate or buffer which has its input pulled high with a
high value resistor.
With internal gates on gate arrays, old technology sometimes could not
provide good VCC isolation and some vendors did not allow direct
connect of a gate's inputs to VCC (you have to use a tie-off cell or
an inverter whose input was grounded).
I'm not familiar with the processes, so I can't answer your question
about the damage.
Tom
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|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX 78741 |f:512-462-5155 |
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Nico Garcia
ajmy@festival (A Myles) writes:
> X-Newsreader: TIN [version 1.1 PL8]
> I've never actually seen why in a data book, but does anyone know why
> you need a 1K or so resistor when tying unused i/ps to Vcc or risk damage?
Because you may get power supply spikes, and they could toast your circuit.
Also, when testing the circuit, you can ground the pin and not damage it
with this, even if you only ground it accidentally.
--
Nico Garcia
CIRL/MEEI
eddie.mit.edu!eplunix!raoul
A Myles
: In article <36...@castle.ed.ac.uk>,
Yes, but what I want to know is _why_. For example, the TI TTL data book
says that LS inputs pulled high (which is the sensible thing to do since
you will save supply current by pulling them high) MUST have this to prevent
damage when the rail kicks, but not if the i/p is grounded. (testability issue
aside)
I speculated on a few possible failure mechanisms (via breakdown),
but would like to know just what sort of damage does occur (e.g. does it
blow the i/p diodes just making the gate i/p suck vast current high, or does
it go i/p to o/p -see last post- and trash the gate totally).
richard.b.dell
In linear applications, I have read of cautions about turn on transients
and the momentary breakdown of the reverse biased junctions leading to
a higher noise factor for the device. Not sure of the mechanism, possiblly
increased leakage or some such. But .. given the small size of junctions,
and given that even bipolar junctions can be blown by static charges,
I have always assumed that turn on transients .. along with internal
capacitances and board level capacitances .. can cause reverse bias across
the junctions, which would need to be limited in magnitude to prevent
damage.
Richard Dell
Mark Zenier
: Yes, but what I want to know is _why_. For example, the TI TTL data book
: says that LS inputs pulled high (which is the sensible thing to do since
: you will save supply current by pulling them high) MUST have this to prevent
: damage when the rail kicks, but not if the i/p is grounded. (testability issue
: aside)
:
: I speculated on a few possible failure mechanisms (via breakdown),
: but would like to know just what sort of damage does occur (e.g. does it
: blow the i/p diodes just making the gate i/p suck vast current high, or does
: it go i/p to o/p -see last post- and trash the gate totally).
According to James Buchanan in "CMOS/TTL Digital Systems Design",
when you put too high a voltage into a multi-emitter input like on the
old 7400 series gates, it isn't an emitter anymore. Due to the
relative voltages inside the input transistor the connection acts
like a collector. With no means to limit the load.
Mark Zenier ma...@ssc.wa.com ma...@ssc.com
A Myles
>According to James Buchanan in "CMOS/TTL Digital Systems Design",
>when you put too high a voltage into a multi-emitter input like on the
>old 7400 series gates, it isn't an emitter anymore. Due to the
>relative voltages inside the input transistor the connection acts
>like a collector. With no means to limit the load.
>Mark Zenier ma...@ssc.wa.com ma...@ssc.com
Yes, this similar to what I was thinking about, just before the onset of
breakdown. I've since found a data sheet (Mullard) which says that the
Vebo(LS) or Vceo of the transistor is low enough for nice lightining bolts to
zip through the gate (for multi-emitter i/ps) like I thought just above 5V.
Thanx
Andy
John Whitmore
>I've never actually seen why in a data book, but does anyone know why
>you need a 1K or so resistor when tying unused i/ps to Vcc or risk damage?
The absolute-max voltage allowed on Vcc is 7V; the absolute-max
voltage allowed on inputs is 5.5V.
It is possible for 74nn series gates that pass all tests
to bias the input transistors (not the clamp diodes, nor the
Schottky diodes on LS and other series) into base/emitter breakdown,
and in the absence of current limiting resistors, to damage the
gates during a power-on transient. It survives 7V transients,
with the resistor in place. It doesn't survive them, with
the inputs strapped to Vcc.
John Whitmore
Dave Mclaughlin
>Yep. Use a pull-up or pull-down resistor if you want to be able to easily
>pull the input "the other way" for testing; otherwise you can tie direct to
>Vcc or ground.
I normally tie to the point to a supply that ensures the device is not in
the switched state. ie. a 74LS00 I tie unused to gnd. This ensures the
transistor internaly is not switched on and therefore no current is used by
the unused gate.
--
Dave Mclaughlin
Dave Thomas
>I normally tie to the point to a supply that ensures the device is not in
>the switched state. ie. a 74LS00 I tie unused to gnd. This ensures the
>transistor internaly is not switched on and therefore no current is used by
>the unused gate.
The definitive snobs of electronics (and I mean that in a good way!),
Horowitz and Hill, authors of The Art Of Electronics, have this to
say. (I'll paraphrase).
If you want to force an unused TTL input low, it is perfectly okay to
ground it. If you want to force it high, though, it's slightly safer
(for the well being of the device) to use a pull-up resistor. The reason
is that the power supply pins can tolerate more overvoltage than the
input pins can, so just in case there's a glitch in the power supply
and the voltage increases briefly (say to 5.5V), you're covered.
They recommend that you tie all unused inputs that are to be forced high
to each other, and then pull them all up with one resistor.
For CMOS, there's no such danger. You can freely tie any input to either
power supply rail. And of course no one needs to be reminded that it's
very bad to leave a CMOS input unconnected.
David