CMOS gates in parallel?
Erland Unruh
in parallel.
The question is: is it safe to connect the outputs together directly,
or should I put a restor on each first and connect them instead? Does
it increase noise or anything?
Thanks!
Erland Unruh
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Telia Research
Box 85, 201 20 Malmo, Sweden
e...@malmo.trab.se
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Jeff Cunningham
Erland...@malmo.trab.se (Erland Unruh) writes:
> To increase drive capacity I'm going to use several gates of a 74AC14
> in parallel.
>
> The question is: is it safe to connect the outputs together directly,
> or should I put a restor on each first and connect them instead? Does
> it increase noise or anything?
If you need reliable operation I would not suggest doing this. Even
gates within the same package can have significantly different prop
delays which will cause current spikes between power and ground. This
can increase noise on the power bus and reduce the life of the gates.
Regarding connecting the outputs together through resistors, I would
think that values large enough to limit current during transitions
would really take away from your higher drive. I'd use something with
beefyer drive, or a transistor or two.
-Jeff.
Richard Steven Walz
With any other CMOS I'd say ok, but the '14 is a hex schmitt trigger, and
the hysteritic differences might make a bunch of false rising and falling
edges at different levels due to variations in the die's!!! You might want
to look at their output under your max load, but you might have to factory
select them too, for closeness to each other! On the same chip, just see if
a scope says it's ok at your desired load! There is no predeliction for CMOS
to complain like bipolar technology would do! I don't think they would be
subject to parasitic oscillation like this, but trying it is quicker than
asking for a cheap part!!! But it might go "hysterical" on you!!!;->
-Steve Walz rst...@armory.com
James C. Bach
In article <1994Aug30.1...@malmo.trab.se>, Erland...@malmo.trab.se (Erland Unruh) writes:
> To increase drive capacity I'm going to use several gates of a 74AC14
> in parallel.
>
> The question is: is it safe to connect the outputs together directly,
> or should I put a restor on each first and connect them instead? Does
> it increase noise or anything?
I've done it before . . . works OK. If you think about it, the "model"
(or "equivalent circuit" to some) of an CMOS output is a pair of switches and
a pair of resistors; one SW and R to Vcc, and another SW and R to Gnd. In the
"1" state the hi-side switch is closed, the low-side open; a "0" is low-side
closed and hi-side open. So "paralleling" them simply puts the resistors
(representing the Rds(on) of the FETs) in parallel.
ONE PROBLEM to be weary of . . . only do this for outputs from the same package;
the propagation delay times and rise/fall times of 2 different packages might
be different enough to cause the hi-side of some outputs to be "on" at the same
time as the low-side of some other outputs (during switching)! Pffffft!
Mika Iisakkila
>the propagation delay times and rise/fall times of 2 different packages might
>be different enough to cause the hi-side of some outputs to be "on" at the same
>time as the low-side of some other outputs (during switching)! Pffffft!
Well it's not that dramatic - most CMOS gates will survive seconds of
output contention, or shorts to either supply. But it's a situation to
be avoided anyway, as having several outputs fighting each other for
tens of nanoseconds during every transition will increase the supply
current and the resulting output waveform may become rather interesting.
--
Segmented Memory Helps Structure Software
Faisal Karmali
I worked on a project a while ago when I had a few of the same cmos chip
outputs in parallel. I found that one chip worked well; two chips built
up some capacitance so it took longer for the final state to be achieved;
three caused signals to be inputted incorrectly.
A solution is to use diodes so signals do not leak backwards.
Faisal Karmali @ Strathcona Composite High School! /////\\
Edmonton, Alberta, Canada: City of Champions o o Smile!!!
Home of the Edmonton Oilers \_____/
Raymond Leung
In article 79...@ahhchoo.ersys.edmonton.ab.ca, fkar...@ahhchoo.ersys.edmonton.ab.ca (Faisal Karmali) writes:
> I worked on a project a while ago when I had a few of the same cmos chip
> outputs in parallel. I found that one chip worked well; two chips built
> up some capacitance so it took longer for the final state to be achieved;
> three caused signals to be inputted incorrectly.
>
> A solution is to use diodes so signals do not leak backwards.
>
Since we usually use CMOS gates to drive a capacitive load, you have
to charge and discharge the output node alternatively. I wonder a diode in
series with the output would make sense.
By the way, the longer delay at the output of two gates I think would majorly
be contributed by the degrading of the chargine/discharging capabilities of
the gates by the transient short circuit current in between the two gates.
A couple of additional pf would not be a problem when joining the driving
capabilities of two gates.