interfacing CMOS with TTL
Jim Washer
I have a CMOS chip that provides parallel output. I want to interface this
to a ttl circuit. Can I use the CMOS output directly into a TTL buffer, or do
I need something else in between.
Mail answers directly as I'm sure MOST readers of this newsgroup already know
the answer.
Thanks
- jim washer (503) 578-3171 was...@sequent.com
Dave Medin
|> Simple question from a simple minded person...
|> I have a CMOS chip that provides parallel output. I want to interface this
|> to a ttl circuit. Can I use the CMOS output directly into a TTL buffer, or do
|> I need something else in between.
|>
|> Mail answers directly as I'm sure MOST readers of this newsgroup already know
|> the answer.
It isn't a silly question at all, and even experienced engineers have
problems in CMOS/TTL interfacing. How to do it begs for a look at the
summary of parameters involved:
CMOS outputs, in general, provide output swings to near the supply
rails. But, for generic CMOS (there are specialized CMOS parts
that escape this generalization), the output drive current in or out is small
by design to minimize the current spike drawn when the complementary
transistors driving the output change state. The low current is usually not a
problem in an all-CMOS system, as CMOS inputs being driven by the output
are high-impedance.
TTL inputs require heavy (relative) currents to be sunk to hold them in a low
state, with pullup to a high state not being much of a problem for CMOS. The
size of the current required usually depends on the technology used in
the logic family. In order, some common examples from most to least
current required are: 74Hxx, 74Sxx, 74xx, 74Lxx, 74LSxx. To register
a logic low, the input must be pulled lower than 0.7 volts. A CMOS
gate (an example in the CD4000 series) can usually do this reliably
providing it is only driving ONE TTL input and the TTL is of the 74xx
or 74LSxx family-type. The "HC" and "HCT" CMOS families becoming more prevalent
in the hobby market have higher output currents and can usually drive
several TTL gates low. Further, the "HCT" family has enhanced "low"
drive for this purpose. If you have multiple uncommitted CMOS gates, they
can be tied in parallel for increased drive current to TTL. ONLY USE
PARALLEL GATES, NOT DIFFERENT POINTS IN THE CIRCUIT WHICH MAY CHANGE
STATE AT THE SAME TIME. Otherwise, small delays between gate outputs
may lead to heavy currents flowing in the circuit.
TTL driving CMOS typically suffers on pullup, as a TTL gate may only
pull the voltage up to near or slightly over the level a CMOS gate
sees as a logic "high." Being slightly over is not good enough, as
a tiny amount of noise added to the input will cause the gate
to change state--this amount is called "noise margin." So, in general, a
pullup resistor to Vcc is used--usually 2.2K is good. The "HCT" CMOS
family will accommodate most TTL outputs directly with a fair
noise margin, as the logic threshhold is designed to be lower
in these parts. The "HCT" output then would drive successive stages
of the pure CMOS circuitry.
Note that none of the above hints hold when the TTL and CMOS
are run from different supply voltages!
A good discussion of logic levels and peculiarities can be found
in the classic text, "The Art of Electronics" by Horowitz and Hill,
mentioned by many readers of this group.
Hope this helps.
--
------------------------------------------------------------------------
Dave Medin Voice: (205) 730-5812
Intergraph Corp. (205) 837-1174
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*********Everywhere You Look...(at least around my office)***********
*The opinions here are strictly my own (or those of my machine)
Gerard Pinzone
In a previous article, was...@sequent.com (Jim Washer) says:
>Simple question from a simple minded person...
>I have a CMOS chip that provides parallel output. I want to interface this
>to a ttl circuit. Can I use the CMOS output directly into a TTL buffer, or do
>I need something else in between.
>
You just put a 1K ohm resistor between the output of the CMOS gate / input
of the TTL gate and ground.
For TTL to CMOS, you put it from Vcc (+5 volts that is!) instead of ground
--
_______ ________ ________ "Small nose, loose girls, no nipples, (.|.)
/ ___/ / _____/ / __ / Iczer curls!" -=- Gerard Pinzone ).(
/ ___/ / /____ / __ / gpin...@george.poly.edu ( v )
/______/ /_______/ /__/ /__/ Join the ECA Wehrmacht! Kill CM! \|/
Dave Medin
|>
|> In a previous article, was...@sequent.com (Jim Washer) says:
|>
|> >Simple question from a simple minded person...
|> >I have a CMOS chip that provides parallel output. I want to interface this
|> >to a ttl circuit. Can I use the CMOS output directly into a TTL buffer, or do
|> >I need something else in between.
|> >
|> You just put a 1K ohm resistor between the output of the CMOS gate / input
|> of the TTL gate and ground.
The above is not reliable for the CD4000 CMOS series... The CMOS gate
may have problems pulling up far enough against the 1 K resistor to trigger
some TTL gates' high state...
Mika R Iisakkila
>several TTL gates low. Further, the "HCT" family has enhanced "low"
>drive for this purpose. If you have multiple uncommitted CMOS gates, they
Minor nit: the HCT family is specifically designed to be driven by TTL
outputs. The output levels are the same in HC and HCT, but the
required input H level is lower in HCT (minimum 3.15V vs 2V). Normally
you would need a pullup resistor to connect TTL to HCMOS, but HCT
doesn't need this. A plain HC can directly drive a TTL input with no
problem (with a fan-out of two, because the HC(T) output L level is
only valid for sink currents less than 4mA).
All this and much more can be found in High-Speed CMOS Logic data book
by Texas Instruments - I've always found the TI data books to be of
great value because they usually have an elaborate section on theory
as well as on practical applications.
David J. Ratliff
I have a question concerning a Chips and Technologies NEAT 20 MHz 286
machine. I am currently trying to configure 8 Megs to the machine for misc
applications. They are all on the Main Board. The tech-ref and regular
(vague) manual say that it is possible. But when I set the jumpers, I get no
display on the monitor, no boot-up response and a series of beeps. My
conclusions are as follows:
1.) It is a power supply problem (I only have 200W)
2.) The system can't recognize the 4-bank active setting
3.) There is a incompatibility problem with DRAMS and SIPPS
My system is set up like this. I have 2 Hard Drives (10M MFM, 85M SCSI). 2
Floppys (1.44M, 1.2M), Super Vga, 4 Serial, 1 Parallel and a game port. My
system is taxed for power so I can see a problem with that. I have a
supposive 4 bank memory configuration option. 4 megs of SIPPS and 4 Megs of
DRAMS. Both are 80ns. I also have a Math Co-Processor, but I assume that
doesn't have much to do with my problem. What I'd like to know is if there
is a hardware-hack, BIOS replacement, or software utility that will do the
trick. The technical support for C&T is debateable. I have called them and
they say it can't be done. But the support isn't from C&T, some other
company. So I am frustrated. I got the 4 Meg cheap, so it's not a loss.
Both types work well independently. But if this doesn't work, is there a way
to trade SIPPS in for SIMMS? If you have info on any of my questions I would
be grateful for a response. Either E-Mail me, or reply via news. I don't
get a lot of time to read news because I am a student, but I need to solve
this problem. Thank you, in advance.
\ -----------------------|--|
\ David J. Ratliff | |
==============================================- drat...@ub.d.umn.edu | |
/ drat...@cpe.d.umn.edu | |
/ -----------------------|--|
Dave Medin
|> gme...@catbyte.b11.ingr.com (Dave Medin) writes:
|>
|> >several TTL gates low. Further, the "HCT" family has enhanced "low"
|> >drive for this purpose. If you have multiple uncommitted CMOS gates, they
|>
|> Minor nit: the HCT family is specifically designed to be driven by TTL
|> outputs. The output levels are the same in HC and HCT, but the
|> required input H level is lower in HCT (minimum 3.15V vs 2V). Normally
|> you would need a pullup resistor to connect TTL to HCMOS, but HCT
|> doesn't need this. A plain HC can directly drive a TTL input with no
|> problem (with a fan-out of two, because the HC(T) output L level is
|> only valid for sink currents less than 4mA).
Another minor nit: Check your databook again. You'll find that the current
sink vs. voltage ability of HCT parts is enhanced over their HC brethren. The
National Logic Databook explains why... However, that is not HCT's major
advantage but rather the lower input thresholds which both you and I mentioned.
That's why I said "Further."
|> All this and much more can be found in High-Speed CMOS Logic data book
|> by Texas Instruments - I've always found the TI data books to be of
|> great value because they usually have an elaborate section on theory
|> as well as on practical applications.
Yes. I still have the TI 1979 hardbound version around, too, for the same reason.
I find the National ap-notes in their TTL, HC, and linear to be superior to
those found elsewhere, though.