CD4060 calculating oscillator circuit.
Sotiris Antoniou
I know the 4060 is a counter / divider and oscillator. How can I calculate
the resistor and capacitor for the oscillator to make it work so I can have
30 sec - 60 sec output at one of the pins.
Thanks.
Sotiris Antoniou .
sam...@ath.forthnet.gr
Tony Williams
Sotiris Antoniou <sam...@ath.forthnet.gr> wrote:
> Hi,
> I know the 4060 is a counter / divider and oscillator.
> How can I calculate the resistor and capacitor for the
> oscillator to make it work so I can have 30 sec - 60 sec
> output at one of the pins.
Very roughly; Cx= 0.01uF, Rs= 680K, Rx= 69K.
I think that should run the clock at about
365Hz, and 365Hz/16384 = 0.022Hz.
Fiddle with Cx if I'm wrong.
--
Tony Williams.
py...@my-deja.com
"Sotiris Antoniou" <sam...@ath.forthnet.gr> wrote:
> Hi,
> I know the 4060 is a counter / divider and oscillator. How can I
calculate
> the resistor and capacitor for the oscillator to make it work so I can
have
> 30 sec - 60 sec output at one of the pins.
For this circuit, commonly used with 4060:
|\ |\
----| O-------| O------o OUT
| |/ | |/ |
| | | ---
| | |R --- C
| ___ | |
----|___|-------------
Rs
C is connected between pin 9 and a circuit node.
R is connected from this node to the pin 10.
Rs, if present, is connected between that node and pin 11. If
inexistent, Rs must be replaced by a short circuit.
The period is given by:
T = -RC{ln[Vtr/(VDD+Vtr)] + ln[(VDD-Vtr)/(2VDD-Vtr)]}
Where Vtr is the transfer voltage (the gate input voltage that switches
the gate), VDD is the supply voltage and Rs is only necessary for
getting a frequency almost VDD independent. If this is not important for
you, take it out. If present, Rs must be >> 2R.
I'm sorry if the diagram is not displayed correctly.
--
Greetings,
Luiz - PY1LL
Sent via Deja.com http://www.deja.com/
Before you buy.
Mark Zenier
Sotiris Antoniou <sam...@ath.forthnet.gr> wrote:
>Hi,
>I know the 4060 is a counter / divider and oscillator. How can I calculate
>the resistor and capacitor for the oscillator to make it work so I can have
>30 sec - 60 sec output at one of the pins.
It's in the datasheet. See the schematic in there for the configuration.
For the MC14060B, the Motorola CD4060 equivalent, they have
Fosc = 1/(2.3 * Rtc * Ctc) (Rtc in Ohms, Ctc in Farads)
For the MC74HC4060, the High Speed CMOS version, they have
Fosc = 1/(3 * Rtc * Ctc) (Rtc in Ohms, Ctc in Farads)
At the last stage of the divider chain, you want 16384/60 Hz, or 273 Hz.
Mark Zenier mze...@eskimo.com mze...@netcom.com Washington State resident
De Guerin
32768 Hz crystal ... :-)
Andre
E-mail returned to sender -- insufficient voltage.
Backup not found: (A)bort (R)etry (P)anic
Mike W
>
>For this circuit, commonly used with 4060:
>
>
> |\ |\
> ----| O-------| O------o OUT
> | |/ | |/ |
> | | | ---
> | | |R --- C
> | ___ | |
> ----|___|-------------
> Rs
>
>C is connected between pin 9 and a circuit node.
>R is connected from this node to the pin 10.
>Rs, if present, is connected between that node and pin 11. If
>inexistent, Rs must be replaced by a short circuit.
>
>The period is given by:
>
>T = -RC{ln[Vtr/(VDD+Vtr)] + ln[(VDD-Vtr)/(2VDD-Vtr)]}
>
Luiz, can this be simplified for "rule of thumb" values?.
John Popelish
|\ |\
----| O-------| O------o OUT
| |/ | |/ |
| | | ---
| | ____ |
--------------|____----
.25R
I like this alternate version, because it does not drive the input
voltage beyond the supply rails. The period is about .6*RC (I think).
It also loads the output less than the other version.
--
John Popelish
py...@my-deja.com
mi...@corn2.freeserve.co.uk wrote:
> On Thu, 30 Mar 2000 22:10:15 GMT, py...@my-deja.com wrote:
>
> >
> >For this circuit, commonly used with 4060:
> >
> >
> > |\ |\
> > | |/ | |/ |
> > | | | ---
> > | ___ | |
> > ----|___|-------------
> > Rs
> >
> >C is connected between pin 9 and a circuit node.
> >R is connected from this node to the pin 10.
> >Rs, if present, is connected between that node and pin 11. If
> >inexistent, Rs must be replaced by a short circuit.
> >
> >The period is given by:
> >
> >T = -RC{ln[Vtr/(VDD+Vtr)] + ln[(VDD-Vtr)/(2VDD-Vtr)]}
> >
>
> Luiz, can this be simplified for "rule of thumb" values?.
>
>
The drawing MUST be rebuilt he he ....
Well, this is not a complicated formula. It takes into account many
things like Vtr that can be easily measured. A simple pocket calculator
does the job easily. The results are rather precise but, when one
doesn't need precision, he can consider Vtr = VDD/2 and the formula
becomes:
T = 2.2 RC
py...@my-deja.com
4060 itself works very fine with common 32768 Hz crystals. The only care
we have to take is to not to overload tha crystal because it can be
easily broken.
Mike Mccarty Sr
John Popelish <jpop...@rica.net> wrote:
)
) |\ |\
) ----| O-------| O------o OUT
) | |/ | |/ |
) | | | ---
) | | |.75R --- C
) | | ____ |
) --------------|____----
) .25R
)I like this alternate version, because it does not drive the input
)voltage beyond the supply rails. The period is about .6*RC (I think).
)It also loads the output less than the other version.
If it is close to 0.6*RC, I bet it is ln 2 * RC.
--
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel <- They make me say that.
John Popelish
>
> In article <38E5770E...@rica.net>,
> John Popelish <jpop...@rica.net> wrote:
> )
> ) |\ |\
> ) ----| O-------| O------o OUT
> ) | |/ | |/ |
> ) | | | ---
> ) | | |.75R --- C
> ) | | ____ |
> ) --------------|____----
> ) .25R
> )I like this alternate version, because it does not drive the input
> )voltage beyond the supply rails. The period is about .6*RC (I think).
> )It also loads the output less than the other version.
>
> If it is close to 0.6*RC, I bet it is ln 2 * RC.
Damn. Now I have to go back and figure out how I got that rule of
thumb.
)-;
Assuming that the threshold voltage is precisely at 1/2 of the supply
voltage (lets call the supply one unit of voltage for simplicity), and
that each time the divider tap voltage reaches the threshold (1/2)
from the positive side , the cap must be just reaching (4/3)*(1/2)=2/3
by the values of the divider.
At that moment, both sides of the cap experience -1 unit of voltage
swing, so the voltage on the resistor side of the cap goes to 2/3 - 1=
-1/3. At the same time, the middle output swings to 1 and so the tap
voltage is 3/4 of 1+(1/3) more negative than 1 = 0. That is, the
divider has 1 at the top and -1/3 at the bottom, so 0 at the tap.
This is where the elimination of voltage swings outside of the supply
range comes in that allows me to neglect any conduction current
through the input clamping network on the left input.
The astable will stay in this state until the tap voltage reaches
threshold (1/2 from the negative side) while the cap charges from -1/3
to +1/3 (on the way to 1). This is 2/3 out of a total possible swing
of 4/3 (if the astable never changed state) or *** 1/2 *** of the
starting charge voltage.
(At this point, the right output goes through a +1 transition, while
the middle output goes to 0, and the next half cycle begins as the cap
starts to discharge from +4/3 to 2/3.)
From the exponential RC time constant relationship between voltage and
time: fraction remaining of initial charge voltage = e^(-t/(R*C))
1/2=e^(-t/(R*C))
Taking the natural log of both sides to eliminate the exponential
term:
ln(1/2)=-t/(R*C)
Solving for t:
t=-ln(1/2)*R*C
This is the time of one half a cycle, so the total period of both half
cycles is:
Cycle Period=-2*ln(1/2)*R*C= 1.38*R*C
Oh well, I was only off by a little more than a factor of 2.
Did I screw it up the first time (on the back of some envelop) or this
time?
--
John Popelish