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When to use pull-ups on unused inputs ???

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Stuart Adams - Sun Microsystems Labs BOS

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Jan 20, 1994, 9:26:00 AM1/20/94
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When do you have to use pull-ups to tie a pin "high" rather than just
connecting to pin to VCC. I know some of the early 74XXX parts allowed
VCC to be greater than max Vin on the pins but this is not the case
with modern parts. In particular I am designing a very-low power
board and want to minimize power consumed as well as space - hence I
don't want to use pull-ups unless I have to. (In the past I have
always used pull-ups but this has mostly been for historical reasons).

Thanks,
Stuart Adams


Rich W. Herbold

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Jan 20, 1994, 10:41:02 AM1/20/94
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Read the data sheet to determine the input current specification. If
1uA (like with CMOS), you can usually tie the input pin directly high
or low. If in the mA range (like with LS and TTL devices), tie the
input high through a current limiting resistor so as to still guarantee
Vin high min (a low does not require a current limiting resistor). You
can use a single resistor for multiple inputs as long as you adjust the
value to make the same guarantee.

RWH


Richard Steven Walz

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Jan 21, 1994, 8:55:48 AM1/21/94
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In article <CJxq8...@cs690-3.erie.ge.com>,
---------------------------
In CMOS, open inputs should be tied HI or LO, because they have such a nice
high impedance that they can pick up high frequencies or parasitically
oscillate, and then over heat. In TTL, you should pull unused inputs
whatever way necessary to make totem pole outputs high, thus minimizing the
current draw by the unused gates. TTL can be tied directly to power
extremes, but use resistors to limit current pulses into CMOS.
-Steve Walz rst...@armory.com


Clark Bremer

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Jan 21, 1994, 3:34:46 PM1/21/94
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To minimize power consumption, you DO want the pull-up. The largest value you
can get away with!

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Sam Jam

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Jan 27, 1994, 9:02:07 AM1/27/94
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In article <CJzG1...@armory.com>,

rst...@armory.com (Richard Steven Walz) writes:
>In CMOS, open inputs should be tied HI or LO, because they have such a nice
>high impedance that they can pick up high frequencies or parasitically
>oscillate, and then over heat. In TTL, you should pull unused inputs
>whatever way necessary to make totem pole outputs high, thus minimizing the
>current draw by the unused gates. TTL can be tied directly to power
>extremes, but use resistors to limit current pulses into CMOS.
>-Steve Walz rst...@armory.com

I'm sure its the otherway round. CMOS having such mega high input
resistance anyway - and in our digital labs they said TTL should really
have a resisitor...


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Dan Fischer

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Jan 28, 1994, 1:34:17 PM1/28/94
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>In article 3...@dr-pepper.East.Sun.COM, sad...@rome.East.Sun.COM (Stuart Adams - Sun Microsystems Labs BOS) writes:
>When do you have to use pull-ups to tie a pin "high" rather than just
>connecting to pin to VCC. I know some of the early 74XXX parts allowed
>VCC to be greater than max Vin on the pins but this is not the case
>with modern parts. In particular I am designing a very-low power
>board and want to minimize power consumed as well as space - hence I
>don't want to use pull-ups unless I have to. (In the past I have
>always used pull-ups but this has mostly been for historical reasons).
>
>Thanks,
> Stuart Adams
>
Use of pull-up and pull-down resistors is considered good
"design-for-testability" practice when in-circuit testing
will be performed after manufacture. Pay particular attention
to device control lines that tri-state device outputs. In-circuit
testers have a choice - tristate a device and take control of its
outputs, or BACKDRIVE/OVERDRIVE the devices outputs. Not only is
this not the best thing for the device being backdriven, it can
give a test engineer fits/migraines/stress attacks.

I could talk for hours (pages) on use of pull-ups/downs. Bottom
line is, if in-circuit testing is planned, use them!

df
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Marc Nance x6837

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Jan 27, 1994, 8:08:26 AM1/27/94
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CMOS devices can latch up if their input pins exceed the
level of their VCC pin(s). The low power characteristics of CMOS also make
it possible for the devices to try to power up from the input pins if there
is not enough power available on the VCC pin. The pull up resistor limits
the available current (and therefore power) on the input pin. This prevents
the chip from using the input pin as a power source. The current limit also
makes it very difficult for a chip to continue a latch up event caused by
a voltage spike on an input pin. Finally a resistor, combined with the
natural capacitance at the input of the chip tends to limit current spikes
into the chips input pins.
CMOS inputs must always be terminated! For your low power design, review
the gates you need to terminate. If there is no power difference between
tying the input HI or LO tie it directly to GND and save the resistor. If
you will save more power by a HI input, use a high value resistor as a
current limit. As stated above you can share the resistor between these
unused inputs as long as the total leakage current on the input pins doesn't
cause the voltage at the inputs to fall below the guaranteed HI value due to
voltage drop across the resistor.

Marc Nance 426...@fsd.com

Gary Lorman

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Jan 28, 1994, 9:08:19 PM1/28/94
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Another good reason to use pull-ups is testability.
If you tie the pins to VCC or GND, then you cannot overdrive them
to test the device.
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