1. Is there any problem running a 16MHz CPU with an 8MHZ
68450 DMA controller ? Does the async nature of the 68k
bus cope with this ? I can only see the problem being
major when the CPU was addressing the DMA.
2. Is there a better/cheaper 4 channel DMA chip than the 450 ?
3. I hear rumours of PLA equations for interfacing a Zilog
SCC (8530) to a 68k bus, does anyone have these ?
4. With the 68330, if an external bus master accesses memory
selected by one of the on-chip CS* lines, does the CS*
work ? Do DSACKn* or wait states get asserted ?
Any help/advice will be appreciated.
--
andyw. (W0/G1XRL)
an...@aspen.cray.com Andy Warner, Cray Research, Inc. (612) 683-5835
> 3. I hear rumours of PLA equations for interfacing a Zilog
> SCC (8530) to a 68k bus, does anyone have these ?
Check out the 1991 Zilog Datacomm IC's databook. Pages 621 and 697
contain two app notes on this. 697 describes a 20X10 PAL to intfc
any Z85xx part to a 68K. Take a look at the ISCC and page 621 which
talk about the SCC with 4 DMA channels built-in.
At one point, they gave away a little shrink-wrapped package with 3
85xx parts (incl. 8530) and a booklet that gave schematics and PAL eqns
on how to interface all these parts to <insert your favourite micro
here>. The micros included 80x86, 68K, Z8K and some others (?).
> Any help/advice will be appreciated.
You're welcome! :-)
[Datclaimer: I am not a stooge for Zilog; I just like their parts.]
--
"CAUTION: OBJECTS IN SCREEN ARE CLOSER THAN THEY APPEAR"
b...@isgtec.uucp [ ..uunet!utai!lsuc!isgtec!bmw ] Bruce Walker
In <15...@isgtec.UUCP>, Bruce M. Walker writes:
> In article <1991Sep25.1...@hemlock.cray.com> an...@aspen32.cray.com (Andy Warner) writes:
> > 2. Is there a better/cheaper 4 channel DMA chip than the 450 ?
>
> Two Zilog Z8516 DMA controllers would be better if not cheaper (although
> they may not run fast enough for you, I don't think Zilog has kept up
> with rising CPU clock rates with this part).
Choice of your chips depends much on what you want to do with it.
A nice idea which is definitely NOT generally applicable is the following:
For a real-time sampling application we needed a VERY intelligent
DMA-controller.
(No time for the MPU to set registers on and on,
multiple circular buffers and so on)
We used a MC68020 (yes MC68020, the MPU) with a short routine
which fits into the code-cache. So we were able to control
actions by only switching the contents of ONE memory cell.
I only did the soft(-ware) part of the application so really detailed
information on the hardware is not at hand.
Just thought the idea was interesting.
have fun, Uwe
--
Uwe Kloss UUCP: UweK...@lionbbs.han.de
Fasanenstrasse 65 BTX: 0531336908 0001
3300 Braunschweig FIDO: not connected
>
>Just thought the idea was interesting.
>
Sure is.
--
__
John Grana, Performance Technologies Incorporated j...@pt.com
315 Science Parkway, Rochester, New York 14620 uupsi!ptsys1!jjg
Phone: (716) 256-0200 Fax: (716) 256-0791