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RS Flip Flop
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fynn...@gmail.com
Jul 14, 2020, 4:09:28 AM7/14/20
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Please comrades I want to find out when a SET states and a RESET state are obtained in an RS flip flop.
The Net has been confusing me with conflicting facts but l know this learned and honored group will settle it for me as you always do
is the state determined by the S (SET) input or the Q output? Is the criteria the same for both the NOR and NAND gates?
Thank you
The Net has been confusing me with conflicting facts but l know this learned and honored group will settle it for me as you always do
is the state determined by the S (SET) input or the Q output? Is the criteria the same for both the NOR and NAND gates?
Thank you
Pimpom
Jul 14, 2020, 7:44:51 AM7/14/20
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the input. In its basic form, S (SET) makes the Q output go high.
R (RESET) makes the output return to the way it was before, that
is, it resets the state of the output.
This type of question is best asked in sci.electronics.basics
fynn...@gmail.com
Jul 14, 2020, 2:14:32 PM7/14/20
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John Robertson
Jul 14, 2020, 2:52:01 PM7/14/20
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https://tinaja.com/
He wrote some great books on TTL logic and made clear a lot of questions
I had about digital logic when I first started out, as I was never
formally trained in electronics servicing or Boolean Logic.
Note he has many free ebooks!
John :-#)#
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