What limits noise in voltage regulators?

[Rick C]

Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product.

So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.

The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

[whit3rd]

On Wednesday, January 27, 2021 at 9:11:19 PM UTC-8, gnuarm.del...@gmail.com wrote:
> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop.

Usually, a regulator can be made quiet by an output capacitor. If stability is more important than
accuracy, you can downsize the output capacitor and just use a slow op amp and transistor follower.
Bipolar transistors have nicely low output Z as long as they're driving significant current, and
a base capacitor gets capacitance-multiplied.

[Rick C]

What happens to stability when you add the cap to the base? Why would this not work the same for a FET?

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

[upsid...@downunder.com]

On Thu, 28 Jan 2021 00:05:17 -0800 (PST), Rick C
<gnuarm.del...@gmail.com> wrote:

>On Thursday, January 28, 2021 at 12:48:46 AM UTC-5, whit3rd wrote:
>> On Wednesday, January 27, 2021 at 9:11:19 PM UTC-8, gnuarm.del...@gmail.com wrote:
>> > Mostly at higher frequencies, above the useful range of frequency response in the feedback loop.
>> Usually, a regulator can be made quiet by an output capacitor. If stability is more important than
>> accuracy, you can downsize the output capacitor and just use a slow op amp and transistor follower.
>> Bipolar transistors have nicely low output Z as long as they're driving significant current, and
>> a base capacitor gets capacitance-multiplied.
>
>What happens to stability when you add the cap to the base? Why would this not work the same for a FET?

In the old days open loop voltage regulators were often used, i.e. an
emitter follower driven by a constant voltage at the base, The base
voltage is just Vbe drop higher than the desired output voltage and
typically generated by a zener diode, thus no feedback.

The transistor fT determines how well the output noise follows the
base noise at higher frequencies. The low power base circuit noise is
easier to suppress than the full power output noise.

The bipolar Vbe drop is quite well defined, thus the output voltage is
quite predictable. Open loop regulators work better with higher
voltages, but usually the variations of Vbe is too large for 3.3 V and
lower output voltages, requiring a feedback construction.

[Rocky]

On Thursday, 28 January 2021 at 10:55:08 UTC+2, upsid...@downunder.com wrote:
> On Thu, 28 Jan 2021 00:05:17 -0800 (PST), Rick C
> <gnuarm.del...@gmail.com> wrote:

snip

> >What happens to stability when you add the cap to the base? Why would this not work the same for a FET?
> In the old days open loop voltage regulators were often used, i.e. an
> emitter follower driven by a constant voltage at the base, The base
> voltage is just Vbe drop higher than the desired output voltage and
> typically generated by a zener diode, thus no feedback.

snip
Having a base cap and an emitter cap /may/ create a parasitic colpits oscillator.

[whit3rd]

On Thursday, January 28, 2021 at 12:05:22 AM UTC-8, gnuarm.del...@gmail.com wrote:
> On Thursday, January 28, 2021 at 12:48:46 AM UTC-5, whit3rd wrote:
> > On Wednesday, January 27, 2021 at 9:11:19 PM UTC-8, gnuarm.del...@gmail.com wrote:
> > > Mostly at higher frequencies, above the useful range of frequency response in the feedback loop.

> > Usually, a regulator can be made quiet by an output capacitor. If stability is more important than
> > accuracy, you can downsize the output capacitor and just use a slow op amp and transistor follower.
> > Bipolar transistors have nicely low output Z as long as they're driving significant current, and
> > a base capacitor gets capacitance-multiplied.

> What happens to stability when you add the cap to the base? Why would this not work the same for a FET?

A bipolar transistor emitter has lower output impedance than a MOSFET source, in follower
connection. So, it regulates output voltage better with current-drawn variations, at frequencies above
effective feedback control.

Output impedance = dV_{be}/dI = 0.025/I at room temperature (from an Ebers-Moll model)
so at 200 mA, it's about 0.13 ohms.

[Phil Hobbs]

Rick C wrote:
> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..

>
> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>
> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
>

Use a BJT, or two in series. My go-to is a single stage, two- or
three-pole cap multiplier (two or three RC sections in the base), one in
the collector (might as well use that V_BE drop for something useful)
and one at the output. You can get sub-nanovolt noise densities that way.

Of course there's not a lot you can do at very low frequencies but buy a
quieter reference.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[Liz Tuddenham]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

[...]

> Of course there's not a lot you can do at very low frequencies but buy a
> quieter reference.

A handy trick is to stand up a general purpose regulator on a diode or
two to get a slightly higher output voltage, then use a long
time-constant RC network to remove the noise down to whatever lowest
frequency you need. Feed the Base of a low noise audio transistor from
the quiet supply, power the Collector from the slightly-higher
stabilised rail and take the load current from the Emitter (as an
emitter follower).

The stabilisation with variations in load will be poorer but the L.F.
noise level will be excellent. I have used that circuit for feeding
electret mic capsules.

It also gives you the option of referring your low-noise supply to a
signal earth (or even a wanted signal source) at the bottom of the
capacitor, rather than a power earth which may introduce extra noise.


--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

[jla...@highlandsniptechnology.com]

On Thu, 28 Jan 2021 08:41:54 -0500, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>Rick C wrote:
>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
>>
>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>>
>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
>>
>
>Use a BJT, or two in series. My go-to is a single stage, two- or
>three-pole cap multiplier (two or three RC sections in the base), one in
>the collector (might as well use that V_BE drop for something useful)
>and one at the output. You can get sub-nanovolt noise densities that way.
>
>Of course there's not a lot you can do at very low frequencies but buy a
>quieter reference.
>
>Cheers
>
>Phil Hobbs

You can just hang a giant polymer cap on a regulator output. It gets
better as the regulator loop gets worse.

Or, as someone mentioned, make your own regulator with a well-filtered
reference and a good opamp. Some linear regs include a reference
bypass pin.

Bypassing the adj pin of a 3t reg often helps too. Or bypassing one
feedback resistor for the other kind.







--

John Larkin Highland Technology, Inc

The best designs are necessarily accidental.

[George Herold]

On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
> Rick C wrote:
> > Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
> >
> > So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
> >
> > The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
> >
> Use a BJT, or two in series. My go-to is a single stage, two- or
> three-pole cap multiplier (two or three RC sections in the base), one in
> the collector (might as well use that V_BE drop for something useful)
> and one at the output. You can get sub-nanovolt noise densities that way.

'one in the collector', scratch scratch, scribble...
Where does the collector RC go? anywhere I put it looks to increase to resistance
(power supply source resistance) of the cap multiplier.

George H.
(who needs to start a thread on higher current cap mults. with either a
Darlington or Sziklai as pass element... but I need to order some
transistors first.)

[Phil Hobbs]

Adrian, you need to keep your alter ego for the weekend. ;)

I occasionally put the cap multiplier inside the DC feedback loop of a
regulator, with AC feedback taken from the collector circuit so it
doesn't oscillate. Cheap shunt voltage references tend to be very noisy,
and the Zout of an emitter follower is pretty low, so I usually just
hang the cap multiplier off an LM1117 or a switcher.

Discrete circuits can have wonderful properties, but good supply
rejection is not one of them. Cap multipliers fix it.

[Phil Hobbs]

Biasing a photodiode off a switcher rail requires like >150 dB of noise
rejection. A cap multiplier can do that, if you give it some help in
the collector circuit, but a single bypass is not going to get you
there. (Well, 150 dB will probably take two transistors, I admit. You
also have to be insanely scrupulous about layout.)

[Clifford Heath]

On 29/1/21 4:06 am, jla...@highlandsniptechnology.com wrote:
> You can just hang a giant polymer cap on a regulator output. It gets
> better as the regulator loop gets worse.

Salient point! Just beware of the reverse, too. If you're trying to
avoid massive supply current spikes being passed through from the load,
you can't do that with a big load-side capacitor if your regulation is
tight. The regulator just sees the cap voltage drop and opens wide to
replenish it.

CH

[Phil Hobbs]

George Herold wrote:
> On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
>> Rick C wrote:
>>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
>>>
>>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>>>
>>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
>>>
>> Use a BJT, or two in series. My go-to is a single stage, two- or
>> three-pole cap multiplier (two or three RC sections in the base), one in
>> the collector (might as well use that V_BE drop for something useful)
>> and one at the output. You can get sub-nanovolt noise densities that way.
>
> 'one in the collector', scratch scratch, scribble...
> Where does the collector RC go? anywhere I put it looks to increase to resistance
> (power supply source resistance) of the cap multiplier.

You've got a whole V_BE to play with in the collector circuit before you
run into any trouble, so you pick the resistor to drop maybe 0.4V at max
current, and size the cap appropriately. You can also use an LC.

In my Class H TEC driver, I use an all-reactive cap multiplier, which
also works very well.

>
> George H.
> (who needs to start a thread on higher current cap mults. with either a
> Darlington or Sziklai as pass element... but I need to order some
> transistors first.)

Sziklai for my money. Local feedback is almost always a win.

(The switcheroo Wilson current mirror [not the usual Wilson] has three
feedback loops made from four components total.)

[jla...@highlandsniptechnology.com]

On Thu, 28 Jan 2021 20:28:58 -0500, Phil Hobbs

For low DC currents, a few stages of RC filtering is pretty good.

150 dB is kind of demanding. That might need a can, and some exotic
ground planes, stuff not on the schematic.

[Phil Hobbs]

Yup. Round here we mark places on the schematic that will need
super-good isolation with a pink highlighter, so it's called 'the pink
treatment'. Faraday cage, blind vias, multipole filtering, minimal loop
areas, tight restrictions on what can be on the back side and what
traces can be routed through the area (even on the other side of the
featureless ground plane), and a can over the whole works. (Lotsa via
stitching on the mounting pads for the can, too.)

We had one PSU board with a 1.5 MHz async buck switcher making -17 from
an intermediate +12 rail.(*) It was supposed to be an AOZ1280, but in
reality was a Chinese counterfeit that the CM had in stock.

Parts of that board showed a whole lot of 125 MHz junk, and other parts
almost as much junk but at 180 MHz. Turned out to be harmonics from
that buck switcher, selected by transmission line resonances in the
board. They got into everything that was powered off that intermediate
rail (i.e. just about everything).

Turning off the negative reg cleaned the whole board right up.

Cheers

Phil Hobbs


(*) The +12 was needed because the negative reg's voltage rating wasn't
high enough to make -17 from +24 directly. It was made by an LMR23630
sync buck, which is a very nice part if you watch out for the ~600 ps edges.

[jla...@highlandsniptechnology.com]

On Fri, 29 Jan 2021 05:41:04 -0500, Phil Hobbs

We don't often hang around the noise floor. We usually have enough
electrical or optical signal to break things. One place we do have
problems is time jitter. Switchers and picosecond jitter don't
co-exist well on a board.

"Demodulating time" can extract the jitter component, and the
recovered frequency hints at the source of the wobble. HP once had an
instrument to do that. One trick is to use a sampling scope to look at
an edge, zoomed way up, and vary the system trigger rate. What looks
like noise can sometimes be heterodyned and revealed to have
structure, then one applies some simple number theory to relate it to
one of the switchers on the board. Or touch/spritz each switcher to
see which one is the cause.

I had one LTM8078 switcher making jitter that was so close to 200.000
KHz that I was sure a crystal oscillator was involved. It wasn't.

I have this problem often enough that I should build a time-to-voltage
converter probe somehow.

>(*) The +12 was needed because the negative reg's voltage rating wasn't
>high enough to make -17 from +24 directly. It was made by an LMR23630
>sync buck, which is a very nice part if you watch out for the ~600 ps edges.

Some synchronous switchers make insane edges.

https://www.dropbox.com/s/u7gcciyon6181d0/LM3102_SwitcherRise.JPG?raw=1

Looks like a drift-step-recovery substrate diode to me. It freaked out
opamps 6 inches away.

The little LTM bricks seem to keep most of that sort of thing onboard.
I think TI has some similar switcher blocks now, with the inductor and
some capacitance included. That helps with ground loops.

I sometimes put nasty circuits on mouse-bite subassemblies.

[George Herold]

Right, I used a cap mult on the end of a supply for biasing led's for
shot noise measurements.
Switching supply, LC lowpass, Voltage Reg., cap mult.
My big mistake was not paying enough attention to the noise
in the voltage reg. It was the biggest noise source into the
CM.
Later design replaced Volt reg, with volt ref and opamp.
(w/ RC stages between reference and opamp.)

George H.

[legg]

The minimum achievable is going to be related to the reference and
regulator components along with their layout and environment - so
a low frequency issue that can't be addressed with filtering.

The active components can also be affected by HF modulation as well,
so shielding and placement of noise sources also has to be
considered.

As peak and random deviation are time-related, it will also be
dependent on measurement technique. Measuring equipment obviously
has to be quieter than the thing being measured, so toss your
digital scopes, multiplexed dataloggers etc etc etc. . . .

RL

[George Herold]

On Thursday, January 28, 2021 at 8:34:42 PM UTC-5, Phil Hobbs wrote:
> George Herold wrote:
> > On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
> >> Rick C wrote:
> >>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
> >>>
> >>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
> >>>
> >>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
> >>>
> >> Use a BJT, or two in series. My go-to is a single stage, two- or
> >> three-pole cap multiplier (two or three RC sections in the base), one in
> >> the collector (might as well use that V_BE drop for something useful)
> >> and one at the output. You can get sub-nanovolt noise densities that way.
> >
> > 'one in the collector', scratch scratch, scribble...
> > Where does the collector RC go? anywhere I put it looks to increase to resistance
> > (power supply source resistance) of the cap multiplier.
> You've got a whole V_BE to play with in the collector circuit before you
> run into any trouble, so you pick the resistor to drop maybe 0.4V at max
> current, and size the cap appropriately. You can also use an LC.

Sorry to be so dense, but you're running the R from collector to
emitter,(?) with an emitter cap to ground?

I must say that a resistor across the transistor seems like the wrong
thing to do...

George H.

[jla...@highlandsniptechnology.com]

On Fri, 29 Jan 2021 10:21:49 -0800 (PST), George Herold
<gghe...@gmail.com> wrote:

>On Thursday, January 28, 2021 at 8:34:42 PM UTC-5, Phil Hobbs wrote:
>> George Herold wrote:
>> > On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
>> >> Rick C wrote:
>> >>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
>> >>>
>> >>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>> >>>
>> >>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
>> >>>
>> >> Use a BJT, or two in series. My go-to is a single stage, two- or
>> >> three-pole cap multiplier (two or three RC sections in the base), one in
>> >> the collector (might as well use that V_BE drop for something useful)
>> >> and one at the output. You can get sub-nanovolt noise densities that way.
>> >
>> > 'one in the collector', scratch scratch, scribble...
>> > Where does the collector RC go? anywhere I put it looks to increase to resistance
>> > (power supply source resistance) of the cap multiplier.
>> You've got a whole V_BE to play with in the collector circuit before you
>> run into any trouble, so you pick the resistor to drop maybe 0.4V at max
>> current, and size the cap appropriately. You can also use an LC.
>Sorry to be so dense, but you're running the R from collector to
>emitter,(?) with an emitter cap to ground?
>
>I must say that a resistor across the transistor seems like the wrong
>thing to do...

It can shift power dissipation. The old Tek tube scopes did that a lot
in the power supplies.

Sometimes a series resistor, in the input of a transistor or a
regulator, will reduce worst-case dissipation, and it's an opportunity
to noise filter too.

[George Herold]

Huh OK, I'll have to try it. Thanks.

>
> Sometimes a series resistor, in the input of a transistor or a
> regulator, will reduce worst-case dissipation, and it's an opportunity
> to noise filter too.

Right, I've done that some. First to mind is a class A current source
for driving ~1 ohm coils. 1Amp max and only +15V supply.
10 ohm resistor, burns power but it did make the coils
snappier (L/R time)

George H.

[Phil Hobbs]

George Herold wrote:
> On Thursday, January 28, 2021 at 8:34:42 PM UTC-5, Phil Hobbs wrote:
>> George Herold wrote:
>>> On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
>>>> Rick C wrote:
>>>>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
>>>>>
>>>>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>>>>>
>>>>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?
>>>>>
>>>> Use a BJT, or two in series. My go-to is a single stage, two- or
>>>> three-pole cap multiplier (two or three RC sections in the base), one in
>>>> the collector (might as well use that V_BE drop for something useful)
>>>> and one at the output. You can get sub-nanovolt noise densities that way.
>>>
>>> 'one in the collector', scratch scratch, scribble...
>>> Where does the collector RC go? anywhere I put it looks to increase to resistance
>>> (power supply source resistance) of the cap multiplier.
>> You've got a whole V_BE to play with in the collector circuit before you
>> run into any trouble, so you pick the resistor to drop maybe 0.4V at max
>> current, and size the cap appropriately. You can also use an LC.
> Sorry to be so dense, but you're running the R from collector to
> emitter,(?) with an emitter cap to ground?
>
> I must say that a resistor across the transistor seems like the wrong
> thing to do...

No, the resistor is in series with the collector, and the capacitor goes
from there to ground. At very high isolation, junk gets in via
capacitance and the Early effect otherwise. (BJTs are good that way,
but not 150 dB worth of good.)

It's sometimes useful to put a largish resistor from base to emitter to
make sure there's enough CB bias for good performance--since it's got a
BE drop across it, it's a reasonably-constant current source. That's
needed especially when using a 2-stage cap multiplier, because without
it the V_BE of the first stage puts the second stage into saturation.
(Assuming that you use a single RC ladder for both bases, which you should.)

[George Herold]

OK so this is after the node that feeds the base RC,
and the Vbe drop of which you spoke is because I can run the collector
a little closer to the emitter than the base is ? (Vce<Vbe)

I wonder if I design cap mults wrong?
1.) I want the Vin -> base resistance to be as big as possible.
(I'm now wondering about this. the bad thing about big R_base
is it gives the low noise supply a larger source resistance.)
Big R_base gives me a long time constant for a given capacitance
2.) I then take the max current, (let's say 100mA, cause that is one I did.)
3.) and a conservative guess at current gain, say 100 for the 2n4401
4.) and at max current I want less than/about a volt of drop across R_base
So for this example that's 1V/1mA = 1k ohm.
5.) I wanted it to have a LF time constant of ~100ms so C_base = 100uF.
Now that I'm almost done, I think it was the 100ms TC that drove the desire
for large R. Two RC stages of 100ms does a nice job of knocking down the
60 Hz. crud.
6.) you build the thing, see how it works, tweak if needed.

>
> It's sometimes useful to put a largish resistor from base to emitter to
> make sure there's enough CB bias for good performance--since it's got a
> BE drop across it, it's a reasonably-constant current source. That's
> needed especially when using a 2-stage cap multiplier, because without
> it the V_BE of the first stage puts the second stage into saturation.
> (Assuming that you use a single RC ladder for both bases, which you should.)

Huh.. do you get phase shift issues inside a two stage thing?
The last thing you want is to make anything close to an oscillator.

George H.

[Phil Hobbs]

George Herold wrote:
> On Friday, January 29, 2021 at 2:27:23 PM UTC-5, Phil Hobbs wrote:
>> George Herold wrote:
>>> On Thursday, January 28, 2021 at 8:34:42 PM UTC-5, Phil Hobbs wrote:
>>>> George Herold wrote:
>>>>> On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote:
>>>>>> Rick C wrote:
>>>>>>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product..
>>>>>>>

>>>>>>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances..

The two are simply in cascade. There's no feedback to speak of. For a
two-stage cap multiplier, you just go


Q1 Q2
0-*-R1R1---*----* *--------* *----*--0
| | \ A \ A |
| giant CCC ------ ------ |
| alpo CCC | | |
| | | | |
| GND | | bias |
| | | |
*-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
| | | | |
CCC CCC CCC CCC CCCC giant
CCC CCC CCC CCC CCCC alpo
| | | | |
GND GND GND GND GND

(Extra points for using quad pack resistors intelligently.)

You pick the bias resistor R6 such that R4+R5 drop enough to keep Q2
from saturating.

Good transistors include the 2SD2704K for currents below about 20 mA,
and its big, low voltage brother 2SD2114 up to 500 mA or so. They're
both low-sat superbeta devices, although slow as molasses, which puts
more of a demand on the alpos' high frequency behaviour.

You also need some input protection, because folks will inevitably short
the input to ground or attach a car battery to it.

[Kevin Aylward]

"whit3rd" wrote in message
news:e989c8d4-ea51-4778...@googlegroups.com...

In practice, its more subtle than this, such that the raw gm of the output
devices is not a key factor in the regulation design of a regulator. indeed,
a typical problem is that the gm of the output device, even for mosfets, is
too high.

The stability and dc regulation of the regulator is a function of ALL of the
gain stages in the loop. It doesn't really matter where this gain is
distributed as far as the basic regulation of the system is concerned.
Internal DC gains of 80 dB-100 dB isn't usually a problem to achieve.
However, large DC gains, even with compensation, translate to tricky
stabilisation issues.

The "low" output resistance of a bipolar in emitter follower mode is also an
illusion. It only achieves this low resistance because it has an internal
feedback loop of output current to input emitter voltage. The raw output
resistance of a bipolar is high, because it is fundamentally a voltage
controlled current source. To analyse the loop, all loops need to be broken
at once. This is analysed here:

https://www.kevinaylward.co.uk/ee/osc_loop_gain/osc_loop_gain.xht
.

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

[George Herold]

Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?
I have found it hard to de-scramble the above. Google takes out the spaces...
I try and put them in to make the picture make sense... but...
Has anyone found a way to recover the ascii art in google groups?

George H

[jla...@highlandsniptechnology.com]

If you don't need a lot of current, why not use one quad r-pack and 5
caps? Current limiting is free.

[Phil Hobbs]

George Herold wrote:
> On Saturday, January 30, 2021 at 12:29:59 AM UTC-5, Phil Hobbs wrote:

<sniiip>

>> Q1 Q2
>> 0-*-R1R1---*----* *--------* *----*--0
>> | | \ A \ A |
>> | giant CCC ------ ------ |
>> | alpo CCC | | |
>> | | | | |
>> | GND | | bias |
>> | | | |
>> *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
>> | | | | |
>> CCC CCC CCC CCC CCCC giant
>> CCC CCC CCC CCC CCCC alpo
>> | | | | |
>> GND GND GND GND GND
>>
>
> Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?

> I have found it hard to de-scramble the above. Google takes out the spaces....

> I try and put them in to make the picture make sense... but...
> Has anyone found a way to recover the ascii art in google groups?
>

They totally screwed up all the Python code posted over the years, too.
In Python spaces are part of the semantics. They could just have
run-length encoded the spaces, but noooooo.

I posted the ASCII at
<https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt>
.
There's also an LTspice file there from five or so years ago,
<https://electrooptical.net/www/sed/TwoSectionCapMultiplierTrans.asc>

[Rick C]

On Saturday, January 30, 2021 at 12:09:27 PM UTC-5, George Herold wrote:
> >
> Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?
> I have found it hard to de-scramble the above. Google takes out the spaces...
> I try and put them in to make the picture make sense... but...
> Has anyone found a way to recover the ascii art in google groups?

This was not a problem under the old interface. I was able to continue using the old interface for some time after they switched because I leave a window open and simply access each group when interested. I found in another window that a reload retrieved the new interface, but was able to use the historical window for over a week before it ran into a GG bug that required a reload. If someone could figure out what changed in the web page code, perhaps another source of the interface web code could still access the GG data? Or we could use another client altogether and forget about GG.

The guy who makes and sells the Beagle Boards used GG for his support channel. I don't know if he still does or if Google screwed him over. There is a GG for EV charging with various categories and lots of info. I think some of the more recent changes make that group much harder to use. So it's not all just issues with newsgroups.

One of the nice features of GG is the fact that it is based on a browser, so when a link appears it is easy to open or a phrase is easy to research or a word to lookup. My spelling is horrible and the common spell checker on my machine (don't know if there's a common one for all the apps or if they each have their own, I've never figured that out) is pretty stupid not knowing many, many common words. Before I shove a new word into the dictionary I check the spelling with a web search. Easy peasy while in the browser.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

[whit3rd]

On Friday, January 29, 2021 at 11:27:23 AM UTC-8, Phil Hobbs wrote:

> No, the resistor is in series with the collector, and the capacitor goes
> from there to ground. At very high isolation, junk gets in via
> capacitance and the Early effect otherwise. (BJTs are good that way,
> but not 150 dB worth of good.)

In other words, use a pi filter to the collector of the capacitance multiplier...
because this is about backing up an already-filtered DC supply, isn't it?

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

> I posted the ASCII at
> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt>
> .
> There's also an LTspice file there from five or so years ago,
> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierTrans.asc>
>
> Cheers
>
> Phil Hobbs

Very good.

This shows the ripple at the collector of Q2, and the resulting ripple at the
output in uV:

http://s000.tinyupload.com/index.php?file_id=06788871958645763979



--
The best designs occur in the theta state. - sw

[Phil Hobbs]

Usually because I need to power some glorified CPH3910 JFET stage that
takes 20-40 mA altogether. BF862s work great at about 10-12 mA, but the
3910's I_DSS is much higher. Occasionally I power part of the circuit
off the first cap multiplier stage and part off the second, but I've
only done that once or twice. You get a nice bit of isolation between
the two parts, but you have to waste some headroom making sure that the
load variations on the first stage don't push the second into
saturation. Even a little bit of beta modulation makes a big difference
there.

The overall issue is that single-ended discrete stages have little or no
PSR, so the cap multiplier has to carry the freight.

[Phil Hobbs]

Generally it's to turn a switcher rail with ~100 mV ripple and lots of
other junk into something suitable for ultrasensitive measurements (~30
nV ripple, ~1 nV noise in 1 Hz). See the stuff I posted upthread.

Back in the palmy days, we ultrasensitive measurements folk could just
say "You have to use a linear supply" and make that stick. Not any more.

[whit3rd]

On Saturday, January 30, 2021 at 1:56:21 AM UTC-8, Kevin Aylward wrote:
> "whit3rd" wrote in message
> news:e989c8d4-ea51-4778...@googlegroups.com...
> >On Thursday, January 28, 2021 at 12:05:22 AM UTC-8, gnuarm.del...@gmail.com
> >wrote:
> >> On Thursday, January 28, 2021 at 12:48:46 AM UTC-5, whit3rd wrote:
> > > On Wednesday, January 27, 2021 at 9:11:19 PM UTC-8,
> > > gnuarm.del...@gmail.com wrote:

[about quieting a regulated source]

> > > > Mostly at higher frequencies, above the useful range of frequency
> > > > response in the feedback loop.

> >> >>...you can downsize the output capacitor and just use a slow op

> >> >> amp and transistor follower.
> >> >> Bipolar transistors have nicely low output Z as long as they're
> >> >> driving significant current, and
> >>> > a base capacitor gets capacitance-multiplied.
>
> >>> What happens to stability when you add the cap to the base? Why would
> >>> this not work the same for a FET?
>
> >>A bipolar transistor emitter has lower output impedance than a MOSFET
> >>source, in follower
> >>connection. So, it regulates output voltage better with current-drawn
> >>variations, at frequencies above
> >>effective feedback control.
>
> >>Output impedance = dV_{be}/dI = 0.025/I at room temperature (from an
> >>Ebers-Moll model)
> >>so at 200 mA, it's about 0.13 ohms.
> In practice, its more subtle than this, such that the raw gm of the output
> devices is not a key factor in the regulation design of a regulator. indeed,
> a typical problem is that the gm of the output device, even for mosfets, is
> too high.

An emitter follower has voltage gain slightly less than one, so 'gm' isn't
really a relevant specification there; the overall feedback loop was stable
because of the 'slow op amp' parts, which operate within the
'useful range of frequency response' while the cap multiplier operates
above that range.

> The stability and dc regulation of the regulator is a function of ALL of the
> gain stages in the loop. It doesn't really matter where this gain is
> distributed as far as the basic regulation of the system is concerned.
> Internal DC gains of 80 dB-100 dB isn't usually a problem to achieve.
> However, large DC gains, even with compensation, translate to tricky
> stabilisation issues.

True enough. I've seen some applications where it takes mercury-based
batteries to get low noise, and temperature control, and.... Gain isn't free
if you value low noise.

[legg]

On Wed, 27 Jan 2021 21:11:15 -0800 (PST), Rick C
<gnuarm.del...@gmail.com> wrote:

>Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product.
>

>So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.
>

>The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?

An low power, a noise cancellation circuit might make more sense.

It shouldn't require headroom, being capacitively coupled, just
impedance isolation from the noise source, over the frequency band of
interest.

RL

[Kevin Aylward]

"whit3rd" wrote in message
news:99dea115-fdd3-48cf...@googlegroups.com...

On Saturday, January 30, 2021 at 1:56:21 AM UTC-8, Kevin Aylward wrote:
> "whit3rd" wrote in message

>

> >>A bipolar transistor emitter has lower output impedance than a MOSFET
> >>source, in follower
> >>connection. So, it regulates output voltage better with current-drawn
> >>variations, at frequencies above
> >>effective feedback control.
>
> >>Output impedance = dV_{be}/dI = 0.025/I at room temperature (from an
> >>Ebers-Moll model)
> >>so at 200 mA, it's about 0.13 ohms.
>> In practice, its more subtle than this, such that the raw gm of the
>> output
>> devices is not a key factor in the regulation design of a regulator.
>> indeed,
>> a typical problem is that the gm of the output device, even for mosfets,
>> is
>> too high.

>An emitter follower has voltage gain slightly less than one, so 'gm' isn't
>really a relevant specification there;

It is relevant. I explained why. A feedback system containing an emitter
follower doesn't work how most assume it does.

>the overall feedback loop was stable
>because of the 'slow op amp' parts, which operate within the
>'useful range of frequency response' while the cap multiplier operates
>above that range.

....as I explained, the "unity gain" concept of an emitter follower is
erroneous in feedback analysis. It doesn't directly account for the
stability of a feedback amplifier.

as I noted, to understand the technical point, you really should read this:

https://www.kevinaylward.co.uk/ee/osc_loop_gain/osc_loop_gain.xht

It needs to be understood, as I stated, that an emitter follower only looks
like it has low output resistance is because it is a negative feedback
system. A bipolar transistor is inherently a current source.

The essentials of a regulator, with an emitter follower output is that one
has an amplifier 1, with gain. It feeds another amplifier 2 that,
essentially,looks like an op amp with 100% feedback. There is an overall
feedback loop from amplifier 2 to amplifier 1. Its a dual loop system.

The second amplifier, is the output emitter follower. To understand the
stability of the system, one must break BOTH loops at once.

The loop gain will then seen to be LG=A1.gm.Zload

The "raw" gm is not a key factor in the *regulation* specification, because
its the product of A1.gm.ZL that matters. If the gm is not that which is
required, then the gain A1 can be changed. However, the gm itself is indeed
a key component that needs to be addressed to stabilise the system.

If the system actually used a collector output, the basic transfer equation
would, essentially, still be the same.

The advantage in the case of using an emitter follower in practice, is that
additional AC feedback can be placed from the bipolar base back to the main
negative input, thus taking the transistor out of the loop for high
frequencies. This cannot be done for the collector output topology. The
disadvantage of the follower topology, is that that one cannot achieve a low
dropout voltage.

[George Herold]

On Saturday, January 30, 2021 at 12:59:44 PM UTC-5, Phil Hobbs wrote:
> George Herold wrote:
> > On Saturday, January 30, 2021 at 12:29:59 AM UTC-5, Phil Hobbs wrote:
> <sniiip>
> >> Q1 Q2
> >> 0-*-R1R1---*----* *--------* *----*--0
> >> | | \ A \ A |
> >> | giant CCC ------ ------ |
> >> | alpo CCC | | |
> >> | | | | |
> >> | GND | | bias |
> >> | | | |
> >> *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
> >> | | | | |
> >> CCC CCC CCC CCC CCCC giant
> >> CCC CCC CCC CCC CCCC alpo
> >> | | | | |
> >> GND GND GND GND GND
> >>
> >
> > Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?
> > I have found it hard to de-scramble the above. Google takes out the spaces....
> > I try and put them in to make the picture make sense... but...
> > Has anyone found a way to recover the ascii art in google groups?
> >
> They totally screwed up all the Python code posted over the years, too.
> In Python spaces are part of the semantics. They could just have
> run-length encoded the spaces, but noooooo.
>
> I posted the ASCII at
> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt>

Thanks Phil, I was picturing a Darlington or Sziklia, so had no hope of reconstructing the
right pic.
(the quad resistor pac should be all the base resistors.. I don't think the order
makes much difference. It's a filter... keep input away from output. I'd do a string.)
George H.

[George Herold]

On Saturday, January 30, 2021 at 4:03:14 PM UTC-5, Phil Hobbs wrote:
> whit3rd wrote:
> > On Friday, January 29, 2021 at 11:27:23 AM UTC-8, Phil Hobbs wrote:
> >
> >> No, the resistor is in series with the collector, and the capacitor goes
> >> from there to ground. At very high isolation, junk gets in via
> >> capacitance and the Early effect otherwise. (BJTs are good that way,
> >> but not 150 dB worth of good.)
> >
> > In other words, use a pi filter to the collector of the capacitance multiplier...
> > because this is about backing up an already-filtered DC supply, isn't it?
> Generally it's to turn a switcher rail with ~100 mV ripple and lots of
> other junk into something suitable for ultrasensitive measurements (~30
> nV ripple, ~1 nV noise in 1 Hz). See the stuff I posted upthread.
>
> Back in the palmy days, we ultrasensitive measurements folk could just
> say "You have to use a linear supply" and make that stick. Not any more.

The AC magnetic stuff* in linear supplies was a pain. There is something to be said for
a brick on the rope switcher... where you can put the supply over there...
and just have to worry about filtering the electrical path.

George H.
* this mostly seemed to be radiated... moving the linear supply away (on long wires)
reduces the 'stuff'.

[gray_wolf]

On 31/01/2021 3:59 pm, George Herold wrote:
> On Saturday, January 30, 2021 at 12:59:44 PM UTC-5, Phil Hobbs wrote:
>> George Herold wrote:
>>> On Saturday, January 30, 2021 at 12:29:59 AM UTC-5, Phil Hobbs wrote:
>> <sniiip>
>>>> Q1 Q2
>>>> 0-*-R1R1---*----* *--------* *----*--0
>>>> | | \ A \ A |
>>>> | giant CCC ------ ------ |
>>>> | alpo CCC | | |
>>>> | | | | |
>>>> | GND | | bias |
>>>> | | | |
>>>> *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
>>>> | | | | |
>>>> CCC CCC CCC CCC CCCC giant
>>>> CCC CCC CCC CCC CCCC alpo
>>>> | | | | |
>>>> GND GND GND GND GND
>>>>
>>>
>>> Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?
>>> I have found it hard to de-scramble the above. Google takes out the spaces....
>>> I try and put them in to make the picture make sense... but...
>>> Has anyone found a way to recover the ascii art in google groups?

I don't know about googlegroups but I'd just copy the text, paste it in an
editor and change the font to 'fixed width'. Veritable width fonts will screw
ascii art to bits

       /\     /\
      /^ \'''/ ^\
         -   -
        @   @
___o00o__( )__o00o___

The Dog says "Woof!"

[Rick C]

The trouble is ascii art is highly dependant on the spacing and GG rips that down to a single space between "words".

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

[Liz Tuddenham]

Use a non-breaking space. It's only a matter of holding down a modifier
key on old Macs (I don't know what is involved on modern ones or on
PCs).


--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

[Phil Hobbs]

It's worse than that. Google just strips out all the spaces after the
first one, so that information is actually destroyed.

Otherwise that scrooched thing George posted would have rendered
properly in a real newsreader.

[George Herold]

Right, I cut and pasted into text editor... with hopes of recovering the pic
by just adding leading spaces one each line...
But no! All 'extra' spaces have been taken out.
usernet ascii art ruined by google. If someone knew someone....
I sent feedback saying I wanted the 'show original' option back.
(no response from gg.)
George h.

[Simon S Aysdie]

On Saturday, January 30, 2021 at 9:09:27 AM UTC-8, George Herold wrote:
> On Saturday, January 30, 2021 at 12:29:59 AM UTC-5, Phil Hobbs wrote:
> > The two are simply in cascade. There's no feedback to speak of. For a
> > two-stage cap multiplier, you just go
> >
> >
> > Q1 Q2
> > 0-*-R1R1---*----* *--------* *----*--0
> > | | \ A \ A |
> > | giant CCC ------ ------ |
> > | alpo CCC | | |
> > | | | | |
> > | GND | | bias |
> > | | | |
> > *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
> > | | | | |
> > CCC CCC CCC CCC CCCC giant
> > CCC CCC CCC CCC CCCC alpo
> > | | | | |
> > GND GND GND GND GND
> >
> Thanks Phil, Can I ask a favor? Could you send the above ascii art to my email?
> I have found it hard to de-scramble the above. Google takes out the spaces...
> I try and put them in to make the picture make sense... but...
> Has anyone found a way to recover the ascii art in google groups?

This is a ascii schematic test... It assumes Unicode works in GG.

In one case I replaced all spaces (U+0020 SPACE [SP]) with a U+00D7 MULTIPLICATION SIGN, as a dummy, that hopefully does not get stripped. In the second case I tried someone's suggestion of using a non breaking space... in case the Google Shiva does not see it as white space to be minimized.

In the following, all spaces replaced with ×.
In Notepad++, use CTRL-H to replace all × with a space to re-constuct it.

××1×├───R───┤××××50.000000××Ω
××3×├───C───┤××××25.305273×pF
××××│×××××┌─┴┐
××4×│×××××L××C××131.970860×nH×res.frequency
××××│×××××└─┬┘×××16.562015×pF×107.652600×MHz
××5×├───C───┤××××42.452992×pF
××××│×××××┌─┴┐
××6×│×××××L××C××190.021181×nH×res.frequency
××××│×××××└─┬┘×××17.132488×pF××88.208190×MHz
××8×│×××××××C××××48.891234×pF
××9×├──L─C──┤×××266.819370×nH×res.×frequency
××××│×××××××│×××190.531166×pF××22.321760×MHz
×11×├───C───┤××××54.368883×pF
××××│×××××┌─┴┐
×12×│×××××L××C×××81.504415×nH×res.frequency
××××│×××××└─┬┘×××47.125095×pF××81.208866×MHz
×14×│×××××××C××××91.843591×pF
×15×├───C───┤×××××4.580406×pF
×17×├───R───┤××××74.078142××Ω

All non-breaking space
U+00A0 NO-BREAK SPACE [NBSP]
 1 ├───R───┤   50.000000  Ω
 3 ├───C───┤   25.305273 pF
   │     ┌─┴┐
 4 │     L  C 131.970860 nH res.frequency
   │     └─┬┘  16.562015 pF 107.652600 MHz
 5 ├───C───┤   42.452992 pF
   │     ┌─┴┐
 6 │     L  C 190.021181 nH res.frequency
   │     └─┬┘  17.132488 pF  88.208190 MHz
 8 │       C   48.891234 pF
 9 ├──L─C──┤  266.819370 nH res. frequency
   │       │  190.531166 pF  22.321760 MHz
11 ├───C───┤   54.368883 pF
   │     ┌─┴┐
12 │     L  C  81.504415 nH res.frequency
   │     └─┬┘  47.125095 pF  81.208866 MHz
14 │       C   91.843591 pF
15 ├───C───┤    4.580406 pF
17 ├───R───┤   74.078142  Ω

[Simon S Aysdie]

Either way seems to work..

                   Q1            Q2
0-*-R1R1---*----*     *--------*     *----*--0
  |        |     \   A          \   A     |
  | giant CCC    ------         ------    |
  | alpo  CCC      |              |       |
  |        |       |              |       |
  |       GND      |              |  bias |
  |                |              |       |
  *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
          |        |       |      |       |

         CCC      CCC     CCC    CCC     CCC giant
         CCC      CCC     CCC    CCC     CCC alpo

[George Herold]

Hi Simon, The above does look better when copied and pasted into a text editor...
I can copy it back, it looks the same.

I think it's wrong to make ascii art fit google.

George H.

copy- paste-copy- is pasted below.

[Simon S Aysdie]

On Tuesday, February 2, 2021 at 5:55:50 PM UTC-8, George Herold wrote:
> I think it's wrong to make ascii art fit google.

hah hah. I agree with your principle. God Google doesn't care about our principles any more than our spaces.

[upsid...@downunder.com]

On Tue, 2 Feb 2021 17:46:11 -0800 (PST), Simon S Aysdie
<gwh...@ti.com> wrote:

>
>This is a ascii schematic test... It assumes Unicode works in GG.
>
>In one case I replaced all spaces (U+0020 SPACE [SP]) with a U+00D7 MULTIPLICATION SIGN, as a dummy, that hopefully does not get stripped. In the second case I tried someone's suggestion of using a non breaking space... in case the Google Shiva does not see it as white space to be minimized.

This will cause problems for those readers using newsreaders not
supporting Unicode.

Since the file is transmitted as MIME, it is then possible to extract
it to a file and view it with Notepad on any Windows NT an later
computers.

A simple solution would be to use ordinary periods instead of spaces.

[Steve Wilson]

A better solution is to put it in LTspice. Zip the ASC and PLT files and
upload to http://tinyupload.com/index.php



--
The best designs are no accident - sw

[upsid...@downunder.com]

On Wed, 3 Feb 2021 06:11:48 -0000 (UTC), Steve Wilson <sp...@me.com>
wrote:

Which requires installing LTspice on the system in order to follow the
discussion.

[Don]

An LTspice prerequisite mostly limits your communication to a subset of
readers who already use LTspice. Worse, you only reach a subset of
LTspice users with enough gumption to actually download and unzip
multiple zip files, plural. It demands a lot from readers of ephemeral
online conversations.

The easier you make it for your readers, the more people hear you. The
best way to communicate online is to speak through a webpage hosted on
your own website.

Danke,

--
Don, KB7RPU, https://www.qsl.net/kb7rpu
There was a young lady named Bright Whose speed was far faster than light;
She set out one day In a relative way And returned on the previous night.

[Simon S Aysdie]

Periods are definitely used in some "ASCII" SCH. So, use of a period would create an escape problem. Escape problems are much less probable w/ Unicode because there are so many characters to choose from. ☺ The "×" and " " are in "extended" ASCII too, so they might work with archaic readers.

Unicode has been around long enough to rule out usage of archaic non-supportive readers. Google groups apparently supports Unicode. HTML standards accommodate Unicode to the extent needed here, as do modern browsers.

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

[...]

> I posted the ASCII at
> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt>
> .
> There's also an LTspice file there from five or so years ago,
> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierTrans.asc>
>
> Cheers
>
> Phil Hobbs

An improvement is to use a constant current source for the first stage
instead of an emitter follower. An emitter follower gives zero attenuation
at low frequencies due to the low impedance driving the increasing
impedance of the filter capacitor.

A constant current source is a high impedance, and gives good attenutation
down to low frequency. The example below gives around -28dB at 10 Hz, where
the emitter follower has to go aboe 300 Hz for the same attenuation.

The constant current source also gives a respectable -180dB attenuation
between 100 KHz and 2 MHz. The attenuation at higher frequencies depends on
the quality of the bypass capacitors, and it is probably a good idea to add
ceramics in parallel.

https://rb.gy/m4gx7e

[Steve Wilson]

What on earth are you doing messing around with electronics without using
LTspice? How do you run an ASCII file?

SPICE has a huge learning curve, I'll grant you that. But it opens your
eyes to insights about electronics that you can never get with pencil and
paper.

Many have objected to the use of LTspice. Bob Pease, Winfield Hill, and
even some of the leaders of this newsgroup. But when they learned what
LTspice could do, they gave up on the old methods and embraced the use of
LTspice completely.

There is no way to verify the validity of an ASCII circuit. You have to
build it, and have all the equipment needed to test it, or convert it to
LTspice and simulate it. It turns out the LTspice route is far simpler,
faster, and gives far more information than you could ever get on the
bench.

You can quickly determine if a design is worth spending the time building,
or if it is hopeless and should be discarded.

Or what it needs to fix it and make it a valuable addition to your
repertoire.

Once you have analyzed a circuit in LTspice, the next step is to actually
build it and see how well it works.

But there are many traps and pitfalls in bench work. You could have
miswires, inadvertent solder bridges, shorts, faulty components, crosstalk,
parasitic oscillations, poor RF grounding, and a host of other issues that
bedevil experiments.

One of the first problems to solve is how to mount the components. Most
experienced people recommend against using the solderless prototyping
boards, shown here:

https://www.circuitbasics.com/how-to-use-prototyping-boards/

https://www.analog.com/en/analog-dialogue/studentzone/studentzone-november-
2016.html

https://en.wikipedia.org/wiki/Breadboard

These boards suffer from poor connections, crosstalk, stray capacitance,
poor RF grounding, excessive inductance in the connections, unreliability,
poor layout capability, unsuitabililty for SMD components, and many other
issues. You end up spending all your time trying to solve problems that
should never exist in the first place.

Perfboard is an improvement over solderless breadboards, but suffer from
many of the same problems:

https://en.wikipedia.org/wiki/Perfboard

The next step up is dead bug and air wiring, favored by some demented
inhabitants of this newsgroup. Here, the circuit is built on a copperclad
ground plane (+1), and the ic's are glued upside-down on the copperclad.

The obvious problem is you cannot read the information on the top of the ic
that tells you what kind it is. Six months later when you have forgotten,
you cannot identify which ic is which, or how the circuit is supposed to
work.

The components are air wired using the ic leads and each other for support.

Air wiring is great for the shortest leads possible and the lowest stray
capacity to ground, but is impractical for SMD components. It is also
fragile and delicate, and the weight of a single scope probe could cause
short circuits.

Live bug prototyping is identical to dead bug, except the ic's are mounted
rightside up on the ground plane so you can read the device information
printed on the top.

Many prople including myself favor the Manhattan style of prototyping.
There are many examples on the web such as

http://www.worldofindie.co.uk/?p=900

http://www.unixnut.net/files/manart.pdf

http://www.sdmakersguild.org/the-art-of-manhattan-style-circuit-
construction/

https://hackaday.com/2016/05/04/getting-ugly-dead-bugs-and-going-to-
manhattan/

Manhattan style may give higher stray capacity and longer leads than some
other methods, which can limit its use to frequencies below 1 Ghz. But it
is a solid technique and deserves consideration in your next project.

In all these methods, LTspice can tell you not only if a circuit is worth
building in the first place, and how it is supposed to work. This is
invaluable in bench testing, where you could have any of a host of problems
discussed above trying to build the circuit in real life.

So give up on ASCII art, and join the mainstream of electronic design and
use. Load LTspice and learn to love it as so many others have done!

There are many, many articles and YouTube videos on how to use LTspice. One
place to start is the LTwiki at

http://ltwiki.org/index.php?title=Main_Page

Another very useful group is the Yahoo page in groups.io:

https://groups.io/g/LTspice

And don't forget to check out the LTspice videos on Youtube.

Finally, there is the occasional post here in SED. So keep your eyes open
for ASC files and give them a try.

[Steve Wilson]

Steve Wilson <sp...@me.com> wrote:

[...]

Once you have graduated to copperclad for the excellent ground plane, clean
it and spray with clear acrylic spray. This protects it against discoloration
and fingrprints. You can solder through the coating.

Here is an example, but you can probably find a can in any hardware store:

Krylon Spray protects clear finish

$11.99

https://www.deserres.ca/en/krylon-aerosol-acrylic-cristal-clear

Finally, do not cut the ground plane unless you have a clear idea of what
will happen. This can force ground currents to go places you do not want them
to go, and it increases the impedance between points that increases the
noise.

[Phil Hobbs]

Steve Wilson wrote:
> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
>
> [...]
>
>> I posted the ASCII at
>> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt>
>> .
>> There's also an LTspice file there from five or so years ago,
>> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierTrans.asc>
>>
>> Cheers
>>
>> Phil Hobbs
>
> An improvement is to use a constant current source for the first stage
> instead of an emitter follower. An emitter follower gives zero attenuation
> at low frequencies due to the low impedance driving the increasing
> impedance of the filter capacitor.

A constant current source has infinite impedance, which ISTM would be
quite unlikely to improve a voltage-stabilization device.

> A constant current source is a high impedance, and gives good attenutation
> down to low frequency. The example below gives around -28dB at 10 Hz, where
> the emitter follower has to go aboe 300 Hz for the same attenuation.

> The constant current source also gives a respectable -180dB attenuation
> between 100 KHz and 2 MHz. The attenuation at higher frequencies depends on
> the quality of the bypass capacitors, and it is probably a good idea to add
> ceramics in parallel.
>
> https://rb.gy/m4gx7e

Requires a sign-in.

I use cap multipliers a lot, and they work great. You can put them
inside an op amp loop with split feedback if you want better low
frequency ripple rejection--the amp can be powered off the cap
multiplier's output to avoid its crappy HF CMR screwing everything up.

In a positive switching regulator circuit, you can even use the
split-feedback trick to put the cap multiplier inside the regulator's
feedback loop. You do have to watch the sneak path via the series RC,
of course, but it's fine for light-duty use such as op amp rails.

Op amps have good CMR at LF but much less at HF, which makes cap
multipliers the natural complement.

[Phil Hobbs]

If you mean your humble servant, that's a canard. I've used simulation
routinely for years and years, and once spent a year of my life writing
one that I needed but couldn't buy. However, I use circuit simulation
almost exclusively for discrete circuitry since nearly all board-level
SPICE models suck eggs.

> There is no way to verify the validity of an ASCII circuit.

Of course there is. You don't need a simulator to discuss architecture
and topology, or to estimate how hot things will get, or figure out what
effects are going to limit its performance. What GBW and slew rate do I
need? How many bits in this digitizer? How clean do the rails need to be?

A lot of that gets done standing in front of a white board with no
computers or soldering irons in sight.

The same white board is also good for optical / mechanical / software
architecture and topology, often in the same session as the electronics.

Once you've figured out what you're going to build, you make the
tradeoffs and do the detailed designs. Some of that will need to be
simulated, and usually some bits breadboarded as well.

> You have to
> build it, and have all the equipment needed to test it, or convert it to
> LTspice and simulate it. It turns out the LTspice route is far simpler,
> faster, and gives far more information than you could ever get on the
> bench.

As Kipling's shipwrecked mariner said to the Whale, "Not so, but far
otherwise." It'll give you as many plots as you like, true, but zero
clues as to how well they match reality. Chip simulations based on
foundry models can be very good indeed, but board level ones are a mixed
bag, to put it kindly.

> You can quickly determine if a design is worth spending the time building,
> or if it is hopeless and should be discarded.

But not what to replace it with.

>
> Or what it needs to fix it and make it a valuable addition to your
> repertoire.

The simulator will not tell you that. You can think at the keyboard,
the way most of us write, but the simulator doesn't design your circuit
any more than Notepad will write your love letter.

[Phil Hobbs]

Steve Wilson wrote:
> Steve Wilson <sp...@me.com> wrote:
>
> [...]
>
> Once you have graduated to copperclad for the excellent ground plane, clean
> it and spray with clear acrylic spray. This protects it against discoloration

> and fingerprints. You can solder through the coating.

+1. You need a few strategically-placed solder blobs for probe grounds.

> Here is an example, but you can probably find a can in any hardware store:
>
> Krylon Spray protects clear finish
>
> $11.99
>
> https://www.deserres.ca/en/krylon-aerosol-acrylic-cristal-clear
>
> Finally, do not cut the ground plane unless you have a clear idea of what
> will happen. This can force ground currents to go places you do not want them
> to go, and it increases the impedance between points that increases the
> noise.

+1 again. Wow, we're up to agreeing about a quarter of the time! ;)

[John Larkin]

On Thu, 4 Feb 2021 13:17:24 -0000 (UTC), Steve Wilson <sp...@me.com>
wrote:

>Steve Wilson <sp...@me.com> wrote:
>
>[...]
>
>Once you have graduated to copperclad for the excellent ground plane, clean
>it and spray with clear acrylic spray. This protects it against discoloration
>and fingrprints. You can solder through the coating.
>
>Here is an example, but you can probably find a can in any hardware store:
>
>Krylon Spray protects clear finish
>
>$11.99
>
>https://www.deserres.ca/en/krylon-aerosol-acrylic-cristal-clear
>

Use gold plated FR4.

https://www.dropbox.com/s/opnxfnk79o5lk1s/Z466_2.JPG?raw=1

https://www.dropbox.com/s/mcf1aneghx9lepp/Z338_PCB.JPG?raw=1

https://www.dropbox.com/s/pa9mu4ehtrjei8m/Z384_1.JPG?raw=1


(and use Dropbox)

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

> Steve Wilson wrote:
>> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
>>
>> [...]
>>
>>> I posted the ASCII at
>>> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierAsciiArt.txt
>>> > . There's also an LTspice file there from five or so years ago,
>>> <https://electrooptical.net/www/sed/TwoSectionCapMultiplierTrans.asc>
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> An improvement is to use a constant current source for the first stage
>> instead of an emitter follower. An emitter follower gives zero
>> attenuation at low frequencies due to the low impedance driving the
>> increasing impedance of the filter capacitor.
>
> A constant current source has infinite impedance, which ISTM would be
> quite unlikely to improve a voltage-stabilization device.

This is not a voltage stabilization circuit. It is a ripple filter. The
purpose is identical to your cap multiplier, but the performance is greatly
improved. As I describe below, a current source into a capacitor has much
better low frequency performance than an emitter follower into the same
cap.

Of course, a real world current source does not have infinite impedance,
but a PNP transistor is good enough.

>> A constant current source is a high impedance, and gives good
>> attenutation down to low frequency. The example below gives around
>> -28dB at 10 Hz, where the emitter follower has to go aboe 300 Hz for
>> the same attenuation.
>
>> The constant current source also gives a respectable -180dB attenuation
>> between 100 KHz and 2 MHz. The attenuation at higher frequencies
>> depends on the quality of the bypass capacitors, and it is probably a
>> good idea to add ceramics in parallel.
>>
>> https://rb.gy/m4gx7e
>
> Requires a sign-in.

Sorry about that. I spent the better part of a day trying to find a
suitable file host. There are plenty, but they all have problems such as
limited file lifetime, limited downloads, strange signin, or just plain
don't work. Google Drive turned out to be the best, but I was unaware it
requires a signin. I'm still trying to get my own web site working again at
000webhost.com, but they rewrote the program and broke it. I'll try the
others and see if they are any better.

I'll post the ASC and PLT files at the end.

> I use cap multipliers a lot, and they work great. You can put them
> inside an op amp loop with split feedback if you want better low
> frequency ripple rejection--the amp can be powered off the cap
> multiplier's output to avoid its crappy HF CMR screwing everything up.

Can you post a circuit?

> In a positive switching regulator circuit, you can even use the
> split-feedback trick to put the cap multiplier inside the regulator's
> feedback loop. You do have to watch the sneak path via the series RC,
> of course, but it's fine for light-duty use such as op amp rails.

I also use rc filters in the feedback path for TL431 regulators. Works
great.

> Op amps have good CMR at LF but much less at HF, which makes cap
> multipliers the natural complement.
>
> Cheers
>
> Phil Hobbs

Here's the current source version of your cap multiplier. The PLT file is
at the end.

Version 4
SHEET 1 1352 680
WIRE 368 -224 -352 -224
WIRE 688 -224 432 -224
WIRE -400 -128 -480 -128
WIRE -352 -128 -352 -224
WIRE -352 -128 -400 -128
WIRE -304 -128 -352 -128
WIRE -240 -128 -304 -128
WIRE -112 -128 -144 -128
WIRE -32 -128 -112 -128
WIRE 160 -128 -32 -128
WIRE 256 -128 160 -128
WIRE 400 -128 352 -128
WIRE 688 -128 688 -224
WIRE 688 -128 400 -128
WIRE 720 -128 688 -128
WIRE 832 -128 720 -128
WIRE 880 -128 832 -128
WIRE 944 -128 880 -128
WIRE 160 -96 160 -128
WIRE 624 -64 592 -64
WIRE 656 -64 624 -64
WIRE 720 -64 720 -128
WIRE 832 -64 832 -128
WIRE 944 -64 944 -128
WIRE -480 -48 -480 -128
WIRE -304 -48 -304 -128
WIRE -288 -48 -304 -48
WIRE -192 -48 -192 -64
WIRE -192 -48 -224 -48
WIRE -160 -48 -192 -48
WIRE -144 -48 -160 -48
WIRE -32 -48 -32 -128
WIRE -32 -48 -64 -48
WIRE 592 -48 592 -64
WIRE 400 -32 400 -128
WIRE 544 -32 400 -32
WIRE 160 -16 160 -32
WIRE 400 16 400 -32
WIRE 416 16 400 16
WIRE 512 16 496 16
WIRE 544 16 512 16
WIRE 512 32 512 16
WIRE 592 48 592 32
WIRE 720 64 720 0
WIRE 832 64 832 16
WIRE 832 64 720 64
WIRE 944 64 944 16
WIRE 944 64 832 64
WIRE -32 80 -32 -48
WIRE 0 80 -32 80
WIRE 112 80 80 80
WIRE 144 80 112 80
WIRE 160 80 144 80
WIRE 272 80 240 80
WIRE 304 80 304 -64
WIRE 304 80 272 80
WIRE 720 80 720 64
WIRE -480 96 -480 32
WIRE 144 112 144 80
WIRE 304 112 304 80
WIRE 512 112 512 96
WIRE -480 192 -480 176
WIRE 144 192 144 176
WIRE 304 192 304 176
FLAG 304 192 0
FLAG 720 80 0
FLAG 880 -128 Vout
FLAG -400 -128 Vin
FLAG -160 -48 Q2B
FLAG 272 80 Q1B
FLAG -112 -128 Q2C
FLAG 592 48 0
FLAG 512 112 0
FLAG 624 -64 Mult
FLAG 160 -16 0
FLAG -480 192 0
FLAG 512 16 E1N
FLAG 144 192 0
FLAG 112 80 R1R2
SYMBOL res 144 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL npn 256 -64 R270
WINDOW 0 58 37 VRight 2
WINDOW 3 91 14 VRight 2
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 816 -80 R0
SYMATTR InstName R6
SYMATTR Value 500
SYMBOL current 944 -64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value 50m
SYMBOL cap 144 -96 R0
SYMATTR InstName C3
SYMATTR Value {Cf}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 288 112 R0
SYMATTR InstName C6
SYMATTR Value {Cf}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 704 -64 R0
SYMATTR InstName C7
SYMATTR Value {Cf}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 432 -240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 43 26 VTop 2
SYMATTR InstName C8
SYMATTR Value 1f
SYMBOL e 592 -64 R0
SYMATTR InstName E1
SYMATTR Value 1000
SYMBOL cap 496 32 R0
SYMATTR InstName C4
SYMATTR Value {Cf}
SYMATTR SpiceLine Rser=10m
SYMBOL res 512 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL pnp -144 -64 M270
WINDOW 0 50 53 VLeft 2
WINDOW 3 83 77 VLeft 2
SYMATTR InstName Q2
SYMATTR Value 2N3906
SYMBOL res -48 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 490
SYMBOL cap -224 -64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9
SYMATTR Value 10m
SYMBOL voltage -480 -64 R0
WINDOW 123 39 78 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 37 19 Left 2
WINDOW 3 7 114 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value PULSE(11.5 12.5 0 1u 5u 0 6u)
SYMBOL voltage -480 80 R0
WINDOW 123 -75 167 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 37 19 Left 2
WINDOW 3 -75 145 Left 2
SYMATTR InstName V4
SYMATTR Value PULSE(0.5 -0.01 0 500n 0 0n)
SYMBOL res -16 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 128 112 R0
SYMATTR InstName C1
SYMATTR Value {Cf}
SYMATTR SpiceLine Rser=10m
TEXT 224 -408 Left 2 !.param Cf 100u
TEXT -168 -328 Left 2 ;.tran 0 100u 0 10n\n.ac oct 100 0.1 1G\n.noise v
(out) v1 dec 500 1 100meg
TEXT -168 -448 Left 2 ;'5-Pole, 2-Stage Cap Multiplier PNP -28dB@10Hz
TEXT -168 -408 Left 2 !.ac oct 100 0.1 1G

[AC Analysis]
{
Npanes: 4
Active Pane: 2
{
traces: 1 {524291,0,"V(mult)"}
X: ('G',0,0.1,0,1e+009)
Y[0]: (' ',0,1e-007,20,1000)
Y[1]: (' ',0,-280,40,120)
Volts: ('µ',0,0,0,0,5e-006,5.5e-005)
Log: 1 2 0
GridStyle: 1
PltMag: 1
},
{
traces: 1 {524293,0,"V(vout)"}
X: ('G',0,0.1,0,1e+009)
Y[0]: (' ',0,1e-010,20,1)
Y[1]: (' ',0,-280,40,120)
Volts: (' ',0,0,3,10.138,0.002,10.16)
Log: 1 2 0
GridStyle: 1
PltMag: 1
PltPhi: 1 0
},
{
traces: 2 {524292,0,"V(q2c)"} {524294,0,"V(q1b)"}
X: ('G',0,0.1,0,1e+009)
Y[0]: (' ',0,1e-012,20,10)
Y[1]: (' ',0,-280,40,120)
Volts: (' ',0,0,5,10.86908,2e-005,10.86934)
Log: 1 2 0
GridStyle: 1
PltMag: 1
},
{
traces: 1 {524290,0,"V(vin)"}
X: ('G',0,0.1,0,1e+009)
Y[0]: ('m',0,0.998849369936505,0.002,1.00115195553817)
Y[1]: ('m',1,-0.001,0.0002,0.001)
Volts: (' ',0,0,1,11.5,0.1,12.5)
Log: 1 2 0
GridStyle: 1
PltMag: 1
}
}
[Transient Analysis]
{
Npanes: 4
Active Pane: 2
{
traces: 1 {524291,0,"V(mult)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: ('µ',1,6e-007,3e-007,3.6e-006)
Y[1]: (' ',0,1e+308,40,-1e+308)
Volts: ('µ',0,0,1,6e-007,3e-007,3.6e-006)
Log: 0 0 0
GridStyle: 1
PltMag: 1
PltPhi: 1 0
},
{
traces: 1 {524293,0,"V(out)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: (' ',3,9.8,0.002,9.82)
Y[1]: (' ',0,1e+308,40,-1e+308)
Volts: (' ',0,0,3,9.8,0.002,9.82)
Log: 0 0 0
GridStyle: 1
PltMag: 1
PltPhi: 1 0
},
{
traces: 1 {524292,0,"V(q2c)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: (' ',5,10.87242,2e-005,10.87268)
Y[1]: (' ',0,1e+308,20,-1e+308)
Volts: (' ',0,0,5,10.87242,2e-005,10.87268)
Log: 0 0 0
GridStyle: 1
PltMag: 1
PltPhi: 1 0
},
{
traces: 1 {524290,0,"V(vin)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: (' ',1,11.5,0.1,12.5)
Y[1]: ('m',1,1e+308,0.0002,-1e+308)
Volts: (' ',0,0,1,11.5,0.1,12.5)
Log: 0 0 0
GridStyle: 1
PltMag: 1
PltPhi: 1 0

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

> Steve Wilson wrote:
>> Steve Wilson <sp...@me.com> wrote:
>>
>> [...]
>>
>> Once you have graduated to copperclad for the excellent ground plane,
>> clean it and spray with clear acrylic spray. This protects it against
>> discoloration and fingerprints. You can solder through the coating.
>
> +1. You need a few strategically-placed solder blobs for probe grounds.

I bend a piece of wire into a U-shape with flat feet and solder them to
strategic places on the copperclad. These make excellent grounds for the
scope probe and are strong enough to survive an inadvertent fall to the
floor when accidentally stepping on the probe cable.

>> Here is an example, but you can probably find a can in any hardware
>> store:
>>
>> Krylon Spray protects clear finish
>>
>> $11.99
>>
>> https://www.deserres.ca/en/krylon-aerosol-acrylic-cristal-clear
>>
>> Finally, do not cut the ground plane unless you have a clear idea of
>> what will happen. This can force ground currents to go places you do
>> not want them to go, and it increases the impedance between points that
>> increases the noise.
>
> +1 again. Wow, we're up to agreeing about a quarter of the time! ;)

Some people, probably digitally oriented, have no compunction against
dremelling their copperclad for various reasons. We need to introduce them
to perfboard or Manhattan prototyping styles.

Multiple GHz signals are a bit of a pain. I learned from experience that
1/2" of hookup wire won't work. You need a controlled 50 ohm environment
from end to end. Fortunately there is subminiature coax available. It is
lossy, but so is RG-58, so you need to keep the runs very short.

Another option for scoping signals is a single 450 ohm resistor in series
with a coax connector such as SMD. This makes a 10:1 divider into the 50
ohm scope input and is good up to several GHz with short runs. The helical
trim adds some inductance which affects the higher frequencies, and you may
get some peaking or dips in the response.

> Cheers

> Phil Hobbs

[Steve Wilson]

Gold plating is too expensive for simple prototypes. I don't want to scare
prospective users away.

I tried to get on Dropbox but for some reason it would not accept my
Windows XP. Just about everyone else has no problem. I'm going to try
getting a web site on GoDaddy to upload files instead of using Google
Drive.

[Phil Hobbs]

> Here's the current source version of your cap multiplier. The PLT file is
> at the end.

<snip>
Thanks. I understand the source of my confusion: That's not a current
source, it's a giant gyrated capacitor (simulated inductor).

But you cheated. 10,000 uf is not going to fit in the little postage
stamp of area, and it has the same voltage sag problem as the cap
multiplier anyway, except that it loses two full Vbe drops plus what the
resistors contribute. Even those three 100uF caps cost board space and
height, like 7x7x6 mm each (some are 9 mm tall). To get adequately low
ESR for the high frequency application they'll have to be alpos.

Here's a comparison of your circuit, my circuit, and your circuit with
the same (reasonable) capacitor values as mine (10 uF ceramics or alpos
at the ends and 1 uF ceramics in the middle). Have a look at the
rejection near 1 kHz. BTW at 100 mA, mine saves a whole Vbe drop
compared with yours. (Those Rohm transistors are the bomb.)

The ceramics are a bit more expensive but are smaller in area and
nowhere near as tall. The height can matter for this application,
because it often needs to fit under a shield.

Cheers

Phil Hobbs

==================

Version 4
SHEET 1 1584 1076
WIRE -480 -800 -512 -800
WIRE -416 -800 -480 -800
WIRE -288 -800 -336 -800
WIRE -192 -800 -288 -800
WIRE 144 -800 -96 -800
WIRE 352 -800 240 -800
WIRE 608 -800 352 -800
WIRE 720 -800 608 -800
WIRE 768 -800 720 -800
WIRE 880 -800 768 -800
WIRE 880 -784 880 -800
WIRE -288 -768 -288 -800
WIRE 352 -736 352 -800
WIRE 608 -736 608 -800
WIRE 720 -736 720 -800
WIRE -288 -688 -288 -704
WIRE 880 -672 880 -704
WIRE 608 -608 608 -672
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WIRE 720 -608 608 -608
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WIRE 48 -592 32 -592
WIRE 160 -592 128 -592
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WIRE 192 -560 192 -592
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WIRE 32 -480 32 -496
WIRE 192 -480 192 -496
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WIRE -320 -352 -384 -352
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WIRE 80 -352 -112 -352
WIRE 176 -352 80 -352
WIRE 640 -352 272 -352
WIRE 752 -352 640 -352
WIRE 800 -352 752 -352
WIRE 880 -352 800 -352
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WIRE 752 -288 752 -352
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WIRE -112 -272 -144 -272
WIRE 80 -240 80 -256
WIRE 880 -224 880 -256
WIRE 640 -160 640 -224
WIRE 752 -160 752 -208
WIRE 752 -160 640 -160
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WIRE -80 -144 -112 -144
WIRE 64 -144 0 -144
WIRE 80 -144 64 -144
WIRE 224 -144 224 -288
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WIRE 640 -144 640 -160
WIRE 64 -112 64 -144
WIRE 224 -112 224 -144
WIRE 64 -32 64 -48
WIRE 224 -32 224 -48
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WIRE 688 96 368 96
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WIRE 848 96 800 96
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WIRE 624 160 592 160
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WIRE -224 176 -224 160
WIRE -224 176 -256 176
WIRE -192 176 -224 176
WIRE -176 176 -192 176
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WIRE -64 176 -96 176
WIRE 560 176 560 160
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WIRE 512 192 368 192
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WIRE 928 224 928 192
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WIRE 512 240 480 240
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WIRE 688 288 688 224
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WIRE 800 288 688 288
WIRE -64 304 -64 176
WIRE -32 304 -64 304
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FLAG 272 416 0
FLAG 688 304 0
FLAG -432 96 Vin
FLAG -192 176 Q2B
FLAG 240 304 Q1B
FLAG -144 96 Q2C
FLAG 560 272 0
FLAG 480 336 0
FLAG 592 160 Mult
FLAG 128 208 0
FLAG -512 416 0
FLAG 480 240 E1N
FLAG 112 416 0
FLAG 80 304 R1R2
FLAG 928 224 0
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FLAG 608 -592 0
FLAG 768 -800 Vout
FLAG -512 -800 Vin
FLAG 160 -592 Q3B
FLAG 32 -480 0
FLAG 880 -672 0
FLAG -144 -480 0
FLAG -176 -592 Q4B
FLAG -288 -688 0
FLAG -304 -480 0
FLAG 848 96 Vfilt
FLAG 224 -32 0
FLAG 640 -144 0
FLAG -480 -352 Vin
FLAG 80 -240 0
FLAG 64 -32 0
FLAG 880 -224 0
FLAG 800 -352 Vfilt2
SYMBOL res 112 320 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 1k

SYMBOL npn 224 160 R270

WINDOW 0 58 37 VRight 2
WINDOW 3 91 14 VRight 2
SYMATTR InstName Q1
SYMATTR Value 2N3904

SYMBOL res 784 144 R0

SYMATTR InstName R6
SYMATTR Value 500

SYMBOL cap 112 128 R0
SYMATTR InstName C3
SYMATTR Value {Calpo}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 256 336 R0
SYMATTR InstName C6
SYMATTR Value 100u
SYMATTR SpiceLine Rser=10m
SYMBOL cap 672 160 R0
SYMATTR InstName C7
SYMATTR Value 100u
SYMATTR SpiceLine Rser=10m
SYMBOL e 560 160 R0

SYMATTR InstName E1
SYMATTR Value 1000

SYMBOL cap 464 256 R0
SYMATTR InstName C4
SYMATTR Value 100u
SYMATTR SpiceLine Rser=10m
SYMBOL res 480 224 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100k

SYMBOL pnp -176 160 M270

WINDOW 0 50 53 VLeft 2

WINDOW 3 105 101 VLeft 2

SYMATTR InstName Q2
SYMATTR Value 2N3906

SYMBOL res -80 160 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 490

SYMBOL cap -256 160 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9

SYMATTR Value 10000u
SYMBOL voltage -512 160 R0
WINDOW 123 42 102 Left 2

WINDOW 39 0 0 Left 2
WINDOW 0 37 19 Left 2

WINDOW 3 23 137 Left 2

SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value PULSE(11.5 12.5 0 1u 5u 0 6u)

SYMBOL voltage -512 304 R0

WINDOW 123 -75 167 Left 2
WINDOW 39 0 0 Left 2

WINDOW 0 55 77 Left 2

WINDOW 3 -75 145 Left 2
SYMATTR InstName V4
SYMATTR Value PULSE(0.5 -0.01 0 500n 0 0n)

SYMBOL res -48 320 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k

SYMBOL cap 96 336 R0
SYMATTR InstName C1
SYMATTR Value 100u
SYMATTR SpiceLine Rser=10m
SYMBOL npn 144 -736 R270

WINDOW 0 58 37 VRight 2
WINDOW 3 91 14 VRight 2

SYMATTR InstName Q3
SYMATTR Value 2SD2114K
SYMBOL res 704 -752 R0
SYMATTR InstName R7
SYMATTR Value 500
SYMBOL cap 592 -736 R0
WINDOW 0 -80 33 Left 2
WINDOW 3 -103 72 Left 2
SYMATTR InstName C10
SYMATTR Value {Calpo}
SYMATTR SpiceLine Rser=10m
SYMBOL current 880 -784 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -397 -67 Left 2
SYMATTR InstName I1
SYMATTR Value PULSE(100m 150m 1m 50n 50n 50m)
SYMBOL res -464 -576 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R11
SYMATTR Value 2k
SYMBOL res -320 -816 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName R12
SYMATTR Value 2.5
SYMBOL cap -320 -560 R0
SYMATTR InstName C2
SYMATTR Value {Ccer}
SYMBOL cap -160 -560 R0
SYMATTR InstName C5
SYMATTR Value {Ccer}
SYMBOL cap 16 -560 R0
SYMATTR InstName C11
SYMATTR Value {Ccer}
SYMBOL cap 176 -560 R0
SYMATTR InstName C12
SYMATTR Value {Ccer}
SYMBOL res 336 -752 R0
SYMATTR InstName R8
SYMATTR Value 22k
SYMBOL cap -304 -768 R0
SYMATTR InstName C13
SYMATTR Value {Calpo}
SYMATTR SpiceLine Rser=10m
SYMBOL npn -192 -736 R270

WINDOW 0 58 37 VRight 2
WINDOW 3 91 14 VRight 2

SYMATTR InstName Q4
SYMATTR Value 2SD2114K
SYMBOL res -304 -576 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R4
SYMATTR Value 2k
SYMBOL res -128 -576 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R9
SYMATTR Value 2k
SYMBOL res 32 -576 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R10
SYMATTR Value 2k
SYMBOL res 64 -128 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R13
SYMATTR Value 1k
SYMBOL npn 176 -288 R270

WINDOW 0 58 37 VRight 2
WINDOW 3 91 14 VRight 2

SYMATTR InstName Q5
SYMATTR Value 2N3904
SYMBOL res 736 -304 R0
SYMATTR InstName R14
SYMATTR Value 500
SYMBOL cap 64 -320 R0
SYMATTR InstName C8
SYMATTR Value {Calpo}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 208 -112 R0
SYMATTR InstName C14
SYMATTR Value {Ccer}
SYMATTR SpiceLine Rser=10m
SYMBOL cap 624 -288 R0
SYMATTR InstName C15
SYMATTR Value {Calpo}
SYMATTR SpiceLine Rser=10m
SYMBOL pnp -224 -288 M270

WINDOW 0 50 53 VLeft 2
WINDOW 3 83 77 VLeft 2

SYMATTR InstName Q6
SYMATTR Value 2N3906
SYMBOL res -128 -288 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName R16
SYMATTR Value 490
SYMBOL cap -304 -288 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2

SYMATTR InstName C17
SYMATTR Value {Calpo}
SYMBOL res -96 -128 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2

SYMATTR InstName R17
SYMATTR Value 1k
SYMBOL cap 48 -112 R0
SYMATTR InstName C18
SYMATTR Value {Ccer}
SYMATTR SpiceLine Rser=10m
SYMBOL current 880 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -397 -67 Left 2
SYMATTR InstName I2
SYMATTR Value PULSE(100m 150m 1m 50n 50n 50m)
SYMBOL current 928 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -397 -67 Left 2
SYMATTR InstName I3
SYMATTR Value PULSE(100m 150m 1m 50n 50n 50m)
TEXT -280 -1000 Left 2 !; SIMULATION COMMAND\n;.tran 0 100m \n.ac dec
500 1 1G\n;.noise v (out) v1 dec 500 1 100meg
TEXT -360 240 Left 2 ;10,000 uF!
TEXT 408 -952 Left 2 !; CMULT PARAMS\n.param Ccer 1u\n.param Calpo 10u
TEXT 2392 -1664 Invisible 2 !* Superbeta NPN good to 500 mA but only
12V\n* Q2SD2114K NPN BJT model\n* Date: 2006/12/06\n.MODEL 2SD2114K
NPN(\n+ IS=1.5000E-12\n+ BF=1.0520E3\n+ VAF=36.700\n+ IKF=3.2468\n+
ISE=1.5000E-12\n+ NE=2.3002\n+ BR=52.730\n+ VAR=100\n+ IKR=.37406\n+
ISC=1.7779E-12\n+ NC=2.1499\n+ NK=.96651\n+ RE=.1\n+ RB=2.7608\n+
RC=.17064\n+ CJE=51.912E-12\n+ MJE=.39966\n+ CJC=22.112E-12\n+
MJC=.38184\n+ TF=384.39E-12\n+ XTF=23.667\n+ VTF=33.125\n+ ITF=5.0910\n+
TR=6.2144E-9\n+ XTB=1.5000)
TEXT -408 -208 Left 2 ;10,000 uF!

[Phil Hobbs]

Whoops, there goes our average. ;) Dead bug all the way for me. If
it's something I'm likely to use again, I build it into the lid of a
cast-aluminum stomp box and put a folded-up paper schematic inside.

Live-bug weakens the leads so badly that you can't reef on them the way
you can when they're intact. A DIP8 gives you eight nice sturdy
standoffs for free, as long as you don't weaken them like that.

Of course it's increasingly a moot point--the sorts of parts that need
protos don't come in DIP anymore, so it's breakout boards stuck to
Cu-clad with foam double-sticky tape. Those are all live-bug.

My dead-bug things are mostly testers or other small instruments these days.

Manhattan is _way_ too slow by comparison with dead-bug, and all those
FR4-copper capacitors are unnecessary when you have the aforementioned
free standoffs.

Perf board is also very slow, but in addition it's super flaky--almost
as bad as a white proto board.

Cheers

Phil Hobbs

>
> Multiple GHz signals are a bit of a pain. I learned from experience that
> 1/2" of hookup wire won't work. You need a controlled 50 ohm environment
> from end to end. Fortunately there is subminiature coax available. It is
> lossy, but so is RG-58, so you need to keep the runs very short.
>
> Another option for scoping signals is a single 450 ohm resistor in series
> with a coax connector such as SMD. This makes a 10:1 divider into the 50
> ohm scope input and is good up to several GHz with short runs. The helical
> trim adds some inductance which affects the higher frequencies, and you may
> get some peaking or dips in the response.
>
>> Cheers
>
>> Phil Hobbs
>
>
>
>
>


--

[Steve Wilson]

I was not even thinking of you.

>> There is no way to verify the validity of an ASCII circuit.
>
> Of course there is. You don't need a simulator to discuss architecture
> and topology, or to estimate how hot things will get, or figure out what
> effects are going to limit its performance. What GBW and slew rate do I
> need? How many bits in this digitizer? How clean do the rails need to
> be?

That has nothing to do with ASCII art. An ASCII circuit proposes specific
components arranged in a specific configuration. You have no way to tell if
it is accurate, or if it will even work. You need to simulate it or make a
breadboard. Simulation is faster and gives much more information.

> A lot of that gets done standing in front of a white board with no
> computers or soldering irons in sight.
>
> The same white board is also good for optical / mechanical / software
> architecture and topology, often in the same session as the electronics.
>
> Once you've figured out what you're going to build, you make the
> tradeoffs and do the detailed designs. Some of that will need to be
> simulated, and usually some bits breadboarded as well.

So you agree. ASCII circuits are very limited.

>> You have to
>> build it, and have all the equipment needed to test it, or convert it
>> to LTspice and simulate it. It turns out the LTspice route is far
>> simpler, faster, and gives far more information than you could ever get
>> on the bench.

[...]

>> You can quickly determine if a design is worth spending the time
>> building, or if it is hopeless and should be discarded.
>
> But not what to replace it with.
>
>>
>> Or what it needs to fix it and make it a valuable addition to your
>> repertoire.
>
> The simulator will not tell you that. You can think at the keyboard,
> the way most of us write, but the simulator doesn't design your circuit
> any more than Notepad will write your love letter.

I don't see your point. It takes skill and experience to work in
electronics. We have tools such as calculators, finite element analysis
programs, simple ohms law for basic calculations, Matlab, google for
searching for different approaches, various programming languages such as
Python, C, Basic, and many others, and simulators.

But you have to have the skills, experience, and creativity to know how to
fix problems, and how to use simulation to show a solution works.

As far as using ASCII art, you showed the general configuraton of your
ripple filter in ASCII, then followed up with the LTspice ASC file for the
actual simulation.

My point is to simply skip the ASCII art, which does little, and go
directly to LTspice.

> Cheers
>
> Phil Hobbs

[Joe Gwinn]

On Thu, 4 Feb 2021 20:59:47 -0000 (UTC), Steve Wilson <sp...@me.com>

It wanted me to address it in what appears to be Czech. This has
happened to me before.

Joe Gwinn

[DecadentLinux...@decadence.org]

Joe Gwinn <joeg...@comcast.net> wrote in
news:p92p1gliav0asrj3t...@4ax.com:

snip
Sorry for that, Joe.
>

My answer... Among other things... PARD.

[John Larkin]

On Thu, 4 Feb 2021 22:35:56 -0000 (UTC), Steve Wilson <sp...@me.com>

wrote:

>John Larkin <jlarkin@highland_atwork_technology.com> wrote:
>
>> On Thu, 4 Feb 2021 13:17:24 -0000 (UTC), Steve Wilson <sp...@me.com>
>> wrote:
>>
>>>Steve Wilson <sp...@me.com> wrote:
>>>
>>>[...]
>>>
>>>Once you have graduated to copperclad for the excellent ground plane,
>>>clean it and spray with clear acrylic spray. This protects it against
>>>discoloration and fingrprints. You can solder through the coating.
>>>
>>>Here is an example, but you can probably find a can in any hardware
>>>store:
>>>
>>>Krylon Spray protects clear finish
>>>
>>>$11.99
>>>
>>>https://www.deserres.ca/en/krylon-aerosol-acrylic-cristal-clear
>>>
>>
>> Use gold plated FR4.
>>
>> https://www.dropbox.com/s/opnxfnk79o5lk1s/Z466_2.JPG?raw=1
>>
>> https://www.dropbox.com/s/mcf1aneghx9lepp/Z338_PCB.JPG?raw=1
>>
>> https://www.dropbox.com/s/pa9mu4ehtrjei8m/Z384_1.JPG?raw=1
>>
>>
>> (and use Dropbox)
>
>Gold plating is too expensive for simple prototypes. I don't want to scare
>prospective users away.

Every year or two, I have one of our PCB suppliers make me a couple of
square feet of ENIG plated FR4. I then shear that up as needed. It's
about $100 a square foot, which is trivial when making small
prototypes.

[Phil Hobbs]

Which of the other regulars started out as a SPICE skeptic? I can't
think of any. JL started simulating circuits on a PDP-11 or a Marchand
calculator or an abacus or something.

[John Larkin]

On Thu, 4 Feb 2021 08:54:40 -0000 (UTC), Steve Wilson <sp...@me.com>

I can stand behind someone and show them how to draw and run LT Spice
circuits in ten minutes. Some advanced things are tough, but basic
circuits, using the standard parts, are simple to enter and run.

They have to understand a little electronics first, of course.

The one about 1/4 of the way down, with the thre SMBs and the two blue
inductors, is one of mine. Uncredited!

[John Larkin]

On Thu, 4 Feb 2021 21:34:22 -0000 (UTC), Steve Wilson <sp...@me.com>
wrote:

>Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
>
>> Steve Wilson wrote:
>>> Steve Wilson <sp...@me.com> wrote:
>>>
>>> [...]
>>>
>>> Once you have graduated to copperclad for the excellent ground plane,
>>> clean it and spray with clear acrylic spray. This protects it against
>>> discoloration and fingerprints. You can solder through the coating.
>>
>> +1. You need a few strategically-placed solder blobs for probe grounds.
>
>I bend a piece of wire into a U-shape with flat feet and solder them to
>strategic places on the copperclad. These make excellent grounds for the
>scope probe and are strong enough to survive an inadvertent fall to the
>floor when accidentally stepping on the probe cable.

I use 2-56 screws and nuts, coming up from below. They are easy to
clip onto, bring grounds up to topside copper, and look nice.

https://www.dropbox.com/s/aknsdj4lhgdts2k/Z424B_bench.jpg?dl=0

They make nice power connectors too.

https://www.dropbox.com/s/6pyrjb9avf2m2zn/Z476_Bench.jpg?dl=0

[Phil Hobbs]

Having poked it for a bit, I think that yours (SW's) is actually an
interesting circuit topology. The gyrated capacitor is a two-terminal
device, so you can flip it around and use an NPN. That way you can bias
the second transistor from the base of the gyrator and save that extra
Vbe drop. With a couple of 2SD2114Ks replacing the 3N3904s, the
performance of the 10 uF/1 uF version becomes pretty comparable to mine,
and takes fewer parts. There's still a space tradeoff because one of
them is an extra 10 uF alpo vs. 2k+1uF.

For SMPS-taming, you can even go to 0.1 uF and 1 uF instead, and still
get a spherical-cow rejection number of 160 dB at 1-2 MHz where the
switcher runs. The main limitation at high frequency is the sneak path
through the two transistors.

Cheers

Phil Hobbs

[DecadentLinux...@decadence.org]

John Larkin <jlarkin@highland_atwork_technology.com> wrote in
news:kp5p1gdf1a313p8vu...@4ax.com:

>>Gold plating is too expensive for simple prototypes. I don't want
>>to scare prospective users away.
>
> Every year or two, I have one of our PCB suppliers make me a
> couple of square feet of ENIG plated FR4. I then shear that up as
> needed. It's about $100 a square foot, which is trivial when
> making small prototypes.
>
>

Baloney. A Gold plated (ENIG) 4 layer circuit proto even on a one
week turn is pretty cheap. The competition in that 'proto' realm is
high, and the going price is pretty low.

[DecadentLinux...@decadence.org]

John Larkin <jlarkin@highland_atwork_technology.com> wrote in

news:k37p1glq3sbhqksvc...@4ax.com:

> They make nice power connectors too.
>

So do COPPER STUDS with a knurl (or not) near the head to bite into
the PTH with. Depends on the Amperage one supposes.

Oh yeah... That's right.. you think I do not know any electronics.

I guess you think I think PTH means Putz Top Homo.

[Simon S Aysdie]

On Thursday, February 4, 2021 at 2:49:12 PM UTC-8, Phil Hobbs wrote:
> ...

> TEXT -280 -1000 Left 2 !; SIMULATION COMMAND\n;.tran 0 100m \n.ac dec
> 500 1 1G\n;.noise v (out) v1 dec 500 1 100meg
> TEXT -360 240 Left 2 ;10,000 uF!
> TEXT 408 -952 Left 2 !; CMULT PARAMS\n.param Ccer 1u\n.param Calpo 10u
> TEXT 2392 -1664 Invisible 2 !* Superbeta NPN good to 500 mA but only
> 12V\n* Q2SD2114K NPN BJT model\n* Date: 2006/12/06\n.MODEL 2SD2114K
> NPN(\n+ IS=1.5000E-12\n+ BF=1.0520E3\n+ VAF=36.700\n+ IKF=3.2468\n+
> ISE=1.5000E-12\n+ NE=2.3002\n+ BR=52.730\n+ VAR=100\n+ IKR=.37406\n+
> ISC=1.7779E-12\n+ NC=2.1499\n+ NK=.96651\n+ RE=.1\n+ RB=2.7608\n+
> RC=.17064\n+ CJE=51.912E-12\n+ MJE=.39966\n+ CJC=22.112E-12\n+
> MJC=.38184\n+ TF=384.39E-12\n+ XTF=23.667\n+ VTF=33.125\n+ ITF=5.0910\n+
> TR=6.2144E-9\n+ XTB=1.5000)
> TEXT -408 -208 Left 2 ;10,000 uF!

Google messed up that text too by replacing a space with a new line char. I could not read it into LTspice w/o patching it up.

Testing wrap w/ spaces replaced with a dummy char:

[Simon S Aysdie]

It worked. GG did not break the line that had no spaces.

[Phil Hobbs]

Yeah, line wraps are a problem. Some Usenet providers accept
attachments, in which case Windows users can just double click and
launch LTspice.

Cheers

Phil Hobbs

[Clifford Heath]

On 5/2/21 12:58 pm, DecadentLinux...@decadence.org wrote:
> John Larkin <jlarkin@highland_atwork_technology.com> wrote in
> news:kp5p1gdf1a313p8vu...@4ax.com:
>
>>> Gold plating is too expensive for simple prototypes. I don't want
>>> to scare prospective users away.
>>
>> Every year or two, I have one of our PCB suppliers make me a
>> couple of square feet of ENIG plated FR4. I then shear that up as
>> needed. It's about $100 a square foot, which is trivial when
>> making small prototypes.
>>
>>
>
> Baloney. A Gold plated (ENIG) 4 layer circuit proto even on a one
> week turn is pretty cheap

It doesn't beat a ten-minute turn though, like JL gets with his Dremel.

[John S]

On 2/4/2021 7:17 AM, Steve Wilson wrote:
> Steve Wilson <sp...@me.com> wrote:
>
> [...]
>
> Once you have graduated to copperclad for the excellent ground plane, clean
> it and spray with clear acrylic spray. This protects it against discoloration
> and fingrprints. You can solder through the coating.

My personal preference is Liquid Tin instead of Krylon. YMMV.

[DecadentLinux...@decadence.org]

Clifford Heath <no....@please.net> wrote in
news:lm5TH.89291$xa.3...@fx47.iad:

Yes, but those houses I speak of will send you TEN of them exact
copies. And THAT makes for far better proto dev than chipping away
at stones trying to make copies of the same statue.

I have done both.

There are plenty of gantry mounts for dremel and x y CNC setups out
there to control those far more precisely than Jerky Johnny can.

[John S]

I use various sizes of diamond concentric drills to create circular
islands on the board rather than Manhattan construction.

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

[...]

> Having poked it for a bit, I think that yours (SW's) is actually an
> interesting circuit topology. The gyrated capacitor is a two-terminal
> device, so you can flip it around and use an NPN. That way you can bias
> the second transistor from the base of the gyrator and save that extra
> Vbe drop. With a couple of 2SD2114Ks replacing the 3N3904s, the
> performance of the 10 uF/1 uF version becomes pretty comparable to mine,
> and takes fewer parts. There's still a space tradeoff because one of
> them is an extra 10 uF alpo vs. 2k+1uF.
>
> For SMPS-taming, you can even go to 0.1 uF and 1 uF instead, and still
> get a spherical-cow rejection number of 160 dB at 1-2 MHz where the
> switcher runs. The main limitation at high frequency is the sneak path
> through the two transistors.
>
> Cheers
>
> Phil Hobbs

I cannot visualize your circuit. Can you please zip the ASC and PLT files
and upload to

https://sabercathost.com/

It will take a few seconds to register, but then you will be set for life.

If not, can you post the zip file to your web site?

Thanks

[Phil Hobbs]

Sure thing. <https://electrooptical.net/www/sed/CapMultComparison3.zip>

It'll do a good job of switcher-taming with 330 nF 0805 ($0.015@1ku) and
4.7 uF 1206 ($0.06@1ku), suitably derated for dC/dV per the
manufacturer's data.

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

> Steve Wilson wrote:
>> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

>> If not, can you post the zip file to your web site?
>>
>> Thanks
>>
>
> Sure thing. <https://electrooptical.net/www/sed/CapMultComparison3.zip>
>
> It'll do a good job of switcher-taming with 330 nF 0805 ($0.015@1ku) and
> 4.7 uF 1206 ($0.06@1ku), suitably derated for dC/dV per the
> manufacturer's data.
>
> Cheers
>
> Phil Hobbs

Thanks. That's a lot of work!

But it still has zero db attenuation at low frequencies. My goal is to get
the best attenuation as possible at low frequencies, then good attenuation
through the higher frequencies.

This is for driving a 10 MHz vcxo for use in a GPSDO (gps disciplined
oscillator.) The vco uses varactors to control the frequency, and noise and
ripple will result in FM modulation of the signal. This is one of the
reasons why GPSDOs are so noisy.

Going to a TL431 regulation improves the low frequency attenuation. This
uses the same input and output voltages and supplies the same current as
before. The TL431 gives better attenuation, regulated output voltage, and
easy adjustment to different output voltages as needed.

The TL431 model is a transistor-level circuit by Helmut, and it matches
most of the TL431 device parameters. It is far better than the other models
that are out there.

The AC gain peaks at around 0.5 Hz, and it is all downhill from there.
The output is 80 dB down at 10 Hz, -160 dB at 20 KHz, and it stays there
through the higher frequencies.

The constant current source is not much better, so this gets rid of the
10,000 uf cap you complained about.

The flicker noise from the bandgap reference might be an issue, but it is
going to be a problem to measure. You might be in a better position with
your vast horde of HP boatanchors.

Unfortunately, sabercat has introduced a 30 second delay in the download,
but this is still better than the old cut and paste.

You can download it at https://sabercathost.com/e91s/52465a00.zip

[Phil Hobbs]

Steve Wilson wrote:
> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
>
>> Steve Wilson wrote:
>>> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
>
>>> If not, can you post the zip file to your web site?
>>>
>>> Thanks
>>>
>>
>> Sure thing. <https://electrooptical.net/www/sed/CapMultComparison3.zip>
>>
>> It'll do a good job of switcher-taming with 330 nF 0805 ($0.015@1ku) and
>> 4.7 uF 1206 ($0.06@1ku), suitably derated for dC/dV per the
>> manufacturer's data.
>>
>> Cheers
>>
>> Phil Hobbs
>
> Thanks. That's a lot of work!
>
> But it still has zero db attenuation at low frequencies. My goal is to get
> the best attenuation as possible at low frequencies, then good attenuation
> through the higher frequencies.
>
> This is for driving a 10 MHz vcxo for use in a GPSDO (gps disciplined
> oscillator.) The vco uses varactors to control the frequency, and noise and
> ripple will result in FM modulation of the signal. This is one of the
> reasons why GPSDOs are so noisy.
>
> Going to a TL431 regulation improves the low frequency attenuation. This
> uses the same input and output voltages and supplies the same current as
> before. The TL431 gives better attenuation, regulated output voltage, and
> easy adjustment to different output voltages as needed.

I've occasionally split the first base resistor and hung a shunt
regulator on it. You have to use split feedback, though--resistor to
the cmult output and capacitor to the cathode of the TL431. That makes
a sneak path that trashes the ultimate rejection, so it's mostly for
light-duty use.

The TL431 is extraordinarily noisy, as well--iirc around 200 nV 1-Hz
noise in the flatband and bad 1/f. An LT1021-7 with a chopamp providing
dc feedback would be one good choice. Run the chopamp off the
reference so its kickout doesn't screw up the rejection.

>
> The TL431 model is a transistor-level circuit by Helmut, and it matches
> most of the TL431 device parameters. It is far better than the other models
> that are out there.
>
> The AC gain peaks at around 0.5 Hz, and it is all downhill from there.
> The output is 80 dB down at 10 Hz, -160 dB at 20 KHz, and it stays there
> through the higher frequencies.
>
> The constant current source is not much better, so this gets rid of the
> 10,000 uf cap you complained about.
>
> The flicker noise from the bandgap reference might be an issue, but it is
> going to be a problem to measure. You might be in a better position with
> your vast horde of HP boatanchors.

I've used the LT1021-7 in geophysical instruments, and its 1/f noise was
by far the best available at the time (2013) in normal sorts of parts.
DIY kits such as the LTZ1000 are probably better.

>
> Unfortunately, sabercat has introduced a 30 second delay in the download,
> but this is still better than the old cut and paste.
>
> You can download it at https://sabercathost.com/e91s/52465a00.zip

[Steve Wilson]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

[...]

> The TL431 is extraordinarily noisy, as well--iirc around 200 nV 1-Hz
> noise in the flatband and bad 1/f. An LT1021-7 with a chopamp providing
> dc feedback would be one good choice. Run the chopamp off the
> reference so its kickout doesn't screw up the rejection.

It depends on the vendor. The TI LT431 shows 220nv/hz at 10 Hz and 2.5V, or
440nv/hz for 5V output. It is very noisy:

https://www.ti.com/lit/ds/symlink/tl431.pdf

The lt1021-5 shows about 100nv/hz at 10Hz and 5V output, which is much
better. However the output voltage is fixed, and it requires a chopamp at
the output:

https://www.analog.com/media/en/technical-documentation/data-
sheets/1021fc.pdf

The Motorola TL431 shows about 60nv/hz at 2.5V, which is 120nv/hz for 5V
output. This puts it in the same ballpark as the lt1021:

https://datasheet.octopart.com/TL431CDG-ON-Semiconductor-datasheet-
162059.pdf

The NXP doesn't even specify noise:

https://datasheet.octopart.com/TL431QDBZR%2C215-Nexperia-datasheet-
79626427.pdf

For my money, I'd go with the Motorola TL431. It has a parabolic
temperature coefficient that is flat from 25C to 50C, which is roughly the
same category as the LTZ1000. The Motorola TL431 is $0.45 at digi-key, so
it is hard to beat for performance and noise.


[...]

> I've used the LT1021-7 in geophysical instruments, and its 1/f noise was
> by far the best available at the time (2013) in normal sorts of parts.
> DIY kits such as the LTZ1000 are probably better.
>>
>> Unfortunately, sabercat has introduced a 30 second delay in the
>> download, but this is still better than the old cut and paste.

The sabercat delay is actually 15 seconds. I moved the mouse and had to
start over.

>> You can download it at https://sabercathost.com/e91s/52465a00.zip
>
> Cheers
>
> Phil Hobbs
>
>



--

[Steve Wilson]

Steve Wilson <sp...@me.com> wrote:

> For my money, I'd go with the Motorola TL431. It has a parabolic
> temperature coefficient that is flat from 25C to 50C, which is roughly
> the same category as the LTZ1000. The Motorola TL431 is $0.45 at
> digi-key, so it is hard to beat for performance and noise.

Bandgaps are noisy. Recall the LM723, which had a buried zener and was
recognized as one of the lowest noise regulators available.

I spent considerable time looking for a zener model that included noise
without success. However, a zener has to be quieter than a bandgap.

Here is a circuit that uses a 1N751 in a variable output voltage regulator.

It has decent frequency response, -28dB at 1mHz, with a slight peak at 6 Hz,
-80dB at 120 Hz, -165dB from 100 KHz to 3 MHz, then falls from there. It
probably would be much quieter than the Motorola TL431, and uses standard
junk box quality parts.

https://sabercathost.com/e91y/524703f6.zip

[Steve Wilson]

I made a very significant improvement by moving the source for the
main capacitance multipler from Vin to the emitter of the first
stage.

The attenuation is now -26dB at 1mHz, -40dB at 10 Hz, -110dB at 120
Hz, and >-160dB from 10KHz to 3Mhz. The effect of sneak paths is
reduced by having two transistors in series, and the effect of zener
noise is reduced by bypassing with a 100 uF capacitor.

The capacitors are a new product by KEMET: Aluminum Organic Polymer,
100uF 25V, ESR=14mOhms ESL=2.5nh Dia = 6.3mm Height = 5.7mm Part #
A768EB107M1ELAE036 $0.47 Qty 1 at Mouser and Digi-Key. Both have stock.

Polymer is the way to go.

The LTspice files are at

https://sabercathost.com/ilaR/5247bd60.zip

[Simon S Aysdie]

All your zip files have viruses.

[Rick C]

On Tuesday, February 2, 2021 at 6:27:33 PM UTC-5, George Herold wrote:
> On Tuesday, February 2, 2021 at 6:08:29 PM UTC-5, Phil Hobbs wrote:
> > gray_wolf wrote:
> > > On 31/01/2021 3:59 pm, George Herold wrote:
> > >> On Saturday, January 30, 2021 at 12:59:44 PM UTC-5, Phil Hobbs wrote:
> > >>> George Herold wrote:
> > >>>> On Saturday, January 30, 2021 at 12:29:59 AM UTC-5, Phil Hobbs wrote:
> > >>> <sniiip>
> > >>>>> Q1 Q2
> > >>>>> 0-*-R1R1---*----* *--------* *----*--0
> > >>>>> | | \ A \ A |
> > >>>>> | giant CCC ------ ------ |
> > >>>>> | alpo CCC | | |
> > >>>>> | | | | |
> > >>>>> | GND | | bias |
> > >>>>> | | | |
> > >>>>> *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-*
> > >>>>> | | | | |
> > >>>>> CCC CCC CCC CCC CCCC giant
> > >>>>> CCC CCC CCC CCC CCCC alpo
> > >>>>> | | | | |
> > >>>>> GND GND GND GND GND
> > >>>>>
> > >>>>
> > >>>> Thanks Phil, Can I ask a favor? Could you send the above ascii art
> > >>>> to my email?
> > >>>> I have found it hard to de-scramble the above. Google takes out the
> > >>>> spaces....
> > >>>> I try and put them in to make the picture make sense... but...
> > >>>> Has anyone found a way to recover the ascii art in google groups?
> > >
> > > I don't know about googlegroups but I'd just copy the text, paste it
> > > in an editor and change the font to 'fixed width'. Veritable width
> > > fonts will screw ascii art to bits
> > It's worse than that. Google just strips out all the spaces after the
> > first one, so that information is actually destroyed.
> >
> > Otherwise that scrooched thing George posted would have rendered
> > properly in a real newsreader.
> Right, I cut and pasted into text editor... with hopes of recovering the pic
> by just adding leading spaces one each line...
> But no! All 'extra' spaces have been taken out.
> usernet ascii art ruined by google. If someone knew someone....
> I sent feedback saying I wanted the 'show original' option back.
> (no response from gg.)

It's not that they did away with it, but they don't properly account for newsgroups not being Google groups. So it is disabled because of inaction by the group administrator as there isn't one. Something about not having permission to view email addresses. Hell, I've not been able to get view email addresses to work for years!

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

[Rick C]

On Tuesday, February 2, 2021 at 9:01:18 PM UTC-5, Simon S Aysdie wrote:
> On Tuesday, February 2, 2021 at 5:55:50 PM UTC-8, George Herold wrote:
> > I think it's wrong to make ascii art fit google.
> hah hah. I agree with your principle. God Google doesn't care about our principles any more than our spaces.

https://www.youtube.com/watch?v=Y04MQZyh30U

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

[Simon S Aysdie]

On Friday, March 5, 2021 at 11:20:07 AM UTC-8, gnuarm.del...@gmail.com wrote:
> On Tuesday, February 2, 2021 at 9:01:18 PM UTC-5, Simon S Aysdie wrote:
> > On Tuesday, February 2, 2021 at 5:55:50 PM UTC-8, George Herold wrote:
> > > I think it's wrong to make ascii art fit google.
> > hah hah. I agree with your principle. God Google doesn't care about our principles any more than our spaces.
>
> https://www.youtube.com/watch?v=Y04MQZyh30U

very cool!

[Rick C]

Yeah, I like the line, "If you won't take care of us, won't you please, please let us be?"

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

[Steve Wilson]

Simon S Aysdie <gwh...@ti.com> wrote:

I download each zip and check it before posting.

The files are all LTspice ASC and PLT files.

Pretty hard to get a virus in a text file.




--
The best designs occur in the theta state. - sw