On Sunday, March 14, 2021 at 2:42:32 PM UTC-4, Piotr Wyderski wrote:
> Rick C wrote:
>
> > The Gowin web site lists Edge and Rutronik.
> Checked both, no luck with an on-line search. Maybe contacting someone
> there would help, you're right. Thanks!
> > Have you test driven the development software yet?
> No, I am still at the chip selection phase. The requirement is a
> small-non BGA package with about 30 IOs (which excludes TQFP), which
> narrows down the choice to QFN48.
TQFP is excluded because of the physical dimension? Just too big?
> This basically leaves 3 viable
> options: Lattice MachOX2 640HC, ICE40UP5K and GW1N. About the same price
> in low volume, the 640 and the GOWIN are capable of running from a 3.3V
> directly, which is a big advantage. The FPGA can be SRAM-based; I am not
> going to use the built-in flash.
What about the iCE40 Ultra and UltraPlus which come in the same 48 pin QFN?
Lattice has a very useful selection guide.
> Lattice Diamond is a big PITA, too; I got used to the quality of Quartus.
I don't know why people rag on the vendor tool. I don't spend much time with it. I do most of my work in the editor and simulator. Lattice used to provide Active HDL from Aldec, but now it's Modelsim which I understand is a bit more clumsy for some things. I was working with someone who said he couldn't view the state of variables until he was running the code for that unit. AHDL lets you throw the up on the waveform display as soon as you start the simulation.
> And it turns out that 13 years is not enough to implement decent support
> for VHDL-2008 in LSE, Synplify and Modelsim at the same time.
With Gowin you won't care so much about Synplify I think. Gowin has it's own synthesis tool, but I suppose you can buy the Synopsis tool. For simulation you are on your own. I'm working in the AHDL with the Lattice tools.
It's funny sometimes. There's someone who doesn't like every tool. Lots of folks rag on Xilinx and even Altera tools.
> The
> documentation sucks even more, so I don't know if the Gowin's can be any
> worse.
They are, believe me. Trying to use their math blocks I finally had to reverse engineer the simulation code to see how it works. Rather complex too with all the generics for the variations. Eventually I was able to distill it down to something I could understand.
> I would rather use a Xilinx or Altera/Intel part, but they seem
> not to care about the low-end applications anymore, where the only fast
> part required is a differential Manchester multidrop LVDS link. All the
> rest is a boring CIC decimator, an I2C master and so on. It is basically
> MCU-like stuff, but the only FRAM-based MCUs are the MSP430s, which are
> way too slow for a 50Mbps low-latency link. This is the only reason for
> an FPGA here.
Yep, they go after the real money. X and A have no interest in becoming a Microchip type company selling a bazillion different small parts with low margin. I think there is a market for that. FPGAs are fast enough now that many apps can be implemented on the slowest chips without even thinking about it. The high end will always create demand, but that doesn't mean there isn't also significant demand at the low end. I've read a lot about Anlogic as well, but they don't seem to support English as well as Gowin does. Some of the Anlogic data sheets are only in Chinese.
Keep in touch. If you get to using the programming tools before we do I'd like to hear your results. We are skipping the cable thing and are putting the FTDI chip on our prototype boards. Then we don't have to worry with who has programming cables and who doesn't. The people on this project are scattered around the globe.
--
Rick C.
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