Is there something wrong with PMOS model in the LTSpice XVII?

[LM]

The Generic PMOS fet does not conduct when I tried it. When I tried a
some specific fet it worked. The supply voltage is large in case the
fet is lazy, but no, the problem seems to be in the model.

I wanted to play with a circuit from an old Application note. I
replaced PNP power Bipolar with a fet. It did not work with plain
PMOS.

Here is the circuit, if you want to know. It is AN10739 from NXP. The
fet is drawn a bit untidily. I tried to reverse it, in case I had made
a mistake there. (Models do not break when you connect them wrong way.
:).

Version 4
SHEET 1 1032 680
WIRE 160 -272 48 -272
WIRE 304 -272 160 -272
WIRE 544 -272 304 -272
WIRE 544 -240 544 -272
WIRE 576 -160 544 -160
WIRE 304 -144 304 -272
WIRE 464 -96 368 -96
WIRE 576 -96 576 -160
WIRE 576 -96 544 -96
WIRE 720 -96 576 -96
WIRE 160 -64 160 -272
WIRE 688 -16 624 -16
WIRE 720 -16 720 -96
WIRE 800 -16 720 -16
WIRE 688 0 688 -16
WIRE 160 16 112 16
WIRE 304 16 304 -48
WIRE 304 16 256 16
WIRE 576 16 304 16
WIRE 576 80 576 16
WIRE 640 80 576 80
WIRE 800 96 800 -16
WIRE 800 96 688 96
WIRE 48 112 48 -272
WIRE 256 112 256 16
WIRE 432 112 384 112
WIRE 528 112 432 112
WIRE 528 128 528 112
WIRE 624 128 624 -16
WIRE 624 128 528 128
WIRE 112 160 112 16
WIRE 192 160 176 160
WIRE 432 160 432 112
WIRE 528 224 528 128
WIRE 608 224 528 224
WIRE 768 224 688 224
WIRE 864 224 768 224
WIRE 864 240 864 224
WIRE 256 288 256 208
WIRE 768 320 768 224
WIRE 864 352 864 304
WIRE 112 400 112 160
WIRE 384 400 384 112
WIRE 384 400 112 400
WIRE 48 448 48 192
WIRE 256 448 256 368
WIRE 256 448 48 448
WIRE 432 448 432 224
WIRE 432 448 256 448
WIRE 768 448 768 384
WIRE 768 448 432 448
WIRE 864 448 864 416
WIRE 864 448 768 448
WIRE 432 480 432 448
FLAG 432 480 0
SYMBOL voltage 48 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL npn 192 112 R0
SYMATTR InstName Q1
SYMBOL pnp 368 -48 R180
SYMATTR InstName Q2
SYMBOL ind 704 208 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 22µ
SYMBOL res 528 -256 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL res 560 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL diode 448 224 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL diode 848 240 R0
SYMATTR InstName D2
SYMBOL diode 848 352 R0
SYMATTR InstName D3
SYMBOL res 240 272 R0
SYMATTR InstName R3
SYMATTR Value 200
SYMBOL res 144 -80 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 752 320 R0
SYMATTR InstName C1
SYMATTR Value 300µ
SYMBOL diode 112 176 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D4
SYMBOL pmos 640 0 R0
SYMATTR InstName M1
TEXT 16 456 Left 2 !.tran 0 300m 0
TEXT 736 -88 Left 2 !;op 0 300m 0

[Jim Thompson]

On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:

>The Generic PMOS fet does not conduct when I tried it. When I tried a
>some specific fet it worked. The supply voltage is large in case the
>fet is lazy, but no, the problem seems to be in the model.

As you say, "When I tried a some [sic erat scriptum] specific fet it
worked."

You've answered your own question.

LTspice is notorious for having LTspice-specific models tweaked with
special effects to make LTspice look super speedy.

I'd do two things, avoid LTspice-specific models and be sure to set
solver to "Alternate".

Make that _three_ things... treat LTspice XVII with caution until it
is completely debugged.

Did you try your circuit on LTspice IV?

>
>I wanted to play with a circuit from an old Application note. I
>replaced PNP power Bipolar with a fet. It did not work with plain
>PMOS.
>
>Here is the circuit, if you want to know. It is AN10739 from NXP. The
>fet is drawn a bit untidily. I tried to reverse it, in case I had made
>a mistake there. (Models do not break when you connect them wrong way.
>:).
>
>Version 4
>SHEET 1 1032 680
>WIRE 160 -272 48 -272
>WIRE 304 -272 160 -272

[snip]

Complete schematic at...

Message-ID: <u1748chjnoro32hai...@4ax.com>

>TEXT 16 456 Left 2 !.tran 0 300m 0
>TEXT 736 -88 Left 2 !;op 0 300m 0

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I'm looking for work... see my website.

Thinking outside the box... producing elegant solutions.

[Jim Thompson]

On closer examination of the circuit... WHERE in the world did you get
that circuit ?:-)

I suspect _ideal_ diodes 'D' may actually be the problem... though it
looks to be a crap circuit in general.

[John Larkin]

On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:

>The Generic PMOS fet does not conduct when I tried it. When I tried a
>some specific fet it worked. The supply voltage is large in case the
>fet is lazy, but no, the problem seems to be in the model.
>
>I wanted to play with a circuit from an old Application note. I
>replaced PNP power Bipolar with a fet. It did not work with plain
>PMOS.
>
>Here is the circuit, if you want to know. It is AN10739 from NXP. The
>fet is drawn a bit untidily. I tried to reverse it, in case I had made
>a mistake there. (Models do not break when you connect them wrong way.
>:).
>

That circuit appears to have a stable state that toasts the mosfet.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[M Philbrook]

In article <iji48c1lnp1nt72fv...@4ax.com>,
jjlark...@highlandtechnology.com says...

>
> On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:
>
> >The Generic PMOS fet does not conduct when I tried it. When I tried a
> >some specific fet it worked. The supply voltage is large in case the
> >fet is lazy, but no, the problem seems to be in the model.
> >
> >I wanted to play with a circuit from an old Application note. I
> >replaced PNP power Bipolar with a fet. It did not work with plain
> >PMOS.
> >
> >Here is the circuit, if you want to know. It is AN10739 from NXP. The
> >fet is drawn a bit untidily. I tried to reverse it, in case I had made
> >a mistake there. (Models do not break when you connect them wrong way.
> >:).
> >
>
>
> That circuit appears to have a stable state that toasts the mosfet.

change L to something much larger and the circuit will oscillate.

reasons are obvious if you check out the stock values on spice defaults

Jamie

[LM]

When PMOS Source is at +20volts and Gate and Source are at zero, the
fet should conduct. Now the circuit takes 4mA. This same happens with
LTSpice IV. I have no problems with NMOS, what I can remember.

There is no problems with the simulation when I change fet with "Pick
new MOSfet".

How can I see what PMOS values are?

[Jim Thompson]

The symbol should have a model attribute... and the model should be in
one of the libraries.

BEWARE: LTspice has taken to encrypting their models, so you may not
be able to tell what the parameters are.

Oooops! Loading up your schematic... that PMOS is a so-called
break-out device... you need to fill in the parameters, otherwise it
defaults to who-knows-what... which is why it works when you "Pick
new MOSfet".

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I'm looking for work... see my website.

Thinking outside the box... elegant solutions.

[Jim Thompson]

Forget to add: Place "hand" cursor over MOSfet, right-click to set/see
parameters.

[LM]

>>
>> ...Jim Thompson
>
>Forget to add: Place "hand" cursor over MOSfet, right-click to set/see
>parameters.
>
> ...Jim Thompson

Thank you. Just that there was wery little to choose from. VDS, Rds on
and Qgate. Not for instance Vthres.

I played some more with circuit and noticed there definitely is a
stable non oscillating state. But I couuld make work with realistic
part values.

Is there a better circuit without ICs? For 2-3 1W leds and around
12V-24V. I quess there are millions of good ICs available.

[Jim Thompson]

On Sun, 22 Jan 2017 22:47:41 +0200, LM <sala...@mail.com> wrote:

>
>>>
>>> ...Jim Thompson
>>
>>Forget to add: Place "hand" cursor over MOSfet, right-click to set/see
>>parameters.
>>
>> ...Jim Thompson
>Thank you. Just that there was wery little to choose from. VDS, Rds on
>and Qgate. Not for instance Vthres.

Of course not... LTspice relies on hokey LTspice-specific models to
demonstrate/exaggerate how fast it is >:-}

>
>I played some more with circuit and noticed there definitely is a
>stable non oscillating state. But I couuld make work with realistic
>part values.
>
>Is there a better circuit without ICs? For 2-3 1W leds and around
>12V-24V. I quess there are millions of good ICs available.

[Jim Thompson]

On Sun, 22 Jan 2017 22:47:41 +0200, LM <sala...@mail.com> wrote:

>
>>>

How much current is needed by a "1W" LED?

[LM]

On Sun, 22 Jan 2017 14:36:36 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sun, 22 Jan 2017 22:47:41 +0200, LM <sala...@mail.com> wrote:
>
>>
>>>>
>>>> ...Jim Thompson
>>>
>>>Forget to add: Place "hand" cursor over MOSfet, right-click to set/see
>>>parameters.
>>>
>>> ...Jim Thompson
>>Thank you. Just that there was wery little to choose from. VDS, Rds on
>>and Qgate. Not for instance Vthres.
>>
>>I played some more with circuit and noticed there definitely is a
>>stable non oscillating state. But I couuld make work with realistic
>>part values.
>>
>>Is there a better circuit without ICs? For 2-3 1W leds and around
>>12V-24V. I quess there are millions of good ICs available.
>
>How much current is needed by a "1W" LED?
>
> ...Jim Thompson

Well, I aimed for 300mA. Max is around 1A.

[Jim Thompson]

On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:

>The Generic PMOS fet does not conduct when I tried it. When I tried a
>some specific fet it worked. The supply voltage is large in case the
>fet is lazy, but no, the problem seems to be in the model.
>
>I wanted to play with a circuit from an old Application note. I
>replaced PNP power Bipolar with a fet. It did not work with plain
>PMOS.
>
>Here is the circuit, if you want to know. It is AN10739 from NXP. The
>fet is drawn a bit untidily. I tried to reverse it, in case I had made
>a mistake there. (Models do not break when you connect them wrong way.
>:).
>
>Version 4
>SHEET 1 1032 680
>WIRE 160 -272 48 -272
>WIRE 304 -272 160 -272

[snip]

>SYMATTR InstName M1
>TEXT 16 456 Left 2 !.tran 0 300m 0
>TEXT 736 -88 Left 2 !;op 0 300m 0

Try the following. I arbitrarily picked a PMOS, and didn't spend any
time optimizing, but it's something for you to experiment with.

Version 4
SHEET 1 1208 800
WIRE 112 -272 -112 -272
WIRE 256 -272 112 -272
WIRE 576 -272 256 -272
WIRE 256 -192 256 -272
WIRE 112 -176 112 -272
WIRE 576 0 576 -272
WIRE 112 16 112 -96
WIRE 368 16 112 16
WIRE 528 16 368 16
WIRE -112 112 -112 -272
WIRE 368 112 368 16
WIRE 576 224 576 96
WIRE 576 224 496 224
WIRE 608 224 576 224

WIRE 768 224 688 224
WIRE 864 224 768 224
WIRE 864 240 864 224

WIRE 496 288 496 224
WIRE 112 304 112 16

WIRE 768 320 768 224

WIRE 256 352 256 -112
WIRE 256 352 176 352

WIRE 864 352 864 304

WIRE 256 432 256 352
WIRE 368 480 368 192
WIRE 368 480 320 480
WIRE 576 480 368 480
WIRE 864 480 864 416
WIRE 864 480 656 480
WIRE 864 528 864 480
WIRE -112 656 -112 192
WIRE 112 656 112 400
WIRE 112 656 -112 656
WIRE 256 656 256 528
WIRE 256 656 112 656
WIRE 432 656 256 656
WIRE 496 656 496 352
WIRE 496 656 432 656
WIRE 768 656 768 384
WIRE 768 656 496 656
WIRE 864 656 864 608
WIRE 864 656 768 656
WIRE 432 688 432 656
FLAG 432 688 0
SYMBOL voltage -112 96 R0

WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 20

SYMBOL npn 320 432 M0
SYMATTR InstName Q1
SYMATTR Value 2N3904

SYMBOL ind 704 208 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1

SYMATTR Value 500µ
SYMBOL res 848 512 R0
SYMATTR InstName R1
SYMATTR Value 2.7
SYMBOL res 672 464 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100

SYMBOL schottky 512 352 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1

SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode

SYMBOL diode 848 240 R0
SYMATTR InstName D2
SYMBOL diode 848 352 R0
SYMATTR InstName D3

SYMBOL res 240 -208 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 96 -192 R0
SYMATTR InstName R4
SYMATTR Value 1k

SYMBOL cap 752 320 R0
SYMATTR InstName C1
SYMATTR Value 300µ

SYMBOL pmos 528 96 M180
SYMATTR InstName M1
SYMATTR Value RSR020P05
SYMBOL npn 176 304 M0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 352 96 R0
SYMATTR InstName R5
SYMATTR Value 22k
TEXT -128 744 Left 2 !.tran 0 300m 0
TEXT -128 784 Left 2 !;op 0 300m 0

[legg]

On Sun, 22 Jan 2017 22:00:38 +0200, LM <sala...@mail.com> wrote:

Pmos requires the gate to be negative w/r to source for conduction
between source and (negative) drain.

RL

[LM]

On Sun, 22 Jan 2017 20:08:40 -0500, legg <le...@nospam.magma.ca> wrote:


>>>Jamie
>>When PMOS Source is at +20volts and Gate and Source are at zero, the
>>fet should conduct. Now the circuit takes 4mA. This same happens with
>>LTSpice IV. I have no problems with NMOS, what I can remember.
>>
>
>Pmos requires the gate to be negative w/r to source for conduction
>between source and (negative) drain.
>
>RL

A typo. Source is at +20V. Gate and DRAIN are at zero volts. The fet
should conduct.

I tried the circuit Jim Thompson sent. It worked but I noticed , when
I tried to make switching frequency higher, that it will stop
oscillating with certain values. Either L1 or C1 must be large. I
quess these kind of supplies need a Scmitt-trigger or flip flop to
switch the fet either fully conducting or fully off.

LM

[Jim Thompson]

It does have Schmitt action, observe base of Q1 and gate of M1.

Not quite sure why is needs large values. I suspect that the time
constants get forced by the required high value of current sense
resistor, so a different sensing method is in order... maybe use a
comparator, even though you said no I/C's ;-)

[LM]

I'll try it. What is perhaps happening is that I'll move from
discretes to ICs, whether I wanted it or not

Leif M

[LM]

On Sun, 22 Jan 2017 17:03:51 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

Thanks again. It worked(of course). I'll test some more to get some
idea of when it works and when not.
Leif

[legg]

On Mon, 23 Jan 2017 15:20:09 +0200, LM <sala...@mail.com> wrote:

It's easy enough to get going,with non-default model parts, and larger
L values. A PNP bipolar switch will react much more predictably with
the switched-current drive. Even so, I doubt that very high frequency
operation was anticipated.

RL

[Jim Thompson]

Thumbing thru a book, "Feedback in Analog Circuits", by long time
buddy Agustin Ochoa, Xtreme Spectrum (*) & Zarlink chip projects, I
found an example analyzing a switching regulator.

Ochoa suggests that it is best analyzed in a similar fashion to PLL
analysis, except use duty-cycle as the loop variable.

Which led me to realize that hysterical (:-) loop control is self
defeating... with regions of non-oscillation and yet no ripple
reduction.

Conclusion: Clocked works best.

(*) 7,010,056 (Spread Spectrum) System and Method for Generating Ultra
Wideband Pulses

[Steve Wilson]

LM <sala...@mail.com> wrote:

> The Generic PMOS fet does not conduct when I tried it. When I tried a
> some specific fet it worked. The supply voltage is large in case the
> fet is lazy, but no, the problem seems to be in the model.
>
> I wanted to play with a circuit from an old Application note. I
> replaced PNP power Bipolar with a fet. It did not work with plain
> PMOS.
>
> Here is the circuit, if you want to know. It is AN10739 from NXP. The
> fet is drawn a bit untidily. I tried to reverse it, in case I had made
> a mistake there. (Models do not break when you connect them wrong way.
>:).

This is a very interesting circuit. Thanks for posting.

Please ignore Larkin's claims of lockup. He FUD's any circuit he did not
make himself. There is no lockup. The circuit has only two stable states:
M1 is on, or M1 is off. This is abundantly clear from the schematic.

I made some corrections:

1. Except in rare cases, never use default components. Always select some
realistic component for that location.

2. Always name every node. If you do not, then when you add a component
during development, all the node numbers change. Good luck trying to find
what you were measuring before.

3. Never connect to the stub of a component. When you do, and you try to
move it, you will get slanted wire connections.

4. Always define the Max Timestep in .TRAN analysis. You can start with
Max Time / 1,000 and increase or decrease as desired.

5. Always check to see you are in Modified Trap mode. Gear and Trap may
give erroneous results. To check, follow

Control Panel -> SPICE -> Default Integration Method: modified trap

For more information, see

SPICE Differentiation, by Mike Engelhardt

http://preview.tinyurl.com/j4q99t7

With these changes, the circuit starts immediately. You do not have to
run 300ms to see the oscillations begin. This wastes time. 5ms is
sufficient to see the startup and break into oscillations.

The modified circuit is at

https://drive.google.com/open?id=0Bw2W6KGPX7fgaktZZE5adkVsXzg

If your server doesn't like the url, you can try

http://tinyurl.com/hzzmvmn

[Steve Wilson]

I forgot some very important suggestions:

6. Always add realistic values to capacitors and inductors. The default
series resistance for capacitors is zero ohms and zero series inductance.
This never occurs in real life and can greatly affect the results.

7. The default series resistance for inductors is 1 milliohm. This is not
realistic in most cases.

Also, the default parallel capacitance is zero. This can cause problems in
switching circuits where fast edges cause high speed damped oscillations.

8. SPICE can slow down trying to follow these edges and make the analysis
too slow to be useful. This can be a real problem in transformer-coupled
circuits that feed fast schottky diodes. Add realistic component values,
and add snubber circuits where needed to speed the analysis and give
realistic results.

9. Some schottky diode models can give very slow .TRAN results in PWM
circuits. Try another diode, or use the default diode model.

[Jim Thompson]

And set Solver = Alternate to ensure accurate results.

[John Larkin]

On Sat, 28 Jan 2017 12:41:47 GMT, Steve Wilson <n...@spam.com> wrote:

>LM <sala...@mail.com> wrote:
>
>> The Generic PMOS fet does not conduct when I tried it. When I tried a
>> some specific fet it worked. The supply voltage is large in case the
>> fet is lazy, but no, the problem seems to be in the model.
>>
>> I wanted to play with a circuit from an old Application note. I
>> replaced PNP power Bipolar with a fet. It did not work with plain
>> PMOS.
>>
>> Here is the circuit, if you want to know. It is AN10739 from NXP. The
>> fet is drawn a bit untidily. I tried to reverse it, in case I had made
>> a mistake there. (Models do not break when you connect them wrong way.
>>:).
>
>This is a very interesting circuit. Thanks for posting.
>
>Please ignore Larkin's claims of lockup. He FUD's any circuit he did not
>make himself. There is no lockup. The circuit has only two stable states:
>M1 is on, or M1 is off. This is abundantly clear from the schematic.

Exactly. M1 on is a stable state. Until something melts.

Actually, when I run it in LT Spice, it is stable, no oscillation. If
you play with diode drops and Spice settings, you can probably get it
to oscillate.

I don't trash any circuit that's not mine. But most posted and
published circuits are bad.

I don't criticize Phil's stuff, because he knows what he's doing.
Besides, he's bigger than me.

>
>I made some corrections:
>
>1. Except in rare cases, never use default components. Always select some
>realistic component for that location.
>
>2. Always name every node. If you do not, then when you add a component
>during development, all the node numbers change. Good luck trying to find
>what you were measuring before.
>
>3. Never connect to the stub of a component. When you do, and you try to
>move it, you will get slanted wire connections.
>
>4. Always define the Max Timestep in .TRAN analysis. You can start with
>Max Time / 1,000 and increase or decrease as desired.
>
>5. Always check to see you are in Modified Trap mode. Gear and Trap may
>give erroneous results. To check, follow

If you have to fiddle with Spice settings to get a circuit to
oscillate, how can you be sure it will oscillate in real life?

How do you know what "erroneous results" are?

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Jim Thompson]

On Sat, 28 Jan 2017 08:46:00 -0800, John Larkin
<jjla...@highlandtechnology.com> wrote:

[snip]

>
>If you have to fiddle with Spice settings to get a circuit to
>oscillate, how can you be sure it will oscillate in real life?
>
>How do you know what "erroneous results" are?

The default settings in LTspice are designed to emphasize _speed_.

Go to an LTspice seminar and see what Mikey brags about.

Only an amateur at Spice doesn't understand the significance of
MaxTimeStep.

[John Larkin]

On Sat, 28 Jan 2017 10:04:29 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 28 Jan 2017 08:46:00 -0800, John Larkin
><jjla...@highlandtechnology.com> wrote:
>
>[snip]
>>
>>If you have to fiddle with Spice settings to get a circuit to
>>oscillate, how can you be sure it will oscillate in real life?
>>
>>How do you know what "erroneous results" are?
>
>The default settings in LTspice are designed to emphasize _speed_.
>
>Go to an LTspice seminar and see what Mikey brags about.
>
>Only an amateur at Spice doesn't understand the significance of
>MaxTimeStep.
>
> ...Jim Thompson

The default time step in LT Spice can cause pretty big errors, or
prevent convergence.

But fiddling with Spice settings (or diode drops) until a circuit
makes you happy, may not make the production people happy.

[pcdh...@gmail.com]

>If you have to fiddle with Spice settings to get a circuit to
>oscillate, how can you be sure it will oscillate in real life?

>How do you know what "erroneous results" are?

If you give the circuit a small kick, you can reliably tell if it will start oscillating from noise. The only condition is that the kick has to be a small perturbation on the DC quiescent bias, but larger than the SPICE tolerance settings. Since the buildup is exponential, it doesn't take long.

And the Gear integrator is helpful with stiff systems (ones with widely differing eigenvalues), which otherwise require very small time steps. It does have drawbacks, e.g. it can mask oscillations.

Cheers

Phil Hobbs

[John Larkin]

On Sat, 28 Jan 2017 09:19:40 -0800 (PST), pcdh...@gmail.com wrote:

>>If you have to fiddle with Spice settings to get a circuit to
>>oscillate, how can you be sure it will oscillate in real life?
>
>>How do you know what "erroneous results" are?
>
>If you give the circuit a small kick, you can reliably tell if it will start oscillating from noise. The only condition is that the kick has to be a small perturbation on the DC quiescent bias, but larger than the SPICE tolerance settings. Since the buildup is exponential, it doesn't take long.

I was thinking about nonlinear circuits, ones that may not start or
ones that might lock up in some horrible state.

In real life, things like power supply rampup rates, or brownouts, can
do nasty things. My point was that a pleasing Spice run, especially if
fiddled and forced, doesn't mean you can manufacture a zillion of
them.

The problem then is, how can you trust Spice? I think the answer is
that you can't.

[pcdh...@gmail.com]

>>If you give the circuit a small kick, you can reliably tell if it
>>will start oscillating from noise. The only condition is that the
>>kick has to be a small perturbation on the DC quiescent bias, but
>>larger than the SPICE tolerance settings. Since the buildup is
>>exponential, it doesn't take long.

>I was thinking about nonlinear circuits, ones that may not start or
>ones that might lock up in some horrible state.

>In real life, things like power supply rampup rates, or brownouts, can
>do nasty things. My point was that a pleasing Spice run, especially if
>fiddled and forced, doesn't mean you can manufacture a zillion of
>them.

>The problem then is, how can you trust Spice? I think the answer is
>that you can't.

Agreed. For a start, very few IC models are good enough to be more than vague indicators of how real circuits behave. Op amp macromodels are especially bad. Discrete models are generally better, except that the SPICE diode is garbage, and the MESFET one is no better.

Good luck getting SPICE to predict the gate bias of a pHEMT floating negative, but it does.

*gasp*....maybe _design_ is required? Or even _measurements_? Horrors!

;)

Cheers

Phil Hobbs

[Jim Thompson]

On Sat, 28 Jan 2017 09:13:08 -0800, John Larkin

<jjla...@highlandtechnology.com> wrote:

>On Sat, 28 Jan 2017 10:04:29 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sat, 28 Jan 2017 08:46:00 -0800, John Larkin
>><jjla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>>
>>>If you have to fiddle with Spice settings to get a circuit to
>>>oscillate, how can you be sure it will oscillate in real life?
>>>
>>>How do you know what "erroneous results" are?
>>
>>The default settings in LTspice are designed to emphasize _speed_.
>>
>>Go to an LTspice seminar and see what Mikey brags about.
>>
>>Only an amateur at Spice doesn't understand the significance of
>>MaxTimeStep.
>>
>> ...Jim Thompson
>
>The default time step in LT Spice can cause pretty big errors, or
>prevent convergence.
>
>But fiddling with Spice settings (or diode drops) until a circuit
>makes you happy, may not make the production people happy.

I don't fiddle, I set LTspice "defaults" to the same as PSpice... and
PSpice _always_ matches the big expensive guys' simulations.

[Jim Thompson]

On Sat, 28 Jan 2017 10:20:19 -0800 (PST), pcdh...@gmail.com wrote:

>... For a start, very few IC models are good enough to be more than vague indicators of how real circuits behave. Op amp macromodels are especially bad. Discrete models are generally better, except that the SPICE diode is garbage, and the MESFET one is no better.

Thou speaketh of LTspice "hokey" models (*)... real Spice diode models
are generally quite good, likewise FET's.

And the foundry models I work with are excellent.

>
>Good luck getting SPICE to predict the gate bias of a pHEMT floating negative, but it does.
>
>*gasp*....maybe _design_ is required? Or even _measurements_? Horrors!
>
>;)
>
>Cheers
>
>Phil Hobbs

The default "break-out" MOSFET model in LTspice doesn't even have a
settable VTH parameter.

[pcdh...@gmail.com]

>
>>... For a start, very few IC models are good enough to be more than
>>vague indicators of how real circuits behave. Op amp macromodels are
>>especially bad. Discrete models are generally better, except that the
>>SPICE diode is garbage, and the MESFET one is no better.

>Thou speaketh of LTspice "hokey" models (*)... real Spice diode models
>are generally quite good, likewise FET's.

Dunno. Do your diode models accurately predict 1-2V overshoot in V_F due to diffusion delays? That's the main problem with LTspice's.

>And the foundry models I work with are excellent.

Probably so, at least in use cases they've thought about, because foundries live and die by their customers' ability to make working chips.  

I'd be very impressed if SPICE were able to predict the Broadcom pHEMTs spontaneously biasing their own gates negative when left open-circuited.

Cheers

Phil Hobbs

[Jim Thompson]

On Sat, 28 Jan 2017 16:42:25 -0800 (PST), pcdh...@gmail.com wrote:

>>
>>>... For a start, very few IC models are good enough to be more than
>>>vague indicators of how real circuits behave. Op amp macromodels are
>>>especially bad. Discrete models are generally better, except that the
>>>SPICE diode is garbage, and the MESFET one is no better.
>
>>Thou speaketh of LTspice "hokey" models (*)... real Spice diode models
>>are generally quite good, likewise FET's.
>
>Dunno. Do your diode models accurately predict 1-2V overshoot in V_F due to diffusion delays? That's the main problem with LTspice's.

The main problem with LTspice's diode models is that they are
idealized.

>
>>And the foundry models I work with are excellent.
>
>Probably so, at least in use cases they've thought about, because foundries live and die by their customers' ability to make working chips.

Yep.

 
>
>I'd be very impressed if SPICE were able to predict the Broadcom pHEMTs spontaneously biasing their own gates negative when left open-circuited.
>
>Cheers
>
>Phil Hobbs

To impress you all that would be required is that the pHEMT's
manufacturer produce an accurate Spice model.

There's generally nothing wrong with Spice... whatever the flavor...
IF the model is good.

[pcdh...@gmail.com]

>To impress you all that would be required is that the pHEMT's
>manufacturer produce an accurate Spice model.

>There's generally nothing wrong with Spice... whatever the flavor...
>IF the model is good.

There are two issues, I think. The first is (as you say) that the mfg needs to make good models if possible.

The second is more of a SPICE limitation: the D() facility doesn't include diffusion delays, which makes it intrinsically incapable of accounting for V_F overshoot, and the MESFET facility doesn't model real device behaviour such as the aforementioned self-biasing of pHEMTs.

The one is a modelling issue, but the second is an intrinsic limitation of the simulator.

This is not to say that it can't be patched up, just that after N years we're still waiting. (Other more expensive tools may be better, of course.)

Cheers

Phil Hobbs

[Jim Thompson]

On Sat, 28 Jan 2017 18:15:58 -0800 (PST), pcdh...@gmail.com wrote:

>>To impress you all that would be required is that the pHEMT's
>>manufacturer produce an accurate Spice model.
>
>>There's generally nothing wrong with Spice... whatever the flavor...
>>IF the model is good.
>
>There are two issues, I think. The first is (as you say) that the mfg needs to make good models if possible.
>
>The second is more of a SPICE limitation: the D() facility doesn't include diffusion delays, which makes it intrinsically incapable of accounting for V_F overshoot, and the MESFET facility doesn't model real device behaviour such as the aforementioned self-biasing of pHEMTs.

(1) Nonsense. It's quite feasible to write such a MODEL.

>
>The one is a modelling issue, but the second is an intrinsic limitation of the simulator.

(2) Nonsense. Refer to (1) above.

>
>This is not to say that it can't be patched up, just that after N years we're still waiting. (Other more expensive tools may be better, of course.)
>
>Cheers
>
>Phil Hobbs

I have multiple papers on diffusion and recovery... the problem is
they're all by PhD's... clueless about how to really model >:-}

[John Larkin]

On Sat, 28 Jan 2017 18:49:34 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 28 Jan 2017 16:42:25 -0800 (PST), pcdh...@gmail.com wrote:
>
>>>
>>>>... For a start, very few IC models are good enough to be more than
>>>>vague indicators of how real circuits behave. Op amp macromodels are
>>>>especially bad. Discrete models are generally better, except that the
>>>>SPICE diode is garbage, and the MESFET one is no better.
>>
>>>Thou speaketh of LTspice "hokey" models (*)... real Spice diode models
>>>are generally quite good, likewise FET's.
>>
>>Dunno. Do your diode models accurately predict 1-2V overshoot in V_F due to diffusion delays? That's the main problem with LTspice's.
>
>The main problem with LTspice's diode models is that they are
>idealized.
>
>>
>>>And the foundry models I work with are excellent.
>>
>>Probably so, at least in use cases they've thought about, because foundries live and die by their customers' ability to make working chips.
>
>Yep.
>  
>>
>>I'd be very impressed if SPICE were able to predict the Broadcom pHEMTs spontaneously biasing their own gates negative when left open-circuited.
>>
>>Cheers
>>
>>Phil Hobbs
>
>To impress you all that would be required is that the pHEMT's
>manufacturer produce an accurate Spice model.

That's rare for RF parts. You're lucky to get any DC specs. All you
usually get is s-params, which don't help much if you want to use them
in switching apps. The noise data is at high freqs, often just a
microwave band, with no hint of low frequency behavior. Leakage
currents? C-V curves? Substrate diode effects? As if!

Even the rare Spice model is sketchy.

Depletion parts typically enhance nicely, but there's usually no
suggestion of that on data sheets. So we test them.

[Jim Thompson]

So? Take data and write your own model.

[John Larkin]

On Sat, 28 Jan 2017 21:30:25 -0700, Jim Thompson

We usually take data and design circuits! With this picosecond stuff,
breadboarding is better than simulating anyhow.

https://dl.dropboxusercontent.com/u/53724080/Protos/Z382_1.JPG

[pcdh...@gmail.com]

>>The second is more of a SPICE limitation: the D() facility doesn't
>include diffusion delays, which makes it intrinsically incapable
>of accounting for V_F overshoot, and the MESFET facility doesn't
>model real device behaviour such as the aforementioned self-biasing of pHEMTs.

>(1) Nonsense.  It's quite feasible to write such a MODEL.
 

I've asked about SPICE modelling the forward overshoot of diodes both here and in the Yahoo LTspice group, and heard in both places that the SPICE D() facility is too stupid to model it. If you can produce a model for a 1N4148 that overshoots to 1.4 V or so on turn-on (about par for a real unit), and exhibits the same variation with dI/dt as a real one, I'll happily concede your point.

It won't be using just D(), though, that's for sure.

>>
>The one is a modelling issue, but the second is an intrinsic limitation of the simulator.

(2) Nonsense.  Refer to (1) above.

SPICE is a pretty capable solver for largish sparse systems of nonlinear OD

[pcdh...@gmail.com]

>SPICE is a pretty capable solver for largish sparse systems of nonlinear ODEs. Transient carrier diffusion is governed by a transport equation, though, which exhibits intrinsically more complex and nonlocal behaviour. That has to be put in by hand, like transmission line devices, which are also nonlocal and don't follow any ODE.

So there are actually lots of things you can't do in SPICE without hacking the actual simulator code.

Cheers

Phil Hobbs

[John Larkin]

On Sun, 29 Jan 2017 04:43:37 -0800 (PST), pcdh...@gmail.com wrote:

>>>The second is more of a SPICE limitation: the D() facility doesn't
>>include diffusion delays, which makes it intrinsically incapable
>>of accounting for V_F overshoot, and the MESFET facility doesn't
>>model real device behaviour such as the aforementioned self-biasing of pHEMTs.
>
>>(1) Nonsense.  It's quite feasible to write such a MODEL.
> 
>I've asked about SPICE modelling the forward overshoot of diodes both here and in the Yahoo LTspice group, and heard in both places that the SPICE D() facility is too stupid to model it. If you can produce a model for a 1N4148 that overshoots to 1.4 V or so on turn-on (about par for a real unit), and exhibits the same variation with dI/dt as a real one, I'll happily concede your point.

Here are a few cases of 1N914 "forward recovery"...

https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_a.JPG

https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_b.JPG

https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_c.JPG

https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_d.JPG


Although it seldom matters. I can usually work with D(...) with a
couple of parameters, or pick a diode from the standard list.
Simulating varicaps is sometimes useful.

LT Spice is great, as long as you don't turn your back on it.



waking up is "sleep recovery"

eating is "hunger recovery"

I need some coffee and a donut.

[Jim Thompson]

On Sun, 29 Jan 2017 04:43:37 -0800 (PST), pcdh...@gmail.com wrote:

>>>The second is more of a SPICE limitation: the D() facility doesn't
>>include diffusion delays, which makes it intrinsically incapable
>>of accounting for V_F overshoot, and the MESFET facility doesn't
>>model real device behaviour such as the aforementioned self-biasing of pHEMTs.
>
>>(1) Nonsense.  It's quite feasible to write such a MODEL.
> 
>I've asked about SPICE modelling the forward overshoot of diodes both here and in the Yahoo LTspice group, and heard in both places that the SPICE D() facility is too stupid to model it. If you can produce a model for a 1N4148 that overshoots to 1.4 V or so on turn-on (about par for a real unit), and exhibits the same variation with dI/dt as a real one, I'll happily concede your point.
>
>It won't be using just D(), though, that's for sure.

You're evading my point. I said it is possible to write a proper
model. It just hasn't been done (properly) yet, though I've developed
a model that's pretty close, it's not _perfect_... I strive for
perfection so I'm still playing with it as time permits ;-)

>
>>>
>>The one is a modelling issue, but the second is an intrinsic limitation of the simulator.
>
>(2) Nonsense.  Refer to (1) above.
>
>SPICE is a pretty capable solver for largish sparse systems of nonlinear OD

Yes. Pretty much as long as you can write an equation for it Spice
can solve it.

[Phil Hobbs]

On 01/29/2017 10:59 AM, Jim Thompson wrote:
> On Sun, 29 Jan 2017 04:43:37 -0800 (PST), pcdh...@gmail.com wrote:
>
>>>> The second is more of a SPICE limitation: the D() facility doesn't
>>> include diffusion delays, which makes it intrinsically incapable
>>> of accounting for V_F overshoot, and the MESFET facility doesn't
>>> model real device behaviour such as the aforementioned self-biasing of pHEMTs.
>>
>>> (1) Nonsense. It's quite feasible to write such a MODEL.
>>
>> I've asked about SPICE modelling the forward overshoot of diodes both here and in the Yahoo LTspice group, and heard in both places that the SPICE D() facility is too stupid to model it. If you can produce a model for a 1N4148 that overshoots to 1.4 V or so on turn-on (about par for a real unit), and exhibits the same variation with dI/dt as a real one, I'll happily concede your point.
>>
>> It won't be using just D(), though, that's for sure.
>
> You're evading my point. I said it is possible to write a proper
> model. It just hasn't been done (properly) yet, though I've developed
> a model that's pretty close, it's not _perfect_... I strive for
> perfection so I'm still playing with it as time permits ;-)

I'm not evading your point, I'm disagreeing with it. I claim that no
such model exists, and you appear to agree. Your faith in SPICE is
touching but provably wrong--it can't model everything without hacking
the simulator code, not merely the models.

For something whose behaviour is fairly simple and which has wide
device-to-device variations, such as a diode with diffusion overshoot,
you can probably cruft together some subcircuit model that gets vaguely
into the ballpark, maybe using the transmission line model to account
for time delays.

It sure won't be just D() with parameters, though.

>
>>
>>>>
>>> The one is a modelling issue, but the second is an intrinsic limitation of the simulator.
>>
>> (2) Nonsense. Refer to (1) above.
>>
>> SPICE is a pretty capable solver for largish sparse systems of nonlinear OD
>
> Yes. Pretty much as long as you can write an equation for it Spice
> can solve it.
>
> ...Jim Thompson
>

No. Not transport equations, as I said, and there are lots of other
examples of integral or integrodifferential equations. They're
generally not reducible to systems of ODEs, because no ODE can be
nonlocal, and so no solver limited to ODEs can handle them.

You can't even write an ODE to describe a piece of coax from a circuits
point of view--the SPICE transmission line isn't an ODE model, it's a
special case, i.e. the simulator code has to be hacked up to support it.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

[Jim Thompson]

On Sat, 28 Jan 2017 19:37:29 -0800, John Larkin
<jjla...@highlandtechnology.com> wrote:

[snip]

>
>Depletion parts typically enhance nicely, but there's usually no
>suggestion of that on data sheets. So we test them.

That's the datasheet. I'd expect a "real" Spice model (as opposed to
an LTspice-hokeyed model) to properly simulate the enhanced operation.

I just tried an Infineon BSP135_L0, and it does, though it looks like
the model doesn't model the knee very well at all... LEVEL=3 model...
in the real world we're up to model LEVEL's in the 50's ;-)

[Jim Thompson]

On Sun, 29 Jan 2017 11:19:28 -0500, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>On 01/29/2017 10:59 AM, Jim Thompson wrote:
>> On Sun, 29 Jan 2017 04:43:37 -0800 (PST), pcdh...@gmail.com wrote:
>>
>>>>> The second is more of a SPICE limitation: the D() facility doesn't
>>>> include diffusion delays, which makes it intrinsically incapable
>>>> of accounting for V_F overshoot, and the MESFET facility doesn't
>>>> model real device behaviour such as the aforementioned self-biasing of pHEMTs.
>>>
>>>> (1) Nonsense. It's quite feasible to write such a MODEL.
>>>
>>> I've asked about SPICE modelling the forward overshoot of diodes both here and in the Yahoo LTspice group, and heard in both places that the SPICE D() facility is too stupid to model it. If you can produce a model for a 1N4148 that overshoots to 1.4 V or so on turn-on (about par for a real unit), and exhibits the same variation with dI/dt as a real one, I'll happily concede your point.
>>>
>>> It won't be using just D(), though, that's for sure.
>>
>> You're evading my point. I said it is possible to write a proper
>> model. It just hasn't been done (properly) yet, though I've developed
>> a model that's pretty close, it's not _perfect_... I strive for
>> perfection so I'm still playing with it as time permits ;-)
>
>I'm not evading your point, I'm disagreeing with it. I claim that no
>such model exists, and you appear to agree. Your faith in SPICE is
>touching but provably wrong--it can't model everything without hacking
>the simulator code, not merely the models.

Baloney. There's where subcircuits come in.

>
>For something whose behaviour is fairly simple and which has wide
>device-to-device variations, such as a diode with diffusion overshoot,
>you can probably cruft together some subcircuit model that gets vaguely
>into the ballpark, maybe using the transmission line model to account
>for time delays.

Transmission line models are a disaster.

>
>It sure won't be just D() with parameters, though.

Nope. I never said it would.

>
>>
>>>
>>>>>
>>>> The one is a modelling issue, but the second is an intrinsic limitation of the simulator.
>>>
>>> (2) Nonsense. Refer to (1) above.
>>>
>>> SPICE is a pretty capable solver for largish sparse systems of nonlinear OD
>>
>> Yes. Pretty much as long as you can write an equation for it Spice
>> can solve it.
>>
>> ...Jim Thompson
>>
>
>No. Not transport equations, as I said, and there are lots of other
>examples of integral or integrodifferential equations. They're
>generally not reducible to systems of ODEs, because no ODE can be
>nonlocal, and so no solver limited to ODEs can handle them.
>
>You can't even write an ODE to describe a piece of coax from a circuits
>point of view--the SPICE transmission line isn't an ODE model, it's a
>special case, i.e. the simulator code has to be hacked up to support it.
>
>Cheers
>
>Phil Hobbs

Watch this space ;-)

[Phil Hobbs]

On 01/29/2017 10:51 AM, John Larkin wrote:
> On Sun, 29 Jan 2017 04:43:37 -0800 (PST), pcdh...@gmail.com wrote:
>
>>>> The second is more of a SPICE limitation: the D() facility
>>>> doesn't
>>> include diffusion delays, which makes it intrinsically incapable
>>> of accounting for V_F overshoot, and the MESFET facility doesn't
>>> model real device behaviour such as the aforementioned
>>> self-biasing of pHEMTs.
>>
>>> (1) Nonsense. It's quite feasible to write such a MODEL.
>>
>> I've asked about SPICE modelling the forward overshoot of diodes
>> both here and in the Yahoo LTspice group, and heard in both places
>> that the SPICE D() facility is too stupid to model it. If you can
>> produce a model for a 1N4148 that overshoots to 1.4 V or so on
>> turn-on (about par for a real unit), and exhibits the same
>> variation with dI/dt as a real one, I'll happily concede your
>> point.
>
> Here are a few cases of 1N914 "forward recovery"...
>
> https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_a.JPG
>
>
> https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_b.JPG
>
>
> https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_c.JPG
>
>
> https://dl.dropboxusercontent.com/u/53724080/Parts/Diode_TurnOn/1N914_d.JPG
>
>

Yikes.

>
> Although it seldom matters. I can usually work with D(...) with a
> couple of parameters, or pick a diode from the standard list.
> Simulating varicaps is sometimes useful.

Since Schottkys have gotten so cheap, I just use them when forward
recovery might be an issue, so I don't have to care about the stupidity
of SPICE diodes. Back in the day when they were $2, it was a harder call.

>
> LT Spice is great, as long as you don't turn your back on it.

Agreed. Simulation is not an adequate substitute for thought, though
it's often used that way.

[Jim Thompson]

Where I was back in August when I last toyed with it...

<http://www.analog-innovations.com/DeviceModelsSubckts/DiodeReverseRecoveryExperiments.png>

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Thinking outside the box... producing elegant solutions.

[John Larkin]

My commodity part is SMS7621/BAT15 in SOD323. It has around 0.25 pF
capacitance. They are safe up to at least 6 volts. We average about 20
cents each.

Schottkies don't avalanche or anything dramatic; they just leak more
as reverse voltage goes up.

[John Larkin]

If something like forward recovery looks to be a problem, use a
different part!

A good SRD model could be handy, but that can be finessed with a
charge-controlled switch or something. But I wouldn't trust a sim that
uses an SRD; that's breadboard territory.

A boy needs to solder now and then anyhow.

[Jim Thompson]

On Sun, 29 Jan 2017 10:02:10 -0800, John Larkin
<jjla...@highlandtechnology.com> wrote:

[snip].

>
>A boy needs to solder now and then anyhow.

I still have a couple of pounds of 60/40 on hand, plus a Weller WES51
station.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

[John Larkin]

On Sun, 29 Jan 2017 09:32:16 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 28 Jan 2017 19:37:29 -0800, John Larkin
><jjla...@highlandtechnology.com> wrote:
>
>
>[snip]
>>
>>Depletion parts typically enhance nicely, but there's usually no
>>suggestion of that on data sheets. So we test them.
>
>That's the datasheet. I'd expect a "real" Spice model (as opposed to
>an LTspice-hokeyed model) to properly simulate the enhanced operation.

For exotica like phemts, it's easier, and far more believable, to
breadboard a circuit, rather than spending gobs of time fiddling with
a Spice model of unknown accuracy.

I don't often need a full, accurate Spice model. If I'm switching a
phemt on or off, I just need to make a few DC measurements.

The RF boys can live with the s-params, as long as they can figure out
how to get the drain current right. Some of the data sheets say
"adjust the gate voltage for xxx mA drain current [best of luck] "

I guess that designing monolithic ICs discourages breadboarding.
Nobody makes Dremels tiny enough.

[pcdh...@gmail.com]

>I guess that designing monolithic ICs discourages breadboarding.
>Nobody makes Dremels tiny enough.

They do, actually--focused ion beam (FIB) tools. You can dig nice straight sided trenches, and put down platinum wires too.

I've only driven one once, but it was pretty cool.

You should talk your way into a tour of somebody's Failure Analysis lab--good ones have an amazing array of fun tools like that.

Cheers

Phil Hobbs

[Jim Thompson]

On Sun, 29 Jan 2017 10:14:43 -0800, John Larkin
<jjla...@highlandtechnology.com> wrote:

[snip]

>

>I guess that designing monolithic ICs discourages breadboarding.
>Nobody makes Dremels tiny enough.

I started using a simulator somewhere around 1977-1980 (Berkeley Spice
on a VAX780), but I continued to do bread-boarding until ~1990.

There used to be packages of bipolar IC devices, called "kit-parts"
(*). See "BreadBoard.jpg" on the S.E.D/Schematics Page of my website
for an example. I created that board while I was Analog Guru at
OmniComp/GenRad. I still have pieces of it that I use for G-jobs...
original size was 1' x 1' with 72 (IIRC) up to 16 pin DIL socket
locations.

(*) 4-5 devices per package, different packages for different sizes
(emitter-size scale factor)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Jim Thompson]

On Sun, 29 Jan 2017 10:25:03 -0800 (PST), pcdh...@gmail.com wrote:

>>I guess that designing monolithic ICs discourages breadboarding.
>>Nobody makes Dremels tiny enough.
>
>They do, actually--focused ion beam (FIB) tools. You can dig nice straight sided trenches, and put down platinum wires too.

I've never had to use that for repairs, but I've used it for a quicky
test of a re-wire scheme to change a chip function, before going to
the expense of a wafer run.

>
>I've only driven one once, but it was pretty cool.
>
>You should talk your way into a tour of somebody's Failure Analysis lab--good ones have an amazing array of fun tools like that.
>
>Cheers
>
>Phil Hobbs

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

I use BAT54s for medium power things, like everyone else. The sampler
I recently did used one DB2S31400L (30V, 30mA, 3pF, $0.02) to control
the gate of the S/H JFET, and one 1PS10SB82 (15V, 30mA, 1pF, $0.16) for
the actual sampler. Worked fine.

> Schottkies don't avalanche or anything dramatic; they just leak more
> as reverse voltage goes up.

Until you get to reach-through, where the bottom of the potential well
flattens out at the electrode potential.

Interdigitated Schottky photodiodes have back-to-back barriers, so you
have to bias them above reachthrough before they conduct at all. Some
APDs are like that--they don't work at zero bias.

[LM]

On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:

First, thank you for interesting discussion accuracy. I wonder how do
climate scientist test their simulations. By waiting a couple of
thousand years, I quess.

I have now bought a Pfet and 200uH coil. I couldn't find such fet
here. It is IRF5305, if somebody is interested. I chose low gate
capacitance and availability.

The latest circuit seems to work well in simulations, It doesn't
require elyt cap, which is good for reliability. I canged a couple of
parts, like the main diode.

If I yield a bit, what do you think using a comparator and a
smittrigger oscillator. Like this. Even LTspice rejects it so it is
not ready, but the idea is there.

Version 4
SHEET 1 1032 680
WIRE 48 -272 -16 -272
WIRE 208 -272 48 -272
WIRE 288 -272 208 -272
WIRE 352 -272 288 -272
WIRE 624 -272 352 -272
WIRE -16 -256 -16 -272
WIRE -16 -160 -16 -176
WIRE 48 -64 48 -272
WIRE 144 -32 128 -32
WIRE 256 -32 224 -32
WIRE 352 -32 352 -272
WIRE 624 0 624 -272
WIRE 256 16 256 -32
WIRE 304 16 256 16
WIRE 512 16 416 16
WIRE 576 16 512 16
WIRE 128 64 128 -32
WIRE 128 64 96 64
WIRE 160 64 128 64
WIRE 256 64 256 16
WIRE 256 64 224 64
WIRE 96 96 96 64
WIRE 192 96 96 96
WIRE 96 112 96 96
WIRE 352 128 352 64
WIRE 592 144 528 144
WIRE 624 144 624 96
WIRE 624 144 592 144
WIRE 48 224 48 16
WIRE 432 224 48 224
WIRE 528 224 528 144
WIRE 528 224 432 224
WIRE 608 224 528 224
WIRE 768 224 688 224
WIRE 816 224 768 224
WIRE 864 224 816 224
WIRE 864 240 864 224
WIRE 288 288 288 -272
WIRE 496 304 320 304
WIRE 192 320 192 96
WIRE 256 320 192 320
WIRE 768 320 768 224
WIRE 864 320 864 304
WIRE 144 336 144 320
WIRE 352 336 320 336
WIRE 496 336 496 304
WIRE 432 352 432 224
WIRE 864 400 864 384
WIRE 864 400 640 400
WIRE 96 448 96 176
WIRE 288 448 288 352
WIRE 288 448 96 448
WIRE 432 448 432 416
WIRE 432 448 288 448
WIRE 496 448 496 416
WIRE 496 448 432 448
WIRE 768 448 768 384
WIRE 768 448 496 448
WIRE 784 448 768 448
WIRE 864 448 864 400
WIRE 432 480 432 448
WIRE 352 528 352 336
WIRE 640 528 640 400
WIRE 640 528 352 528
FLAG 432 480 0
FLAG -16 -160 0
FLAG 512 16 M1G
FLAG 592 144 M1D
FLAG 816 224 Vout
FLAG 208 -272 Vcc
FLAG 352 128 0
SYMBOL voltage -16 -272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL ind 704 208 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 22µ
SYMBOL schottky 448 416 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS1100
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL LED 848 240 R0
SYMATTR InstName D2
SYMATTR Value XlampMX6
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL LED 848 320 R0
SYMATTR InstName D3
SYMATTR Value LXHL-BW02
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 32 -80 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 752 320 R0
SYMATTR InstName C1
SYMATTR Value 300µ
SYMBOL pmos 576 96 M180
SYMATTR InstName M1
SYMATTR Value RRS090P03
SYMBOL Digital\\schmtinv 160 0 R0
SYMATTR InstName A1
SYMBOL res 128 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL cap 80 112 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL Comparators\\LM339 288 384 R180
SYMATTR InstName U1
SYMBOL voltage 496 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 0.3
SYMBOL res 768 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL Digital\\inverter_philips 352 -48 R0
SYMATTR InstName U2
TEXT 320 -336 Left 2 !.tran 0 5m 0 10u startup
TEXT 320 -360 Left 2 ;'Buck LED Driver NXP AN10739

[Jim Thompson]

On Sun, 29 Jan 2017 21:37:03 +0200, LM <sala...@mail.com> wrote:

>On Fri, 20 Jan 2017 16:39:04 +0200, LM <sala...@mail.com> wrote:
>
>First, thank you for interesting discussion accuracy. I wonder how do
>climate scientist test their simulations. By waiting a couple of
>thousand years, I quess.
>
>I have now bought a Pfet and 200uH coil. I couldn't find such fet
>here. It is IRF5305, if somebody is interested. I chose low gate
>capacitance and availability.
>
>The latest circuit seems to work well in simulations, It doesn't
>require elyt cap, which is good for reliability. I canged a couple of
>parts, like the main diode.
>
>If I yield a bit, what do you think using a comparator and a
>smittrigger oscillator. Like this. Even LTspice rejects it so it is
>not ready, but the idea is there.
>
>Version 4
>SHEET 1 1032 680
>WIRE 48 -272 -16 -272

Full Schematic at...

Message-ID: <3hfs8c1ta083kpf3p...@4ax.com>

>TEXT 320 -336 Left 2 !.tran 0 5m 0 10u startup
>TEXT 320 -360 Left 2 ;'Buck LED Driver NXP AN10739

It comes up as missing symbols for...

LM339
inverter_philips

So please post the appropriate .asy symbols

[Jim Thompson]

On Sun, 29 Jan 2017 10:02:15 -0700, Jim Thompson

<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sun, 29 Jan 2017 09:36:46 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sun, 29 Jan 2017 11:19:28 -0500, Phil Hobbs
>><pcdhSpamM...@electrooptical.net> wrote:
>>

[snip]

>>>
>>>You can't even write an ODE to describe a piece of coax from a circuits
>>>point of view--the SPICE transmission line isn't an ODE model, it's a
>>>special case, i.e. the simulator code has to be hacked up to support it.
>>>
>>>Cheers
>>>
>>>Phil Hobbs
>>
>>Watch this space ;-)
>>
>> ...Jim Thompson
>
>Where I was back in August when I last toyed with it...
>
><http://www.analog-innovations.com/DeviceModelsSubckts/DiodeReverseRecoveryExperiments.png>
>
> ...Jim Thompson

Phil, Comments about my link?

Ain't no transmission line in my model.

Ain't no hack of simulator code.

Just using conventional subcircuit techniques.

And NO inductors.

Only thing holding me back from releasing it is that it requires
tweak-test-tweak-test... to fit the data, and I'm looking for ways to
easily parameterize it.

Got to think outside the box >:-}

[LM]

inverter_philips.asy
The + and - suplplies of the comparator may be swapped in the file I
sent.

Version 4
SymbolType CELL
LINE Normal -16 80 -16 48
LINE Normal 64 64 32 64
LINE Normal -16 80 16 64
LINE Normal -16 48 16 64
LINE Normal -16 64 -48 64
LINE Normal 0 56 0 16
LINE Normal 0 72 0 112
RECTANGLE Normal 48 96 -32 32
CIRCLE Normal 32 72 16 56
WINDOW 0 16 16 Left 0
WINDOW 3 16 112 Left 0
SYMATTR Value INVERT
SYMATTR Description Inverter gate
SYMATTR Prefix X
PIN -48 64 NONE 8
PINATTR PinName A
PINATTR SpiceOrder 1
PIN 64 64 NONE 0
PINATTR PinName Y
PINATTR SpiceOrder 2
PIN 0 16 NONE 8
PINATTR PinName VCC
PINATTR SpiceOrder 3
PIN 0 112 NONE 8
PINATTR PinName VSS
PINATTR SpiceOrder 4

lm339.asy


Version 4
SymbolType CELL
LINE Normal -32 32 32 64
LINE Normal -32 96 32 64
LINE Normal -32 32 -32 96
LINE Normal -28 48 -20 48
LINE Normal -28 80 -20 80
LINE Normal -24 84 -24 76
LINE Normal 0 32 0 48
LINE Normal 0 96 0 80
LINE Normal 4 44 12 44
LINE Normal 8 40 8 48
LINE Normal 4 84 12 84
WINDOW 0 16 32 Left 0
WINDOW 3 16 96 Left 0
SYMATTR Value LM339
SYMATTR Prefix X
SYMATTR SpiceModel LM339.sub
SYMATTR Value2 LM339
SYMATTR Description Quad Single Supply 3V/5V Comparator LM339
PIN -32 80 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 0 32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 0 96 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 32 64 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5

LM339.sub


* LM339 VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
* REV (N/A)
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | |
.SUBCKT LM339 1 2 3 4 5
*
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .75
VI2 22 2 DC .75
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
E1 10 4 9 4 1
V1 10 11 DC 0
Q5 5 11 4 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12
TR=543.8E-9)
DP 4 3 DX
RP 3 4 46.3E3
.MODEL DX D(IS=800.0E-18)
*
.ENDS

* Model for packaged LM339 devices
* 14-pin DIP, 4 comparators per package
* CONNECTIONS: Output 2
* | Output 1
* | | Positive Power Supply
* | | | Input 1 Inverting
* | | | | Input 1 Non-Inverting
* | | | | | Input 2 Inverting
* | | | | | | Input 2 Non-Inverting
* | | | | | | | Input 3 Inverting
* | | | | | | | | Input 3 Non-inverting
* | | | | | | | | | Input 4 Inverting
* | | | | | | | | | | Input 4 Non-inverting
* | | | | | | | | | | | Negative Power Supply (or
Gnd)
* | | | | | | | | | | | | Output 4
* | | | | | | | | | | | | | Output 3
* | | | | | | | | | | | | | |
.SUBCKT LM339_DIP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
X1 5 4 3 12 2 LM339
X2 7 6 3 12 1 LM339
X3 9 8 3 12 14 LM339
X4 11 10 3 12 13 LM339
.ENDS

[LM]

On Sun, 29 Jan 2017 12:56:40 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

If I build this, I will use 4093 as the oscillator and inverter. Some
open collector comparator like LM339. But where to measure the
current. I am not sure about doing it like I did it now.

[pcdh...@gmail.com]

>Phil, Comments about my link?

All I see is a screen shot.

I have a lot of respect for your expertise, Jim, but on account of your habit of teasing like that, I usually don't bother clicking on your links.

Cheers

Phil Hobbs

[Jim Thompson]

You didn't observe both forward overshoot and reverse recovery?

You're so set in your ways you go about proclaiming, "Can't be done",
thus I tease >:-}

[pcdh...@gmail.com]

>You didn't observe both forward overshoot and reverse recovery?

I saw an edge with a peak.

>You're so set in your ways you go about proclaiming, "Can't be done",
>thus I tease >:-}

If you thought I was claiming that there was no way to make a waveform with overshoot in SPICE, you weren't reading very closely. That's all you've got so far.

I'm interested if you have something more substantive, but I'm not holding my breath waiting.

Cheers

Phil Hobbs

[John Larkin]

On Sun, 29 Jan 2017 11:10:22 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sun, 29 Jan 2017 10:02:10 -0800, John Larkin
><jjla...@highlandtechnology.com> wrote:
>
>[snip].
>>
>>A boy needs to solder now and then anyhow.
>
>I still have a couple of pounds of 60/40 on hand, plus a Weller WES51
>station.
>
> ...Jim Thompson

I have a Metcal, and it's worth it. Temperature controlled, gobs of
heat when you need it, heats up in seconds, and you can change the tip
in about 15 seconds.

Of course I use 63/37 leaded, rosin-core solder.

[John Larkin]

On Sun, 29 Jan 2017 11:46:00 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sun, 29 Jan 2017 10:14:43 -0800, John Larkin
><jjla...@highlandtechnology.com> wrote:
>
>[snip]
>
>>
>>I guess that designing monolithic ICs discourages breadboarding.
>>Nobody makes Dremels tiny enough.
>
>I started using a simulator somewhere around 1977-1980 (Berkeley Spice
>on a VAX780), but I continued to do bread-boarding until ~1990.
>
>There used to be packages of bipolar IC devices, called "kit-parts"
>(*). See "BreadBoard.jpg" on the S.E.D/Schematics Page of my website
>for an example. I created that board while I was Analog Guru at
>OmniComp/GenRad. I still have pieces of it that I use for G-jobs...
>original size was 1' x 1' with 72 (IIRC) up to 16 pin DIL socket
>locations.
>
>(*) 4-5 devices per package, different packages for different sizes
>(emitter-size scale factor)
>
> ...Jim Thompson

Didn't someone make a monolithic generic linear IC? The connections
were top layer metalization, or maybe even wire bonds.

The analog equivalent of the FPGA has been attempted but not very
successfully.

[Jim Thompson]

Poor baby! It's a diode.

[Jim Thompson]

On Sun, 29 Jan 2017 14:32:22 -0800, John Larkin

<jjla...@highlandtechnology.com> wrote:

>On Sun, 29 Jan 2017 11:10:22 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sun, 29 Jan 2017 10:02:10 -0800, John Larkin
>><jjla...@highlandtechnology.com> wrote:
>>
>>[snip].
>>>
>>>A boy needs to solder now and then anyhow.
>>
>>I still have a couple of pounds of 60/40 on hand, plus a Weller WES51
>>station.
>>
>> ...Jim Thompson
>
>I have a Metcal, and it's worth it. Temperature controlled, gobs of
>heat when you need it, heats up in seconds, and you can change the tip
>in about 15 seconds.
>
>Of course I use 63/37 leaded, rosin-core solder.

All my G-jobs are thru-hole, no surface-mount stuff, so I don't need
anything fancy. (The 60/40 IS rosin-core.)

[Jim Thompson]

On Sun, 29 Jan 2017 14:38:03 -0800, John Larkin

<jjla...@highlandtechnology.com> wrote:

>On Sun, 29 Jan 2017 11:46:00 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sun, 29 Jan 2017 10:14:43 -0800, John Larkin
>><jjla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>
>>>
>>>I guess that designing monolithic ICs discourages breadboarding.
>>>Nobody makes Dremels tiny enough.
>>
>>I started using a simulator somewhere around 1977-1980 (Berkeley Spice
>>on a VAX780), but I continued to do bread-boarding until ~1990.
>>
>>There used to be packages of bipolar IC devices, called "kit-parts"
>>(*). See "BreadBoard.jpg" on the S.E.D/Schematics Page of my website
>>for an example. I created that board while I was Analog Guru at
>>OmniComp/GenRad. I still have pieces of it that I use for G-jobs...
>>original size was 1' x 1' with 72 (IIRC) up to 16 pin DIL socket
>>locations.
>>
>>(*) 4-5 devices per package, different packages for different sizes
>>(emitter-size scale factor)
>>
>> ...Jim Thompson
>
>Didn't someone make a monolithic generic linear IC? The connections
>were top layer metalization, or maybe even wire bonds.

Yes. They had different size chips with different arrays of devices.
I did a few designs for an audio-phoolery company in San Jose _many_
years ago. It was really tough to get a high-percentage of
utilization with only one metal layer... you could use N+
pass-under's, but that wasted an NPN in the process.

It just came to me, the array-chip provider was Interdesign, Hans
Camenzind's company.

>
>The analog equivalent of the FPGA has been attempted but not very
>successfully.

Yep. Too many variables.

[pcdh...@gmail.com]

>>I'm interested if you have something more substantive, but I'm not holding my breath waiting.
>>
>>Cheers
>>
>>Phil Hobbs

>Poor baby!  It's a diode.

And that in a nutshell is why I don't bother following your links. A pity--you'd have a lot to contribute if you could just get over yourself.

However, life goes on either way.

Cheers

Phil Hobbs

[Jim Thompson]

I was just demonstrating that it _is_ possible to Spice model forward
over-shoot and reverse-recovery... which modeling you have claimed is
impossible without "hacking" the simulator code.

You are wrong, but go ahead and stick your head in the sand if you
want.

I will release the model in encrypted LTspice format.

[pcdh...@gmail.com]

>I was just demonstrating that it _is_ possible to Spice model forward
>over-shoot and reverse-recovery... which modeling you have claimed is
>impossible without "hacking" the simulator code.

>You are wrong, but go ahead and stick your head in the sand if you
>want.

>I will release the model in encrypted LTspice format.

You didn't demonstrate squat. You posted a screen shot and followed it up with a lot of bluster.

Where I come from we know a trick worth two of that one.

Cheers

Phil Hobbs

[Jim Thompson]

Bwahahahahahaha!

[k...@notreal.com]

On Sun, 29 Jan 2017 14:32:22 -0800, John Larkin

<jjla...@highlandtechnology.com> wrote:

>On Sun, 29 Jan 2017 11:10:22 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sun, 29 Jan 2017 10:02:10 -0800, John Larkin
>><jjla...@highlandtechnology.com> wrote:
>>
>>[snip].
>>>
>>>A boy needs to solder now and then anyhow.
>>
>>I still have a couple of pounds of 60/40 on hand, plus a Weller WES51
>>station.
>>
>> ...Jim Thompson
>
>I have a Metcal, and it's worth it. Temperature controlled, gobs of
>heat when you need it, heats up in seconds, and you can change the tip
>in about 15 seconds.

I gave the Metcal away when I got a Weller WX2. Metcal is stone age
stuff.

https://www.digikey.com/product-detail/en/apex-tool-group/WX2021N/WX2021N-ND/2608021

>
>Of course I use 63/37 leaded, rosin-core solder.

No socialist solder for me, either.

[k...@notreal.com]

On Sun, 29 Jan 2017 14:38:03 -0800, John Larkin

<jjla...@highlandtechnology.com> wrote:

>On Sun, 29 Jan 2017 11:46:00 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sun, 29 Jan 2017 10:14:43 -0800, John Larkin
>><jjla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>
>>>
>>>I guess that designing monolithic ICs discourages breadboarding.
>>>Nobody makes Dremels tiny enough.
>>
>>I started using a simulator somewhere around 1977-1980 (Berkeley Spice
>>on a VAX780), but I continued to do bread-boarding until ~1990.
>>
>>There used to be packages of bipolar IC devices, called "kit-parts"
>>(*). See "BreadBoard.jpg" on the S.E.D/Schematics Page of my website
>>for an example. I created that board while I was Analog Guru at
>>OmniComp/GenRad. I still have pieces of it that I use for G-jobs...
>>original size was 1' x 1' with 72 (IIRC) up to 16 pin DIL socket
>>locations.
>>
>>(*) 4-5 devices per package, different packages for different sizes
>>(emitter-size scale factor)
>>
>> ...Jim Thompson
>
>Didn't someone make a monolithic generic linear IC? The connections
>were top layer metalization, or maybe even wire bonds.
>
>The analog equivalent of the FPGA has been attempted but not very
>successfully.

Well, there is the PSoC and IIRC Maxim has some sort of programmable
mixed signal thing.

[Tim Williams]

"Phil Hobbs" <pcdhSpamM...@electrooptical.net> wrote in message
news:mtudndjrZd96iBPF...@supernews.com...
> No. Not transport equations, as I said, and there are lots of other
> examples of integral or integrodifferential equations. They're generally
> not reducible to systems of ODEs, because no ODE can be nonlocal, and so
> no solver limited to ODEs can handle them.

You can't solve diffusion*, but you can make a damn good approximation of it
(say with an R+L or R+C ladder), and if it's close enough for gov't work,
who cares?

*Except in AC steady state (e.g. R = K * sqrt(F)). But that's boring and
doesn't count.

As you're rather more in-depth with physics than I am -- could you
illustrate with some examples of systems that are impractical to approximate
in this way?

Why not a diode? Under what V, I, t conditions would the approximation
fail?

> You can't even write an ODE to describe a piece of coax from a circuits
> point of view--the SPICE transmission line isn't an ODE model, it's a
> special case, i.e. the simulator code has to be hacked up to support it.

Or approximated, such as LC ladder sections. Shitty, but practical for some
cases -- as is the condition for all approximation methods, including
anything else in SPICE.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

[pcdh...@gmail.com]

>As you're rather more in-depth with physics than I am -- could you
>illustrate with some examples of systems that are impractical to approximate
>in this way?

Systems with memory, diffusion, or delay elements such as transmission lines, for a few. You can use a bunch of elements to model the internal state of the process, as you say, but it only works over a restricted parameter range and is not usually very satisfactory.

It takes a metric buttload of LCs to model coax at all accurately over more than a fraction of a wavelength.

>Why not a diode?  Under what V, I, t conditions would the approximation
fail?

Basically any except the ones you used to fit the model. ;)

That's a bit unfair of course, but I invite you to consider how you'd model an SRD accurately in SPICE. It sure wouldn't be a lot of little RCs.

Some people run numerical models in Excel, because that's the only tool they know. Putting bandaids on SPICE may sometimes be better than writing your own simulator, but it's not a universal tool even for circuit design.

Cheers

Phil Hobbs
(simulator writer and very occasional SPICE bandager)

[Jim Thompson]

On Mon, 30 Jan 2017 05:04:38 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"Phil Hobbs" <pcdhSpamM...@electrooptical.net> wrote in message
>news:mtudndjrZd96iBPF...@supernews.com...
>> No. Not transport equations, as I said, and there are lots of other
>> examples of integral or integrodifferential equations. They're generally
>> not reducible to systems of ODEs, because no ODE can be nonlocal, and so
>> no solver limited to ODEs can handle them.
>
>You can't solve diffusion*, but you can make a damn good approximation of it
>(say with an R+L or R+C ladder), and if it's close enough for gov't work,
>who cares?

You don't even need that... think charge accumulation as a trigger
mechanism.

>
>*Except in AC steady state (e.g. R = K * sqrt(F)). But that's boring and
>doesn't count.
>
>As you're rather more in-depth with physics than I am -- could you
>illustrate with some examples of systems that are impractical to approximate
>in this way?
>
>Why not a diode? Under what V, I, t conditions would the approximation
>fail?
>
>
>> You can't even write an ODE to describe a piece of coax from a circuits
>> point of view--the SPICE transmission line isn't an ODE model, it's a
>> special case, i.e. the simulator code has to be hacked up to support it.
>
>Or approximated, such as LC ladder sections. Shitty, but practical for some
>cases -- as is the condition for all approximation methods, including
>anything else in SPICE.
>
>Tim

[John Devereux]

pcdh...@gmail.com writes:

>>As you're rather more in-depth with physics than I am -- could you
>>illustrate with some examples of systems that are impractical to approximate
>>in this way?
>
> Systems with memory, diffusion, or delay elements such as transmission
> lines, for a few. You can use a bunch of elements to model the
> internal state of the process, as you say, but it only works over a
> restricted parameter range and is not usually very satisfactory.
>
> It takes a metric buttload of LCs to model coax at all accurately over more than a fraction of a wavelength.
>
>>Why not a diode?  Under what V, I, t conditions would the approximation
> fail?
>
> Basically any except the ones you used to fit the model. ;)
>
> That's a bit unfair of course, but I invite you to consider how you'd
> model an SRD accurately in SPICE. It sure wouldn't be a lot of little
> RCs.

Well you could simulate a computer that could run a better model... :)




--

John Devereux

[John Larkin]

On Mon, 30 Jan 2017 06:07:19 -0800 (PST), pcdh...@gmail.com wrote:

>>As you're rather more in-depth with physics than I am -- could you
>>illustrate with some examples of systems that are impractical to approximate
>>in this way?
>
>Systems with memory, diffusion, or delay elements such as transmission lines, for a few. You can use a bunch of elements to model the internal state of the process, as you say, but it only works over a restricted parameter range and is not usually very satisfactory.
>
>It takes a metric buttload of LCs to model coax at all accurately over more than a fraction of a wavelength.

Been there. The number of LC sections goes as the square of Td/Tr.
That gets painful fast, especially running ECA on an 8086 DOS machine.

LC delay line models ring terribly, too.

>
>>Why not a diode?  Under what V, I, t conditions would the approximation
>fail?
>
>Basically any except the ones you used to fit the model. ;)
>
>That's a bit unfair of course, but I invite you to consider how you'd model an SRD accurately in SPICE. It sure wouldn't be a lot of little RCs.

One wouldn't likely need a full model, just something that behaves
about right under the expected bias and such. A full model would be
nasty to write.

[pcdh...@gmail.com]

>>That's a bit unfair of course, but I invite you to consider how
>>you'd model an SRD accurately in SPICE. It sure wouldn't be a lot
>>of little RCs.

>One wouldn't likely need a full model, just something that behaves
>about right under the expected bias and such. A full model would be
>nasty to write.

It would in Spice, for sure, but it ought to be possible to do it with an auxiliary 1-D transport model bodged into the main SPICE code.

In my EM simulator I have something like that to handle materials with Lorentz and Debye poles (e.g. real metals). I didn't invent the idea, I cribbed it from Taflove & Hagness, "Computational Electromagnetics". (Great book btw.)

Cheers

Phil Hobbs

[Tim Williams]

"Jim Thompson" <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
message news:g5ku8cpdnm7eeqnul...@4ax.com...

>>You can't solve diffusion*, but you can make a damn good approximation of
>>it
>>(say with an R+L or R+C ladder), and if it's close enough for gov't work,
>>who cares?
>
> You don't even need that... think charge accumulation as a trigger
> mechanism.

Well, that's what the existing one does, in a sense, as I understand it.
(You charge up a nonlinear capacitor, and it discharges on reverse.
Turn-off is "triggered" when the excess capacitance becomes small enough not
to care.)

(Huh...Also, you should know better than to use words like "trigger", Mr.
all-continuous-derivatives!)

But that doesn't capture dynamic voltages (namely, the transport stuff Phil
is concerned with), which has a more inductive aspect, but a
non-conservative (dissipative, lossy) one.

*Shrug*, I always put an R||L in series with the thing, approximating the
datasheet's spec (when provided), and that looked right enough. The curve
isn't actually linear, but usually sub-linear... almost sqrt(dI/dt), even
(ta-da, diffusion magic!). But a linear approximation is more than good
enough for a switching supply, where the dI/dt is well defined, consistent
and modest.

[Tim Williams]

<pcdh...@gmail.com> wrote in message
news:ad21884b-1edb-49a2...@googlegroups.com...
>>Why not a diode? Â Under what V, I, t conditions would the approximation

>>fail?
>
> Basically any except the ones you used to fit the model. ;)
>
> That's a bit unfair of course, but I invite you to consider how you'd
> model an SRD accurately in SPICE. It sure wouldn't be a lot of little
> RCs.

Well, I wouldn't, but not because of mathematical reasons, but practical
ones.

There's little point in modeling an SRD, because I wouldn't expect one to
actually be well enough specified to match its model, anyway. You're also
talking bandwidths where you need a full E&M model of the circuit, which
means you need to lay it out first. Catch-22.

An expensive Catch-22 at that -- once you've mortgaged half of your house to
buy the Ansys tool chain!

C'mon Phil, stop sucking on margaritas and kicking sand (by which I mean,
trivially pathological cases) in our faces. ;)

A much more practical case for diode modeling: switching supply
rectification and snubbing. I've yet to build one where the diodes
exhibited snap recovery. The V, I and t are all very well constrained in
this case. That's with V and I bounded by datasheet limits (Vrrm and
Isurge), and dI/dt maybe 10 A/ns worst case. Oh, and say it's pretty gross,
like 20% accuracy.

Is this proscribed well enough now? What's the Big-Oh on the number of
internal states?

[Jim Thompson]

On Tue, 31 Jan 2017 08:31:45 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"Jim Thompson" <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
>message news:g5ku8cpdnm7eeqnul...@4ax.com...
>>>You can't solve diffusion*, but you can make a damn good approximation of
>>>it
>>>(say with an R+L or R+C ladder), and if it's close enough for gov't work,
>>>who cares?
>>
>> You don't even need that... think charge accumulation as a trigger
>> mechanism.
>
>Well, that's what the existing one does, in a sense, as I understand it.
>(You charge up a nonlinear capacitor, and it discharges on reverse.
>Turn-off is "triggered" when the excess capacitance becomes small enough not
>to care.)

The nonlinear capacitor is the key

>
>(Huh...Also, you should know better than to use words like "trigger", Mr.
>all-continuous-derivatives!)

(:<0) I use "soft" switches 8-)

>
>But that doesn't capture dynamic voltages (namely, the transport stuff Phil
>is concerned with), which has a more inductive aspect, but a
>non-conservative (dissipative, lossy) one.

Easy enough as well.

>
>*Shrug*, I always put an R||L in series with the thing, approximating the
>datasheet's spec (when provided), and that looked right enough. The curve
>isn't actually linear, but usually sub-linear... almost sqrt(dI/dt), even
>(ta-da, diffusion magic!). But a linear approximation is more than good
>enough for a switching supply, where the dI/dt is well defined, consistent
>and modest.
>
>Tim

Indeed. I don't know why Phil got a hair so far up his butt he can't
retrieve it. I guess it's the old adage, don't ever try to tell a PhD
he's wrong ;-)

[LM]

On Sun, 29 Jan 2017 23:18:05 +0200, LM <sala...@mail.com> wrote:

I have now simulated two designs from two earlier writers. They both
work. But when looking for a way to attach Star-leds, I found
led-supplies which are cheaper, smaller and better than what I was
building. I of course new that this is the way it is put it is still
frustrating.

After I have attached the leds I'll start building the switcher.