6 bit things

[jla...@highlandsniptechnology.com]

Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \d repeated, roughly 100 Mbits/sec

is DC balanced, which SFP likes.

[Clive Arthur]

The French (and maybe others) use 'octet' for byte, so 'sextet' sounds
reasonable.

I use 'nips' for two bits, don't know if anyone else does.

--
Cheers
Clive

[Martin Rid]

jla...@highlandsniptechnology.com Wrote in message:r
> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

I would still consider it a byte, but sixbit.
You could always call it braille.

Cheers
--


----Android NewsGroup Reader----
https://piaohong.s3-us-west-2.amazonaws.com/usenet/index.html

[jla...@highlandsniptechnology.com]

On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
<martin...@verison.net> wrote:

>jla...@highlandsniptechnology.com Wrote in message:r
>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.
>
>I would still consider it a byte, but sixbit.
>You could always call it braille.
>
>Cheers

Maybe "frame" sounds better than "clump."

[Joe Gwinn]

On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
wrote:

>Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

It would still be a byte. Univac 1108, with 36-bit words.

A byte was always a fraction of a word, but the length of a word was
whatever the computer was designed for. All sizes were tried.

I've worked on digital computers with the following word sizes (in
bits): 12, 16, 24, 32, 36, 48, 64.

There were just as many floating-point formats.

Now days, it has settled down, and words are multiples of 8 bits in
size, usually a power of two. And all FP is IEEE.

The standards folk came up with "octet" because byte was so
ill-defined.

Half an octet was sometimes called a nybble. And so on.

>I want to send data over an SFP optical link, in 6-bit things.
>
> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>
>is DC balanced, which SFP likes.

If you use 8-bit patterns (best for component availability), but use
only the DC balanced subset, does that suffice?

Or, turn it around. Figure out how many DC-balanced patterns you
need, double it (for growth), and figure out long a word is needed.
Don't forget to include some control patterns.

Gigabit Ethernet does something like this, only grander, with two
patterns for every possible symbol to be sent, and they track current
DC balance, and choose which pattern to use that will reduce the
running DC balance.

Joe Gwinn

[Dan Purgert]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512

jla...@highlandsniptechnology.com wrote:
> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

As of sometime in the early-mid 1990s ('94?), "Byte" is 8 bits.
Historically, different terms were used ("word" , "syllable", etc.), and
represented some contiguous set of bits that wasn't necessarily 8 -- for
example 6, 12, or 18 bits. As far as I am aware, these were not
industry-standard terms, and therefore the bit-width would vary between
vendors.

As far as I am aware, the only modern subdivisions of a Byte are

- bit (1/8 Byte)
- nybble (1/2 Byte)

There's probably some ISO standard document somewhere that defines all
of this these days. :)

>
> I want to send data over an SFP optical link, in 6-bit things.
>
> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>
> is DC balanced, which SFP likes.

It is my understanding that an SFP tranceiver is somewhat akin to an
RS485 tranceiver, in that it doesn't particularly "care" about what
you're kicking out "over the wire". Rather, it is up to the
sending/receiving party to agree on a protocol for the data framing.

That being said; I'm mainly familiar with their use in IEEE 802.3
(Ethernet) networking, and not really outside of that context; so take
the above with a grain of salt.

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|_|O|_|
|_|_|O| Github: https://github.com/dpurgert
|O|O|O| PGP: DDAB 23FB 19FA 7D85 1CC1 E067 6D65 70E5 4CE7 2860

[John Walliker]

From https://en.wikipedia.org/wiki/Byte

The size of the byte has historically been hardware-dependent and no definitive standards existed that
mandated the size. Sizes from 1 to 48 bits have been used.[4][5][6][7] The six-bit character code was an
often-used implementation in early encoding systems, and computers using six-bit and nine-bit bytes
were common in the 1960s. These systems often had memory words of 12, 18, 24, 30, 36, 48, or 60 bits,
corresponding to 2, 3, 4, 5, 6, 8, or 10 six-bit bytes. In this era, bit groupings in the instruction stream were
often referred to as syllables[a] or slab, before the term byte became common.

I also like the sound of sextet. Its easy to say out loud and gives a strong hint at the meaning.

John

[John Walliker]

On Wednesday, 3 August 2022 at 17:52:04 UTC+1, Dan Purgert wrote:

> > I want to send data over an SFP optical link, in 6-bit things.
> >
> > 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
> >
> > is DC balanced, which SFP likes.
> It is my understanding that an SFP tranceiver is somewhat akin to an
> RS485 tranceiver, in that it doesn't particularly "care" about what
> you're kicking out "over the wire". Rather, it is up to the
> sending/receiving party to agree on a protocol for the data framing.

SFP transceivers are capacitor coupled on input and output so they do
care about the dc balance of the signal. I believe that there is also
capacitor coupling in the photodetector circuit. They don't care about
the exact protocol however.

John

[Dimiter_Popoff]

And others indeed. All the RFC-s I have read use "octet", apparently
a byte has not always been used meaning 8 bits. So the IETF have taken
the decision quite a while ago.

I'd go with "sextet", although since during programming it will
typically be part of a byte I'd comment "lowest 6 bits" or something.

[John Larkin]

On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net>
wrote:

>On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
>wrote:
>
>>Is a byte always 8 bits? What can I call a 6-bit byte? A clump?
>
>It would still be a byte. Univac 1108, with 36-bit words.
>
>A byte was always a fraction of a word, but the length of a word was
>whatever the computer was designed for. All sizes were tried.
>
>I've worked on digital computers with the following word sizes (in
>bits): 12, 16, 24, 32, 36, 48, 64.
>
>There were just as many floating-point formats.
>
>Now days, it has settled down, and words are multiples of 8 bits in
>size, usually a power of two. And all FP is IEEE.
>
>The standards folk came up with "octet" because byte was so
>ill-defined.
>
>Half an octet was sometimes called a nybble. And so on.
>
>
>>I want to send data over an SFP optical link, in 6-bit things.
>>
>> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>>
>>is DC balanced, which SFP likes.
>
>If you use 8-bit patterns (best for component availability), but use
>only the DC balanced subset, does that suffice?

We could do 8b10b, but that would need an FPGA to generate and
receive. I'm thinking about a spare-time thing that I could design
without an FPGA or uP, all hardware. My digital people are swamped
with big projects and I need something fun to design.

>
>Or, turn it around. Figure out how many DC-balanced patterns you
>need, double it (for growth), and figure out long a word is needed.
>Don't forget to include some control patterns.

The data is a 1-bit steam from a delta-sigma ADC. I just want to
transport it over fiber, and SFP is the easy way to do that. But SFP
is intended for telecom, ac coupled, intolerant of dc imbalance. Most
SFPs won't pass anything below about 1 MHz. But they are crazy fast
and have great AGC.

>
>Gigabit Ethernet does something like this, only grander, with two
>patterns for every possible symbol to be sent, and they track current
>DC balance, and choose which pattern to use that will reduce the
>running DC balance.

8b10b does elaborate long-term DC balancing like that. Too much work.

SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
35% to 65%.

>
>Joe Gwinn

[Fred Bloggs]

It's a hexad.

[Phil Hobbs]

Or 'clod'. Alternatives abound. ;)

I'd go with sextet (or sestet, if you're feeling poetic).

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[Martin Rid]

jla...@highlandsniptechnology.com Wrote in message:r

> On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid<martin...@verison.net> wrote:>jla...@highlandsniptechnology.com Wrote in message:r>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.>>I would still consider it a byte, but sixbit.>You could always call it braille. >>CheersMaybe "frame" sounds better than "clump."

Sixbit packet
And call it a day.

[Cydrome Leader]

six bit word.

[John Walliker]

After all this discussion it occurs to me that the correct answer is a bit.
The 0110 is a dc balanced header and the d \d is just a coding scheme
that ensures dc balance without conveying more than 1 bit of information.

John

[John Larkin]

On Wed, 3 Aug 2022 16:07:04 -0400 (EDT), Martin Rid

<martin...@verison.net> wrote:

>jla...@highlandsniptechnology.com Wrote in message:r
>> On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid<martin...@verison.net> wrote:>jla...@highlandsniptechnology.com Wrote in message:r>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.>>I would still consider it a byte, but sixbit.>You could always call it braille. >>CheersMaybe "frame" sounds better than "clump."
>
>Sixbit packet
>And call it a day.
>
>Cheers

Sixpack.

[John Larkin]

On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>jla...@highlandsniptechnology.com wrote:
>> On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
>> <martin...@verison.net> wrote:
>>
>>> jla...@highlandsniptechnology.com Wrote in message:r
>>>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.
>>>
>>> I would still consider it a byte, but sixbit.
>>> You could always call it braille.
>>>
>>> Cheers
>>
>> Maybe "frame" sounds better than "clump."
>>
>
>
>Or 'clod'. Alternatives abound. ;)
>
>I'd go with sextet (or sestet, if you're feeling poetic).
>
>Cheers
>
>Phil Hobbs

Now one of my guys claims that all we need is

1 0 d1 \d1 1 0 d2 \d2 .... etc

four bits per chunk to recover data d. Which is a nibble. I can still
call each 4 bits a frame.

I hate it when people are smarter than I am.

[Joe Gwinn]

Is it 100 million bits per second, or symbols per second?

What is being digitized? Voice? Data of some kind?

Is there a maximum latency and latency jitter requirement?

One-bit delta samples are usually signed, so the minimum is two
symbols. If the voltage being sent is zero, then we'll get a steady
+,-,+,-,+, stream, which will have very strong RF spurs and thus
emissions, so need to break this up.

A zero symbol makes it three, and an idle symbol, makes it four
symbols.

>>Gigabit Ethernet does something like this, only grander, with two
>>patterns for every possible symbol to be sent, and they track current
>>DC balance, and choose which pattern to use that will reduce the
>>running DC balance.
>
>8b10b does elaborate long-term DC balancing like that. Too much work.
>
>SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
>35% to 65%.

Yes, too much trouble. But if you use table lookup, you can get close
enough.

For instance, have four tables (one per symbol), with unique random
patterns, and choose a pattern from the correct table for the symbol
to be sent. These patterns are all inherently DC balanced, being half
+ and half -, and don't have any long runs.

On the receive end, use table lookup to recover the sent symbols.

You will need a sync pattern to establish and maintain symbol framing.
The key property of sync patterns is a sharp single correlation peak
against shifted examples of that pattern. A sync preamble may be
multiple sync symbols concatenated. Sync and idle symbols may be the
same.


Joe Gwinn

[Martin Brown]

MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
break any algorithm that relied on things being a handy power of two.


--
Regards,
Martin Brown

[John Walliker]

I never had enough bookshelf space - or money at the time - for the complete
works of Knuth. I don't know how he managed to do so much!

John

[Ricky]

That will only sync if your data changes. If your data stream has a sequence of ones, the data and sync can't be distinguished until a zero is sent. You will need a three bit sync pattern for that, or you don't need to send the sync for every bit.

If you are ok with data dependencies for aligning to the data, then simply sending d and /d as a pair is easily synchronized to at any data transition. Hmmm.... d,/d,d,/d Where have I seen that before??? I'm picturing a place in the UK.

Why reinvent the wheel? This doesn't even require a separate clock!

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

[John Larkin]

There's no point in a challenge to design the worst CPU architecture,
since it's been done so many times already.

[John Larkin]

On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net>

The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
do that. 10M would be plenty.

>
>What is being digitized? Voice? Data of some kind?

Some customer's analog voltage. Might be a strain gage load cell, for
example. We'd have some input ranges.

>
>Is there a maximum latency and latency jitter requirement?

Neither, actually. I just want to transport the ADC output correctly.

>
>One-bit delta samples are usually signed, so the minimum is two
>symbols. If the voltage being sent is zero, then we'll get a steady
>+,-,+,-,+, stream, which will have very strong RF spurs and thus
>emissions, so need to break this up.

The ADC has a one-bit output over +-320 mV input, and averages 50%
duty cycle at 0 volts in. I just want to transport that bit over a
fiber link.

>
>A zero symbol makes it three, and an idle symbol, makes it four
>symbols.
>
>
>>>Gigabit Ethernet does something like this, only grander, with two
>>>patterns for every possible symbol to be sent, and they track current
>>>DC balance, and choose which pattern to use that will reduce the
>>>running DC balance.
>>
>>8b10b does elaborate long-term DC balancing like that. Too much work.
>>
>>SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
>>35% to 65%.
>
>Yes, too much trouble. But if you use table lookup, you can get close
>enough.

I don't want an FPGA or a uP in this box. All my coder-people are too
busy on other projects now. So, a few gates and flipflops.

[Ricky]

Manchester encoding is one of the simplest things in the world to decode. It's also very easy to encode. Look it up. You'll be surprised at how easy it is.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

[bitrex]

Have you heard the song that's just six words long:

<https://youtu.be/SIIvJkSLSfw>

[Ricky]

The refrain was seven words actually, so not DC balanced.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

[Jasen Betts]

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
> Is a byte always 8 bits?

no, this is why internet standards use the term "Octet" instead

> What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
"Sextet" would work also.

> I want to send data over an SFP optical link, in 6-bit things.

> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM

> is DC balanced, which SFP likes.

seems heavy on clock and light on data. I'd call that a symbol.


Is there a better term for the code used to control WS2812 leds than
one bit PWM?
--
Jasen.

[Martin Brown]

You can always add more bookshelves...

My friend and I got Volume I Fundamental Algorithms as undergraduates
and worked through most of the problems including implementing a virtual
Mix machine. We even found a bug in the prime number test example and
sent it off hoping for 2^N dollars in return. It had already been
reported so we just got a nice postcard back from him instead.

Someone borrowed my copy of Seminumerical Algorithms and never gave it
back. I never did get to Sorting and Searching (my friend did).

LaTex markup language remains as one of the side effects of Knuth
finding no suitable markup language for such documents.

ISTR Roff on Unix or the IBM mainframe was the least unsuitable option
at the time and later something odd and nearly Wysiwyg (but not quite)
from Manchester University running on a Sirius PC as a word processor.

https://en.wikipedia.org/wiki/Sirius_Systems_Technology

--
Regards,
Martin Brown

[TTman]

On 03/08/2022 16:52, jla...@highlandsniptechnology.com wrote:
> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?
>
> I want to send data over an SFP optical link, in 6-bit things.
>
> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>
> is DC balanced, which SFP likes.
>

A byte with 2 null bits...

--
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus

[John May]

I think Leslie Lamport deserves a bit of a shout for LaTeX :-)

I was quite attracted to Knuth's literate programming ideas for a while, but in multi programmer projects the approach was allways rejected.

[Jeroen Belleman]

You can't deny that LaTeX makes beautiful documents, and it will
never trash your source files, contrary to some other piece of
$oftware we all love to hate. It sure is weird though.

And don't believe the statement that you can concentrate on
contents and forget about the formatting. Still, it's my first
choice for slides and text documents, if the choice is mine.

Jeroen Belleman

[Dan Purgert]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512

Jeroen Belleman wrote:
> Martin Brown wrote:
>> [...]

>> LaTex markup language remains as one of the side effects of Knuth
>> finding no suitable markup language for such documents.
>

> You can't deny that LaTeX makes beautiful documents, and it will
> never trash your source files, contrary to some other piece of
> $oftware we all love to hate. It sure is weird though.
>
> And don't believe the statement that you can concentrate on
> contents and forget about the formatting. Still, it's my first
> choice for slides and text documents, if the choice is mine.

For the most part, I find that statement to be true. That is not to say
there are never cases where I'm looking at a page and shifting an image
or something around; but it always feels more like an aesthetic "last
step". On the other hand, WYSIWYG editors kind of force one to "format"
as they go, which can cause some headaches / loss of momentum in the
writing.


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--
|_|O|_|
|_|_|O| Github: https://github.com/dpurgert
|O|O|O| PGP: DDAB 23FB 19FA 7D85 1CC1 E067 6D65 70E5 4CE7 2860

[John Larkin]

On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
<use...@revmaps.no-ip.org> wrote:

>On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
>> Is a byte always 8 bits?
>
>no, this is why internet standards use the term "Octet" instead
>
>> What can I call a 6-bit byte? A clump?
>
>sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
>"Sextet" would work also.
>
>> I want to send data over an SFP optical link, in 6-bit things.
>
>> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>
>looks like manchester encoded one bit PWM

Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \d

to get a DC balanced form that is easy to generate and decode. It's
terrifyingly clever.

[Joe Gwinn]

On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin

All very low bandwidth stuff. Is it required to transmit absolute
values, or is just the "AC" part enough?

Sounds like for instance actual strain values are desired.

>>
>>Is there a maximum latency and latency jitter requirement?
>
>Neither, actually. I just want to transport the ADC output correctly.

OK.

>>
>>One-bit delta samples are usually signed, so the minimum is two
>>symbols. If the voltage being sent is zero, then we'll get a steady
>>+,-,+,-,+, stream, which will have very strong RF spurs and thus
>>emissions, so need to break this up.
>
>The ADC has a one-bit output over +-320 mV input, and averages 50%
>duty cycle at 0 volts in. I just want to transport that bit over a
>fiber link.

So the ADC output is a signed bit per sample.

>>
>>A zero symbol makes it three, and an idle symbol, makes it four
>>symbols.
>>
>>
>>>>Gigabit Ethernet does something like this, only grander, with two
>>>>patterns for every possible symbol to be sent, and they track current
>>>>DC balance, and choose which pattern to use that will reduce the
>>>>running DC balance.
>>>
>>>8b10b does elaborate long-term DC balancing like that. Too much work.
>>>
>>>SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
>>>35% to 65%.
>>
>>Yes, too much trouble. But if you use table lookup, you can get close
>>enough.
>
>I don't want an FPGA or a uP in this box. All my coder-people are too
>busy on other projects now. So, a few gates and flipflops.

OK. This too can be done, given a large ratio between optical bit
rate and ADC bitrate.

The AGC in the SFP is pretty fast, but the optical bitrate must be
much faster, or the AGC will flatten the desired signal. The SFP
datasheet should define the AGC response speed.

So, pick a convenient optical signaling (flash) rate well above the
AGC reaction speed, so you will be able to recover the sent pattern at
the SFP output.

Here is one possible design:

Choose a ADC sample rate a fraction of the optical rate. The fraction
is determined by choosing orthogonal codes to represent +1, zero, or
-1 ADC outputs to be sent. Also need a frame-start symbol.

The orthogonal codes are chosen from the standard Gold Codes:

.<https://en.wikipedia.org/wiki/Gold_code>

The codes have odd length, and are fairly close to balanced, so one
ought to be able to find some truncated Gold codes of even length
(drop last bit) that are exactly balanced. We need only four such
symbol codes, and a 16-bit code would allow the optical rate to be 16
times the code (ADC output) rate.

There must be a steady stream of ADC symbols, even if ADC output is
zero, to keep the SFP AGC stable.

Generation. Drive a 16-line demux with the optical clock. Make or
don't make connections from the demux to an adder, as dictated by the
symbol to be sent. The adder output is used to drive the SFP TX
input.

Reception. Lock a phase-lock loop to the optical flash rate, to
recover the optical clock.

Have one correlator per symbol type, all running in parallel. Given
the near-perfect correlation behavior of Gold codes, the correlator
output will be roughly one unit amplitude except at the pattern
center, where the peak will be about 16 units, so a threshold set at 8
units should enable perfect recovery.

The frame sync symbol is used if we are switching between a reference
voltage and the strain-gage output voltage, to mark where reference
starts. May need an ref-end symbol.

If no correlator peaks for more than a few symbol periods, complain.
The SFP will also tell you if any optical power is being received, if
I recall.

Design the receiver first, as it's usually the harder of the two, then
design the transmitter to make the receiver happy.


Joe Gwinn

[Clifford Heath]

On 4/8/22 20:26, John May wrote:
> I was quite attracted to Knuth's literate programming ideas for a while, but in multi programmer projects the approach was allways rejected.

The difficulty with literate programming is that you need to find
literate programmers.

Modern programming languages tend to assist the programmer to reveal
their intentions to a much greater degree that was e.g. the FORTRAN in
which Knuth wrote TeX.

But programmers still have to have a sense of which things might or
might not be already known or become apparent to another human - meaning
they need to see outside their own heads. That's not very common, and
even less so in more productive programmers.

[John Larkin]

On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joeg...@comcast.net>

It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
but runs its stuff continuously. It has a clock input and a single bit
logic output. The duty cycle of the output reports the analog input:
0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
crazy precise. Once we convey that logic level to a destination, we
"decimate" it into a 16 or 18 or 20 bit value that reflects the input
voltage. The decimation is typically digital, a sinc3 filter, but I
might do it all analog in this case. Decimation becomes a lowpass
filter.

>
>
>>>
>>>A zero symbol makes it three, and an idle symbol, makes it four
>>>symbols.
>>>
>>>
>>>>>Gigabit Ethernet does something like this, only grander, with two
>>>>>patterns for every possible symbol to be sent, and they track current
>>>>>DC balance, and choose which pattern to use that will reduce the
>>>>>running DC balance.
>>>>
>>>>8b10b does elaborate long-term DC balancing like that. Too much work.
>>>>
>>>>SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
>>>>35% to 65%.
>>>
>>>Yes, too much trouble. But if you use table lookup, you can get close
>>>enough.
>>
>>I don't want an FPGA or a uP in this box. All my coder-people are too
>>busy on other projects now. So, a few gates and flipflops.
>
>OK. This too can be done, given a large ratio between optical bit
>rate and ADC bitrate.
>
>The AGC in the SFP is pretty fast, but the optical bitrate must be
>much faster, or the AGC will flatten the desired signal. The SFP
>datasheet should define the AGC response speed.

The combination of AGC and AC coupling makes SFPs not work well at
data rates below about 1 MHz. That varies a lot with specific parts.

It's really simple; just move the 1-bit logic level output of the ADC
to the destination and recover a clock to know where the bits are.
We'd clock the ADC at 20 or maybe 10 MHz.

[John S]

4 bit is a nybble. Or a dollar.

[Phil Hobbs]

Nah, two bits is a quarter, so 8 bits is a dollar.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[Joe Gwinn]

On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin

The fact that the ADUM7703 is clocked implies that is samples on the
clock. Otherwise, why require a clock input? Datasheet page 4 shows
the relationship.

More at end.

If I'm understanding the timing diagram on datasheet page 4, one can
have a long string of ones, or of zeros, depending on the input analog
voltage, which has fairly low bandwidth and so can linger at a voltage
for very long durations.

It's these long rafts of ones or zeros that I worry will baffle the
SFP's AGC function, causing data-dependent link failures.

What make and model of SFP are you looking at?


But one could use two Gold-code symbols, encoding MDATA one and MDATA
zero, and a pair of correlators at the other end of the fiber-optic
link to recover the original MDATA stream.

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?


Joe Gwinn

[upsid...@downunder.com]

On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
wrote:

>Is a byte always 8 bits? What can I call a 6-bit byte? A clump?
>

>I want to send data over an SFP optical link, in 6-bit things.
>
> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>
>is DC balanced, which SFP likes.

Since you are transferring only a single (net) bit, why are you
worrying about the names of the actual frame bits ?

Compare to the situation with asynchronous serial communication. A
UART can usually transfer 5-8 (some up to 14) net data bits, but in
addition to this, the start bit is added, an optional parity bit and
0, 1, 1.5 or 2 stop bits are added, producing a 75 to 16 bit
transmitted frame. You really rarely have to worry about the total
frame size (except for some RS-485 converters).

[John Walliker]

With optical fibre losses of a few tenths of a dB/km and a likely link
margin of well over 10dB I don't think optical cable length will be an
issue here.
The originally proposed 6-bit encoding scheme included the data bit
followed by its complement, so that will have removed any dc baseline
fluctuation issues.
SFPs are remarkable tolerant of optical abuse. I have tried using
multimode fibre with single mode SFPs and single mode SFPs with
multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every
combination works fine despite the optical losses in some of those
configurations.

John

[John Larkin]

On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>

Of course voltages near the negative rail have to get close to 0% duty
cycle, low bit density. I can avoid that by not allowing more than,
say, +-250 mV.

Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
low frequency components in the duty cycle.

>
>It's these long rafts of ones or zeros that I worry will baffle the
>SFP's AGC function, causing data-dependent link failures.

That's the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

>
>What make and model of SFP are you looking at?

I've evaluated a bunch of them. I'll have to look that up.

>
>
>But one could use two Gold-code symbols, encoding MDATA one and MDATA
>zero, and a pair of correlators at the other end of the fiber-optic
>link to recover the original MDATA stream.
>
>And, optical SNR matters. If the minimum SNR is high, the tolerance
>for non-zero DC balance, is increased. What is the maximum optical
>cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.


>
>
>Joe Gwinn

[Gerhard Hoffmann]

Am 05.08.22 um 19:15 schrieb John Larkin:

>> And, optical SNR matters. If the minimum SNR is high, the tolerance
>> for non-zero DC balance, is increased. What is the maximum optical
>> cable length contemplated?
>
> A couple of km, maybe. Singlemode can go 10s of km.

I think the limit is dispersion, not attenuation.

Chees, Gerhard

[John Larkin]

On Fri, 05 Aug 2022 19:18:19 +0300, upsid...@downunder.com wrote:

>On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
>wrote:
>
>>Is a byte always 8 bits? What can I call a 6-bit byte? A clump?
>>
>>I want to send data over an SFP optical link, in 6-bit things.
>>
>> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>>
>>is DC balanced, which SFP likes.
>
>Since you are transferring only a single (net) bit, why are you
>worrying about the names of the actual frame bits ?

Names?

>
>Compare to the situation with asynchronous serial communication. A
>UART can usually transfer 5-8 (some up to 14) net data bits, but in
>addition to this, the start bit is added, an optional parity bit and
>0, 1, 1.5 or 2 stop bits are added, producing a 75 to 16 bit
>transmitted frame. You really rarely have to worry about the total
>frame size (except for some RS-485 converters).

I can get 10 Gbit SFPs cheap, so channel rate isn't an issue. But we
need DC balance and circuit simplicity. The new 4-bit thing looks
good, 1 0 d \d per frame.

[Lasse Langwadt Christensen]

move the bits around and it is FSK; F and 2F

1100
1010

[Phil Hobbs]

Step-index multimode can be as bad as 20 ns/km iirc. Good graded-index
fibre is more than a factor of 10 better (400 MHz * km is a number I've
seen).

Single-mode fibre is good for a really long distance--it's just the
optical bandwidth that sets the dispersion.

[John Larkin]

Cute. But pattern 1010 1010

has an embedded 1010

which means that a simple running decoder can mis-frame
the clumps.

[John Larkin]

On Fri, 5 Aug 2022 19:20:08 +0200, Gerhard Hoffmann <dk...@arcor.de>
wrote:

Right. Multimode has bad time dispersion.

The Guinness record for an un-repeatered fiber link is 10,358.16 km.

[Lasse Langwadt Christensen]

isn't that what you get with 1 0 d \d and d = 1 ?

>
> which means that a simple running decoder can mis-frame
> the clumps.

won't you have that problem with all possible ways of using 4 bit?

[Mike Monett]

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf





--
MRM

[a a]

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[Joe Gwinn]

On Fri, 05 Aug 2022 10:15:20 -0700, John Larkin

I'd assume that you would prefer not to do that.

If both zero and one MDATA samples are each coded with a DC balanced
pattern, there is no need to restrict the voltage range.

>Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
>low frequency components in the duty cycle.

This MDATA signal seems to be pulse-width modulated,not sigma-delta
(despite the name), sampled at the ADC clock rate. What is being
transmitted is in fact an absolute voltage value, with some
quantization noise added. See datasheet page 16.

No idea why they talk of sigma-delta. Certainly was confusing me.

Maybe the sigma-delta stuff is buried in the front half of the "ADC".
There was talk of an internal 16-bit register somewhere. It could be
accumulating the up/down change pulses, the current value of this
register being what is pulse-width modulated and transmitted back to
earth.

>>It's these long rafts of ones or zeros that I worry will baffle the
>>SFP's AGC function, causing data-dependent link failures.
>
>That's the reason to send 4 bits for every actual payload bit, to keep
>the SFP data balanced.

Yes. Basically, what we are discussing here is how long the symbol
pattern should be. You still need a way to decode that isn't
vulnerable to frame-shift errors.

For which you need long strings of either kind of symbol (zero or one)
to decode in exactly one way, not using the end of one symbol and the
start of the next to declare an ADC sample. So the pattern cannot be
too short or too simple.

Digital correlation receivers are pretty simple, basically a shift
register with outputs being summed, half being direct and half being
inverted.

When the sought-for pattern is centered in the shift register, the
summer emits a peak of amplitude N. Otherwise, the output amplitude
is roughly zero, max unity, where N is the length of the pattern (and
thus shift register) in bits. No computer needed.

>>What make and model of SFP are you looking at?
>
>I've evaluated a bunch of them. I'll have to look that up.

If they all claim the enet PHY mentioned later, the AGC time constant
ought to be about the same, most likely being specified in the
relevant enet standard, to ensure that SFP modules are
interchangeable.

>>
>>But one could use two Gold-code symbols, encoding MDATA one and MDATA
>>zero, and a pair of correlators at the other end of the fiber-optic
>>link to recover the original MDATA stream.
>>
>>And, optical SNR matters. If the minimum SNR is high, the tolerance
>>for non-zero DC balance, is increased. What is the maximum optical
>>cable length contemplated?
>
>A couple of km, maybe. Singlemode can go 10s of km.

Singlemode fiber is cheap, and will certainly do the job. The
Ethernet PHY you want for this is "1000BASE-LX", as defined in IEEE
802.3 Clause 38. This is a common Gigabit Ethernet via optical fiber
PHY.

Going one-fifth the max reach should yield ample optical SNR, so long
ate there are few optical connectors


Joe Gwinn

[Joe Gwinn]

On Fri, 5 Aug 2022 09:22:21 -0700 (PDT), John Walliker
<jrwal...@gmail.com> wrote:

>On Friday, 5 August 2022 at 16:30:03 UTC+1, Joe Gwinn wrote:

[snip]

>>
>> And, optical SNR matters. If the minimum SNR is high, the tolerance
>> for non-zero DC balance, is increased. What is the maximum optical
>> cable length contemplated?
>>
>With optical fibre losses of a few tenths of a dB/km and a likely link
>margin of well over 10dB I don't think optical cable length will be an
>issue here.

Yes. It turns out that the max reach is one km, and singlemode will
go five km.

>The originally proposed 6-bit encoding scheme included the data bit
>followed by its complement, so that will have removed any dc baseline
>fluctuation issues.

It should, but the two-bit and four-bit schemes may be challenged. And
also suffer from framing errors.

>SFPs are remarkable tolerant of optical abuse. I have tried using
>multimode fibre with single mode SFPs and single mode SFPs with
>multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every
>combination works fine despite the optical losses in some of those
>configurations.

At 50 meters, basically anything will work.

With signals sent by RS422 over wire, the standard observation/joke
was that one could sent this signal on a two-strand barbed wire fence
-- so long as the cows didn't use the fence as a back scratchier.

Joe Gwinn

[Jasen Betts]

On 2022-08-04, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
><use...@revmaps.no-ip.org> wrote:
>
>>On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
>>> Is a byte always 8 bits?
>>
>>no, this is why internet standards use the term "Octet" instead
>>
>>> What can I call a 6-bit byte? A clump?
>>
>>sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
>>"Sextet" would work also.
>>
>>> I want to send data over an SFP optical link, in 6-bit things.
>>
>>> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>>
>>looks like manchester encoded one bit PWM
>
> Manchester is ambiguous. A string of 0s looks just like a string of
> 1s.

And also vise-versa but only then.

still the above looks the same as manchester( 0 1 d )

> One of my guys, on his ferry ride, figured out how to add two bit
> times
>
> 1 0 d \d

So now it's manchester( 1 d ) what does idle look like?

> to get a DC balanced form that is easy to generate and decode. It's
> terrifyingly clever.

FM coding seems easier

--
Jasen.

[Jasen Betts]

Biphase-M code (FM) does that for 2 slots per data bit instead of 4

It seems like you're reinventing the wheel, and having rejected the
triangular wheel for the square wheel are impressed by the
improvement it gives.

--
Jasen.

[John Larkin]

On Fri, 5 Aug 2022 23:13:37 -0000 (UTC), Jasen Betts
<use...@revmaps.no-ip.org> wrote:

>On 2022-08-05, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
>> On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>
>> wrote:
>>
>> Of course voltages near the negative rail have to get close to 0% duty
>> cycle, low bit density. I can avoid that by not allowing more than,
>> say, +-250 mV.
>>
>> Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
>> low frequency components in the duty cycle.
>>
>>>
>>>It's these long rafts of ones or zeros that I worry will baffle the
>>>SFP's AGC function, causing data-dependent link failures.
>>
>> That's the reason to send 4 bits for every actual payload bit, to keep
>> the SFP data balanced.
>
>Biphase-M code (FM) does that for 2 slots per data bit instead of 4

A long string of 0s is ambiguous. Harder to decode.

>
>It seems like you're reinventing the wheel, and having rejected the
>triangular wheel for the square wheel are impressed by the
>improvement it gives.

I didn't invent the 4-bit version. I wish I had.

But thank you for your polite and constructive assistance.

[John Larkin]

On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen

The decoder is a 3-bit shift register and a 2-input xnor gate.

[Phil Hobbs]

The schematics redrawn by the patent artist are fun, if not super
intelligible. Before I go trying to follow them, did the artist get
them right?

[Mike Monett]

I don't know. I never checked them. As you well know yourself, Patent
attorneys take the most well layed out schematics and turn them into
scrambled spaghetti. There were 5 pages of this crap and I didn't have time
to go through them all. I had left Memorex by that time and was working for
Diablo Corporation (now extinct), so all I did was sign the papers and take
the mandantory $1.00 to transfer ownership.

Trying to follow the schematic may be difficult. The circuit had to switch
between full phase/frequency detection to MFM decoding, as well as
synchronize the loop as quickly as possible after the address mark. This is a
short section of erased data to signify an area of all data bits (all ones)
to get the loop locked up on the correct data separator window.

The essential part of the circuit is what happens after the pair of d-flops
that form the PFD. By nature, PFD's cannot have deadband. Deadband occurs
when either the pullup or pulldown digital to analog conversion has a long
propagation delay so it does not respond to short pulses around zero phase
error.

The critical area is the quad pairs of 2N4209/2N5851 differential pairs
arranged so they cannot saturate.

This is what I-forget-his-name did in the MC4044. The ASC file is located in
https://tinyurl.com/2p97vht8

His input transistor for the pullup side, Q1, saturated as soon as the DATA
d-flop, U1, was clocked. Consequently, it did not come out of saturation for
a long time after both d-flops were reset. This produced the deadband. He
could easily have avoided this problem by adding a Baker clamp at the input
of Q1:

https://en.wikipedia.org/wiki/Baker_clamp

I avoided this problem by setting the current through the input differential
pair to 20ma and 10mA. When driving 50 Ohms, this produces 1V and 0.5V that
drives the output pair of differential amplifiers. I could have dropped the
pulldown emitter resistor to 510 ohms, but there were so many other issues
with trying to get foreign parts through Memorex purchasing that I was simply
swamped. It worked, time for refinement later.

Anyway, the critical thing is the input differential pair did not saturate,
and there was no deadband. I verified this with countless hours under the
scope hood. If you have ever spent time under a scope hood, you know about
the band it etches around your eyes. I wore that band for 9 months while I
was developing this circuit. The deadband problem was solved.

Of course, there are much simpler ways of coupling a pair of d-flops to a
loop filter, but I won't go through them now. Maybe later. The key is to make
the circuit fast enough to follow the short pulses from the d-flops around
zero phase error.





--
MRM

[Mike Monett]

Mike Monett <spa...@not.com> wrote:

[...]

> Of course, there are much simpler ways of coupling a pair of d-flops to
> a loop filter, but I won't go through them now. Maybe later. The key is
> to make the circuit fast enough to follow the short pulses from the
> d-flops around zero phase error.

I forgot - I included one method in FASTDIOD.ASC in
https://tinyurl.com/2p97vht8


--
MRM

[Clifford Heath]

On 6/8/22 09:13, Jasen Betts wrote:
> It seems like you're reinventing the wheel, and having rejected the
> triangular wheel for the square wheel are impressed by the
> improvement it gives.

Well, at least a Reuleux Triangle rolls with constant width!
<https://en.wikipedia.org/wiki/Reuleaux_triangle>

[Lasse Langwadt Christensen]

and how does that help? you still need to use 1010

[John S]

Oh! You're right! Thanks.

[jla...@highlandsniptechnology.com]

On Sat, 6 Aug 2022 16:35:13 +1000, Clifford Heath <no_...@please.net>
wrote:

That, for some weird reason, reminds me of a DDS frequency synthesizer
variant that we invented on Friday. Maybe I'll post that and see how
much hostility that one inspires.

[jla...@highlandsniptechnology.com]

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen

Try it. Draw a string of such 4-bit frames, with some 1s and 0s
encoded, as if they were in a long shift register.

Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
n+2. Slide it along the string of bits and see what comes out.

Actually, it's easier to think about using 1 0 \d d encoding and use
an xor gate. My guy did it the first way.

[Ricky]

On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
> <use...@revmaps.no-ip.org> wrote:
>
> >On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
> >> Is a byte always 8 bits?
> >
> >no, this is why internet standards use the term "Octet" instead
> >
> >> What can I call a 6-bit byte? A clump?
> >
> >sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
> >"Sextet" would work also.
> >
> >> I want to send data over an SFP optical link, in 6-bit things.
> >
> >> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
> >
> >looks like manchester encoded one bit PWM
> Manchester is ambiguous. A string of 0s looks just like a string of
> 1s.
>
> One of my guys, on his ferry ride, figured out how to add two bit
> times
>
> 1 0 d \d
>
> to get a DC balanced form that is easy to generate and decode. It's
> terrifyingly clever.

This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

With Manchester data you get alignment anytime there is a change in polarity of the data, either 1>0 or 0>1, because you end up with a single transition in the bit time, rather than two that you get with continuous data.

There is nothing magical about the pattern 1 0 d \d.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

[Ricky]

On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
> <use...@revmaps.no-ip.org> wrote:
>
> >On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
> >> Is a byte always 8 bits?
> >
> >no, this is why internet standards use the term "Octet" instead
> >
> >> What can I call a 6-bit byte? A clump?
> >
> >sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
> >"Sextet" would work also.
> >
> >> I want to send data over an SFP optical link, in 6-bit things.
> >
> >> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
> >
> >looks like manchester encoded one bit PWM
> Manchester is ambiguous. A string of 0s looks just like a string of
> 1s.
>
> One of my guys, on his ferry ride, figured out how to add two bit
> times
>
> 1 0 d \d
>
> to get a DC balanced form that is easy to generate and decode. It's
> terrifyingly clever.

Here's a simple and effective data pattern, d \d \d d. Now you have Manchester encoding of a stream which consists of the data and the inverted data, d \d. Very easy to modulate and demodulate along with data redundancy for error checking. No need for wasteful formatting overhead.

Encoding is blindingly simple. The output is the XOR of the data and a two bit, binary counter. The decode is the usual Manchester decode giving two bits, d and \d which you may use as you choose. It literally doesn't get much simpler than this.

--

Rick C.

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[Ricky]

On Thursday, August 4, 2022 at 7:40:51 PM UTC-4, John Larkin wrote:
> On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joeg...@comcast.net>
> wrote:
>
> >On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin
> ><jlarkin@highland_atwork_technology.com> wrote:
> >
> >>On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net>
> >>wrote:
> >>
> >>>On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin
> >>><jlarkin@highland_atwork_technology.com> wrote:
> >>>
> >>>>On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net>
> >>>>wrote:
> >>>>
> >>>>>On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
> >>>>>wrote:
> >>>>>

> >>>>>>Is a byte always 8 bits? What can I call a 6-bit byte? A clump?
> >>>>>
> >>>>>It would still be a byte. Univac 1108, with 36-bit words.
> >>>>>
> >>>>>A byte was always a fraction of a word, but the length of a word was
> >>>>>whatever the computer was designed for. All sizes were tried.
> >>>>>
> >>>>>I've worked on digital computers with the following word sizes (in
> >>>>>bits): 12, 16, 24, 32, 36, 48, 64.
> >>>>>
> >>>>>There were just as many floating-point formats.
> >>>>>
> >>>>>Now days, it has settled down, and words are multiples of 8 bits in
> >>>>>size, usually a power of two. And all FP is IEEE.
> >>>>>
> >>>>>The standards folk came up with "octet" because byte was so
> >>>>>ill-defined.
> >>>>>
> >>>>>Half an octet was sometimes called a nybble. And so on.
> >>>>>
> >>>>>

> >>>>>>I want to send data over an SFP optical link, in 6-bit things.
> >>>>>>
> >>>>>> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
> >>>>>>

> >>>>>>is DC balanced, which SFP likes.
> >>>>>

Or you can use Manchester encoding to encode the clock and easily recover it at the other end. Data bits with the clock for free! I guess some people don't like free.

--

Rick C.

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[Ricky]

I was thinking of sending d \d \d d, and that lets you align at a first level, but still leaves room for misalignment so the recovered data is \d rather than d.

What is wrong with sending a frame that is DC balanced over multiple data bits, even if not each one? 1 1 d0 \d0 0 0 d1 \d1 should be easy to sync to, is DC balanced and has unambiguous alignment. Any given data bit will be the middle two bits of 0011, 0101, 1010 or 1100. Because the frame bits are 11 or 00, they can't be confused with data in these 4 bit sequences.

Encoding is just a 3 bit counter and a few gates. Decoding can be done with a 4 bit shift register, an inverter and an 8 to 1 multiplexer, three SSI devices. That's pretty simple.

--

Rick C.

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[Ricky]

Or, decode can be done with the shift register and a pair of 2-input XOR gates and an AND gate. I almost missed that.

--

Rick C.

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[Lasse Langwadt Christensen]

but you still need to use 1010, in a long string of those you can't tell where the 4 bit start

1010101010
xx10101010

what are you going to clock the shift with?

[John Larkin]

On Sat, 6 Aug 2022 09:36:42 -0700 (PDT), Lasse Langwadt Christensen

Of course we need an 80 MHz PLL on the receive end to clock the bits;
that's easy. If I clock the ADC at 10 MHz, the bit rate and PLL are 40
MHz, which is handy because we stock a nice 40 MHz VCXO.

I don't care where a bit "starts", I just need to recover a 20 Mbps
delta-sigma stream to poke into a decimator.

Try it.

[John Larkin]

On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spa...@not.com>
wrote:

My favorite phase detector is a single d-flop. Clock from received
data, poke the local VCXO square wave into D.

It makes an early/late decision every data rising edge, and can
produce picosecond time alignment and picosecond jitter.

It's basically infinite gain and immune to analog errors. A
differential ECL flop is best, like NB7V52.

[Lasse Langwadt Christensen]

but you said:
"
Cute. But pattern 1010 1010

has an embedded 1010

[Joe Gwinn]

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

What's needed is to choose a pattern that will also ensure correct
framing in an arbitrary random string of one and zero symbols. This
is a slightly stronger requirement than orthogonal: The symbols must
be a good synch pattern as well. With only two kinds of symbol, it
ought to be possible, given a sufficiently long pattern.

Joe Gwinn

[Phil Hobbs]

$18 in hundreds. Got a second fave for us picosecond proles? ;)

[Mike Monett]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

> John Larkin wrote:

[...]

>> My favorite phase detector is a single d-flop. Clock from received
>> data, poke the local VCXO square wave into D.
>>
>> It makes an early/late decision every data rising edge, and can
>> produce picosecond time alignment and picosecond jitter.
>>
>> It's basically infinite gain and immune to analog errors. A
>> differential ECL flop is best, like NB7V52.
>>
>
> $18 in hundreds. Got a second fave for us picosecond proles? ;)
>
> Cheers
>
> Phil Hobbs

I disagree with the claims. However, a MC100EP52DT is CAD$3.47 at
Rochester, and a MC100EP52DTG is CAD$4.13 at Arrow, QTY 1:

https://octopart.com/search?q=100ep52&currency=CAD&specs=0





--
MRM

[Jeroen Belleman]

Infinite (OK, very large) gain around the lock target and zero
gain elsewhere. Not something you really want in a well behaved
loop. You really want constant loop gain.

Jeroen Belleman

[John Larkin]

On Sat, 6 Aug 2022 11:00:50 -0700 (PDT), Lasse Langwadt Christensen

As I said, try it.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
"Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

[John Larkin]

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net>
wrote:

A 2-input xnor is not a correlation receiver.

[Mike Monett]

Jeroen Belleman <jer...@nospam.please> wrote:

> On 2022-08-06 19:52, John Larkin wrote:

[...]

>> My favorite phase detector is a single d-flop. Clock from received
>> data, poke the local VCXO square wave into D.
>>
>> It makes an early/late decision every data rising edge, and can
>> produce picosecond time alignment and picosecond jitter.
>>
>> It's basically infinite gain and immune to analog errors. A
>> differential ECL flop is best, like NB7V52.
>>
>
> Infinite (OK, very large) gain around the lock target and zero
> gain elsewhere. Not something you really want in a well behaved
> loop. You really want constant loop gain.
>
> Jeroen Belleman

A single d-flop is a phase detector, not a frequency detector. It shares
the same lock characteristic with an XOR and a double balanced mixer,
although the XOR and DBM are quadrature detectors, where the d-flop is in
phase.

It has the highly desirable property of retaining the same gain on
harmonics, where the XOR and double balanced mixer both lose gain.

It takes the addition of a second d-flop and a feedback gate to create a
frequency/phase detector. However, it will no longer work on harmonics.

For more information on quadrature detectors, see "Operation of Phase
Comparator PC1" on page 9 of

https://www.ti.com/lit/an/scha003b/scha003b.pdf





--
MRM

[Ricky]

No, the pattern Larkin describes will provide accurate data at all times. While the PLL will produce the 4x clock, there is no data clock without examining the recovered data using the XOR gate, as he describes. By monitoring the output of that "detector", there will be a transition when the data changes.

So with initially, all 1 data, the decode will produce 1s on all 4x clock transitions. However, there is no way to detect the data clock, until the data changes yielding an edge in the data output, showing the data boundary in the 4x clock domain, and showing the alignment of the 1x data.

This is not really an advantage over other schemes which also depend on the data changing to obtain alignment, such as simple Manchester.

The method I described previously, with the pattern of 1 1 d0 \d0 0 0 d1 \d1 provides the same data density, and will synchronize unambiguously without regard to the data, because of the changing sync pattern. It also provides a data clock.

--

Rick C.

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[John Larkin]

Well, you can use a pokey flop like MC10EP51, or degrade yourself and
use a 1 ns cmos flop, like NC7SV74, which will set you back about 13
cents. But give up diff data+diff clock.

[John Larkin]

What I want is a PLL that is time locked to a few picoseconds
long-term and has about a ps of RMS jitter.

https://www.highlandtechnology.com/DSS/V880DS.shtml

https://www.dropbox.com/s/rb0fasr1flvvk51/NIF_Award.jpg?raw=1

The d-flop phase detector annoys some people, but nothing else comes
close.

[John Larkin]

On Sun, 7 Aug 2022 00:49:42 -0000 (UTC), Mike Monett <spa...@not.com>
wrote:

>Jeroen Belleman <jer...@nospam.please> wrote:
>
>> On 2022-08-06 19:52, John Larkin wrote:
>
>[...]
>
>>> My favorite phase detector is a single d-flop. Clock from received
>>> data, poke the local VCXO square wave into D.
>>>
>>> It makes an early/late decision every data rising edge, and can
>>> produce picosecond time alignment and picosecond jitter.
>>>
>>> It's basically infinite gain and immune to analog errors. A
>>> differential ECL flop is best, like NB7V52.
>>>
>>
>> Infinite (OK, very large) gain around the lock target and zero
>> gain elsewhere. Not something you really want in a well behaved
>> loop. You really want constant loop gain.
>>
>> Jeroen Belleman
>
>A single d-flop is a phase detector, not a frequency detector.

Yes. PLL.

It shares
>the same lock characteristic with an XOR and a double balanced mixer,
>although the XOR and DBM are quadrature detectors, where the d-flop is in
>phase.

But the dflop gain is absurdly higher than an XOR or a mixer. An XOR
with microvolt offsets makes picoseconds of time error and 1/f noise.

Diode tempco in a mixer is worse.

[Joe Gwinn]

I guess I'm not visualizing the specific circuit used.

Joe Gwinn

[John Larkin]

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net>

The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
Any 0 sees a \d.

[Ricky]

This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

Using the pattern 1 1 d1 \d1 0 0 d2 \d2 gets around this limitation and is still easy to generate, easy to decode and provides references to align the clock no matter what the data is or whether it changes. This decoder doesn't even require a separate PLL, clock timing being embedded in the data stream. A <2x clock will be able to provide a clock enable for data samples.

--

Rick C.

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[Lasse Langwadt Christensen]

I was bored so I drew it up in spice, the missing bit is generating you receiver clock from the data and resolving the half bit timing uncertainty that you can't tell where a the 4 bit 1010 starts in a long string of 1010101010101, so you'll need at least one 1001 to sync up
and that was what discussion was mostly about

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[Lasse Langwadt Christensen]

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn't really matter

[Ricky]

That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \d1 0 0 d2 \d2 pattern doesn't have this problem and is still simple to encode and decode.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

[Lasse Langwadt Christensen]

stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
the sample rate is 78.125kHz or 128us

25ns is ~8m at the speed of light

[Ricky]

But sampling data when it is changing can cause missed bits and inserted bits, neither very useful.

That's why the 1x clock has to see the data changes, to know to sample on other edges of the 4x clock.

As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

[Lasse Langwadt Christensen]

as long as the 4x is PLL'ed to the data that's not an issue

>
> As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.
>

so like this ?

d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

what edge would you use?

[Ricky]

On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:

> søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
> > As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.
> >
> so like this ?
>
> d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010

When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?


> d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.

This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

> what edge would you use?

Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock enable is generated. I would need to know more about the circuit receiving the data to give details. It's not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it's buried in the thread somewhere.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:
> On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
> > søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
> > > As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.
> > >
> > so like this ?
> >
> > d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
> When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?
>

yes

>
> > d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001
>
> Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.
>
> This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

yes that should work, encoding is a bit more effort if you have to do it in discrete logic

> > what edge would you use?
> Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
enable is generated.

ah, I wrongly assumed you'd some how skip the pll and use the data as clock

> I would need to know more about the circuit receiving the data to give details. It's not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it's buried in the thread somewhere.
>

afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

[Ricky]

On Sunday, August 7, 2022 at 6:02:18 PM UTC-4, lang...@fonz.dk wrote:
> søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:
> > On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
> > > søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
> > > > As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.
> > > >
> > > so like this ?
> > >
> > > d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
> > When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?
> >
> yes
> >
> > > d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001
> >
> > Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.
> >
> > This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.
> yes that should work, encoding is a bit more effort if you have to do it in discrete logic

Encode is idiot simple. A 3 bit counter is decoded to send the appropriate bits at the appropriate time. Again, an 8 to 1 mux and an inverter does the job. Of course, the clock is 4x the actual data rate. In gates, I think an xor, and three, 2-input NANDs, will do the job. Might need an inverter, so four, 2-input NAND gates.

> > > what edge would you use?
> > Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
> enable is generated.
> ah, I wrongly assumed you'd some how skip the pll and use the data as clock

You can. You have to use the logic output and watch for the enable to be asserted. However, because the logic is not race free, you need to design a circuit to reject glitches. But you have to have a clock to drive the shift register. If you use an arbitrary rate clock, it can be done, but the logic is a bit more. It's essentially a digital PLL.

> > I would need to know more about the circuit receiving the data to give details. It's not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it's buried in the thread somewhere.
> >
> afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

Ok.

--

Rick C.

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[Joe Gwinn]

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin

Meaning the outputs of stages 1 and 3, for a separation of two bits?

>Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
>an xnor that spans 3 bits, and slide it along the pattern.
>
>Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
>Any 0 sees a \d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate>

I have been playing with it, and I'm not getting useful detection of
the sent MDATA bits. Perhaps I'm doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


More generally, the basic topology of a correlation receiver is a
tapped delay line feeding a pattern-matching function of some kind.

So a shift register feeding a XNOR gate is in fact a kind of
correlation receiver. Because it's implemented using purely digital
logic, it will not have much tolerance of noise.

However, in the proposed application, scattered decode errors probably
have little effect on the low-passed analog signal being transmitted,
which should be the case so long as the optical SNR is large.


However, if the same thing is instead implemented using an analog
integrate-and-dump scheme (or sampled equivalent), the tolerance of
noise is dramatically increased, and can approach matched-filter
optimum. Which is why it's done that way for Ethernet.

There is also a complicated tradeoff between dispersion (various
kinds) and attenuation with distance in the fiber. Basically, up to a
point, one can overcome distortion by providing added optical power or
more sensitive optical receivers. In Ethernet, transmit optical power
is limited to ensure eye safety, so the action is largely in receiver
design. (In telcomms, transmit power may be far larger.)




Joe Gwinn

[John Larkin]

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joeg...@comcast.net>

I intend to lowpass filter it. I don't need a bit rate reduction.

[Jasen Betts]

On 2022-08-06, Ricky <gnuarm.del...@gmail.com> wrote:

> On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
>> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
>> <use...@revmaps.no-ip.org> wrote:
>>
>> >On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
>> >> Is a byte always 8 bits?
>> >
>> >no, this is why internet standards use the term "Octet" instead
>> >
>> >> What can I call a 6-bit byte? A clump?
>> >
>> >sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
>> >"Sextet" would work also.
>> >
>> >> I want to send data over an SFP optical link, in 6-bit things.
>> >
>> >> 0 1 1 0 d \d repeated, roughly 100 Mbits/sec
>> >
>> >looks like manchester encoded one bit PWM
>> Manchester is ambiguous. A string of 0s looks just like a string of
>> 1s.
>>
>> One of my guys, on his ferry ride, figured out how to add two bit
>> times
>>
>> 1 0 d \d
>>
>> to get a DC balanced form that is easy to generate and decode. It's
>> terrifyingly clever.
>

> This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

How would that matter? eventually it will resolve, and until then it
is all ones anyway, you might be off by a count of one, but coming
into the signal mid stream you are already starting from a bad position,
and this hasn't made it any worse than it would be if you could find
the frame start immediately. So just guess, if it turns out you were
wrong there's only one other choice.

This is raw delta-sigma data, so all bits are least signifigant, and
if you receive, missed, extra, or corrupted single bits it prpbably
won't have noticeable effect.

> There is nothing magical about the pattern 1 0 d \d.

Yeah, for example FM coding gets you the same features in half as many timeslots.

--
Jasen.