AD7793 again

[John Larkin]

The FAQ for this ADC is sort of terrifying:

http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf

Basically, the internal SPI state machine counts bits forever, and
deasserting CS doesn't initialize anything. If anything in the system
ever misses one clock, it's hosed forever after.

Furthermore, the ESD diodes are useless, because if they are ever
actually forward biased, the internal registers can be corrupted. That
includes the ESD diodes on the analog inputs.

We seem to be doing everything right but when it's cold, say -10C, the
SPI interface locks up maybe every 5 minutes, and only the 31-bit
reset sequence will fix it.

The obvious question is, why would anyone design such a nightmare? But
the more general question is, why are so many chips subject to bizarre
behavior when a little current flows into their ESD diodes? You'd
think that every semi house would have a mandatory ESD diode hazard
review for every product. This has been an industry problem for
decades now.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[bitrex]

John Larkin <jjla...@highlandtechnology.com> Wrote in message:

I actually live within a few miles of the Analog Devices corporate
headquarters south of Boston.

You want me to go over there and ask someone about it?

I'm only half kidding.

--


----Android NewsGroup Reader----
http://usenet.sinaapp.com/

[George Herold]

Ahh, pick another ADC.
Re: ESD and current through the diodes, Well if it's low power
then were's the current go? Do you have to build
in zeners and R's that turn on?

George H.

[John Larkin]

Yup, TI. TI understands digital better.

>Re: ESD and current through the diodes, Well if it's low power
>then were's the current go? Do you have to build
>in zeners and R's that turn on?
>
>George H.

ADI says that the ESD diodes protect the chip from damage in "handling
and production" namely when it's not being used.

They also suggest that the chip can latch up (which is generally
destructive) from about a 100 mA ESD diode spike.

[Les Cargill]

John Larkin wrote:
>
> The FAQ for this ADC is sort of terrifying:
>
> http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf
>
> Basically, the internal SPI state machine counts bits forever, and
> deasserting CS doesn't initialize anything. If anything in the system
> ever misses one clock, it's hosed forever after.
>

Holy cow.

> Furthermore, the ESD diodes are useless, because if they are ever
> actually forward biased, the internal registers can be corrupted. That
> includes the ESD diodes on the analog inputs.
>
> We seem to be doing everything right but when it's cold, say -10C, the
> SPI interface locks up maybe every 5 minutes, and only the 31-bit
> reset sequence will fix it.
>

I would find a different chip.

> The obvious question is, why would anyone design such a nightmare? But
> the more general question is, why are so many chips subject to bizarre
> behavior when a little current flows into their ESD diodes? You'd
> think that every semi house would have a mandatory ESD diode hazard
> review for every product. This has been an industry problem for
> decades now.
>
>

Beats me.

--
Les Cargill

[krw]

Don't count on it! They had a very similar problem with their 5000
series DSPs. If the I2S interface lost a clock, the channels were off
by one until the next system reset. Very ugly, since it happened
every half hour or so.

>
>>Re: ESD and current through the diodes, Well if it's low power
>>then were's the current go? Do you have to build
>>in zeners and R's that turn on?
>>
>>George H.
>
>ADI says that the ESD diodes protect the chip from damage in "handling
>and production" namely when it's not being used.
>
>They also suggest that the chip can latch up (which is generally
>destructive) from about a 100 mA ESD diode spike.

Yeah, not good. I'll have to check the ADCs we're using again.

--Keith

[Bill Sloman]

On Friday, 15 January 2016 12:22:10 UTC+11, John Larkin wrote:
> On Thu, 14 Jan 2016 16:56:02 -0800 (PST), George Herold
> <ghe...@teachspin.com> wrote:
> >On Thursday, January 14, 2016 at 6:26:57 PM UTC-5, John Larkin wrote:
> >> The FAQ for this ADC is sort of terrifying:
> >>
> >> http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf
> >>
> >> Basically, the internal SPI state machine counts bits forever, and
> >> deasserting CS doesn't initialize anything. If anything in the system
> >> ever misses one clock, it's hosed forever after.

Sounds unlikely. There has to be some kind of hard reset - it's not as if Analog Devices can manufacture it in a well-defined initial state.

> >> Furthermore, the ESD diodes are useless, because if they are ever
> >> actually forward biased, the internal registers can be corrupted. That
> >> includes the ESD diodes on the analog inputs.

This is true of pretty most ESD diodes - they work by diverting current into the substrate and once it gets into the substrate it can come out anywhere.

They aren't designed to let you operate the device outside of specification, but rather to prevent it from blowing up if some input get outside of specification.

> >> We seem to be doing everything right but when it's cold, say -10C, the
> >> SPI interface locks up maybe every 5 minutes, and only the 31-bit
> >> reset sequence will fix it.

That suggests that you aren't doing absolutely everything right. It's only got 16 pins. Have you looked at each one of them, and made sure that the voltage and impedances conform to what's called p up by the data sheet?

I know that this is teaching my grandmother to suck eggs, but lots of this kind of problem gets solved when somebody notices that something that was "obviously okay" turns out to be subtly wrong.

> >> The obvious question is, why would anyone design such a nightmare? But
> >> the more general question is, why are so many chips subject to bizarre
> >> behavior when a little current flows into their ESD diodes? You'd
> >> think that every semi house would have a mandatory ESD diode hazard
> >> review for every product. This has been an industry problem for
> >> decades now.

It's a problem if you don't know about it. I first ran into it in 1979, but if you think about where the current is going after it's been diverted by an ESD diode, it's fairly obvious that it is at liberty to mess up the rest of the circuit.

Jim Thompson could probably tell us why it's expensive to provide ESD protection any other way.

--
Bill Sloman, Sydney

[Winfield Hill]

John Larkin wrote...

>
> The FAQ for this ADC is sort of terrifying:
>
>http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf
>
> Basically, the internal SPI state machine counts bits forever,
> and deasserting CS doesn't initialize anything. If anything
> in the system ever misses one clock, it's hosed forever after.

Where does it say that? Page 7,8?


--
Thanks,
- Win

[Adrian Jansen]

On 15/01/2016 9:26 AM, John Larkin wrote:
>
> The FAQ for this ADC is sort of terrifying:
>
> http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf
>
> Basically, the internal SPI state machine counts bits forever, and
> deasserting CS doesn't initialize anything. If anything in the system
> ever misses one clock, it's hosed forever after.
>
> Furthermore, the ESD diodes are useless, because if they are ever
> actually forward biased, the internal registers can be corrupted. That
> includes the ESD diodes on the analog inputs.
>
> We seem to be doing everything right but when it's cold, say -10C, the
> SPI interface locks up maybe every 5 minutes, and only the 31-bit
> reset sequence will fix it.
>
> The obvious question is, why would anyone design such a nightmare? But
> the more general question is, why are so many chips subject to bizarre
> behavior when a little current flows into their ESD diodes? You'd
> think that every semi house would have a mandatory ESD diode hazard
> review for every product. This has been an industry problem for
> decades now.
>
>

Maybe all spice models used by chip design engineers should have a
built-in ( and unremoveable ) system which produces random 1 Kv and 1 ns
spikes on every input and output line. Then the people using the models
would have something like a real world situation to cope with.

[John Larkin]

On 14 Jan 2016 18:41:05 -0800, Winfield Hill

Pages 2 and 3 talk about corrupting registers if the analog inputs
touch the ESD diodes. The data sheet mentions this, too.

We've been testing pretty hard, and we are not banging the ESD diodes
or violating any obvious limits or timings. But if we run the
temperature down to -5 or -10C, the chip gets confused and outputs
gibberish, and warming it up doesn't fix it. It needs the reset
sequence.

That's what's so insane: one glitch or temperature excursion, and the
SPI interface gets and stays confused. CS seems to connect and
disconnect the pins, but deselecting the chip initializes no internal
states or counters.

"Faraday shield" is mentioned twice in this FAQ. "Corrupt" appears 8
times.

The last paragraph on page 2 is ominous. Blame the customer.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Chris Jones]

They do normally test the first silicon of each new chip design for both
ESD robustness and also latchup.

As for catching it at the simulation stage, a big part of the problem is
that the spice models are fitted against measurements so that they match
the measured characteristics very well, but the measurements are usually
only done within a range of "reasonable" voltages and currents,
certainly not up to 1kV. The device models do not necessarily behave
like the real devices under ESD conditions, and the designers know this.
Therefore they often get their ESD cells from a corporate "ESD group"
who are supposed to know all about this stuff somehow - perhaps by some
experiments. From the circuit designer's point of view, as long as they
have used the corporate standard cell they would be mostly off the hook
in the event of reliability problems due to ESD. Sometimes the standard
ESD cells limit performance too much (capacitance etc.) and the circuit
designer will have to do their own ones, in which case they would take
much more interest in the actual robustness, and probably do a lot of
extra testing on the first silicon.

Also substrate currents from the ESD diodes can be collected by placing
a thick wall of grounded substrate contacts around the ESD cell.
Potential latchup candidates can be kept away from ESD diodes. (e.g.
grounded n-well capacitors close to a vertical NPN with its base biased
positively is a PNPN SCR structure, as are most CMOS logic gates.) Some
designers know about these things, but sometimes management dictates
that the designer can't do their own layout and a layout engineer is
responsible for that. Often the people doing the layout don't know any
electronics but they may or may not have been given rules that may help
to prevent latchup hazards. When debugging a chip on a probe station, it
is usually easy to trigger any latchup hazards using a pulsed laser
(which is often fitted to the microscope because it is used for cutting
tracks etc.). If the laser is de-focussed (to prevent cutting anything)
and then fired at a part of the chip, it will inject carriers and
trigger any latchup hazards in that region. By going around a chip
looking for these, I was able to fix most of them one by one such that
eventually it was much harder to latch up the chip. I don't think it is
normally something people bother with, provided the chip passes the test
where they try to latch it up by injecting currents into the external pins.

[rickman]

I thought ESD diodes were to prevent damage during standard low ESD
producing handling? If the part is in a circuit, where could the
abnormal voltage be coming from?

I have seen a few parts that provide a spec on how much current is
allowed into inputs during operation, but otherwise, why would anyone
think that is an ok thing to do?

--

Rick

[Klaus Kragelund]

Burst and surge transients

Internal EMC noise

Overshoots from converters

Conducted noise from external signals

Radiated noise from other devices

etc

Cheers

Klaus

[John Devereux]

John Larkin <jjla...@highlandtechnology.com> writes:

> On 14 Jan 2016 18:41:05 -0800, Winfield Hill
> <hi...@rowland.harvard.edu> wrote:
>
>>John Larkin wrote...
>>>
>>> The FAQ for this ADC is sort of terrifying:
>>>
>>>http://www.analog.com/media/en/technical-documentation/frequently-asked-questions/AD779x_FAQ_Instru_Conv.pdf
>>>
>>> Basically, the internal SPI state machine counts bits forever,
>>> and deasserting CS doesn't initialize anything. If anything
>>> in the system ever misses one clock, it's hosed forever after.
>>
>> Where does it say that? Page 7,8?
>
> Pages 2 and 3 talk about corrupting registers if the analog inputs
> touch the ESD diodes. The data sheet mentions this, too.
>
> We've been testing pretty hard, and we are not banging the ESD diodes
> or violating any obvious limits or timings. But if we run the
> temperature down to -5 or -10C, the chip gets confused and outputs
> gibberish, and warming it up doesn't fix it. It needs the reset
> sequence.
>
> That's what's so insane: one glitch or temperature excursion, and the
> SPI interface gets and stays confused. CS seems to connect and
> disconnect the pins, but deselecting the chip initializes no internal
> states or counters.

I have seen this sort of thing when the SPI is wrongly configured, so it
is sampled on the wrong clock edge say (i.e. during a transition). Then
a temperature change speeds things up or slows them down and it goes
wrong.

"warming it up doesn't fix it" is strange but perhaps its configuration
registers get written to accidentally? Do you write to the chip
continually or just at startup?

>
> "Faraday shield" is mentioned twice in this FAQ. "Corrupt" appears 8
> times.
>
> The last paragraph on page 2 is ominous. Blame the customer.

--

John Devereux

[Tim Williams]

"Chris Jones" wrote in message news:J3%ly.447323$yN6.2...@fx17.fr7...

> When debugging a chip on a probe station, it is usually easy to trigger
> any latchup hazards using a pulsed laser (which is often fitted to the
> microscope because it is used for cutting tracks etc.). If the laser is
> de-focussed (to prevent cutting anything) and then fired at a part of
> the chip, it will inject carriers and trigger any latchup hazards in
> that region. By going around a chip looking for these, I was able to fix
> most of them one by one such that eventually it was much harder to latch
> up the chip. I don't think it is normally something people bother with,
> provided the chip passes the test where they try to latch it up by
> injecting currents into the external pins.

There was a case of peculiar latchup, let's see, it was the Raspberry Pi
board. When photographing it with flash, the power supply would conk out.

Turns out, by masking off everything but the PSU controller (which
happened to be a CSP thing), it would still fail, and masking that one
part, it was fine.

EMC is sometimes more than just "low bandwidth" (up to ~GHz) electrical
signals!

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

[mako...@yahoo.com]

It seems software people are particulary plagued by this type of thinking.
They never think about what happens to their design if something UNEXPECTED happens.

Blue screen death should be unaccepable

[mako...@yahoo.com]

On Thursday, January 14, 2016 at 11:44:04 PM UTC-5, John Larkin wrote:

try a small RC low pass filter on the clock pin to stop any glitches on the clock from counting as an extra edge.

M

[rickman]

Aren't all these design issues? They all sound like reasons to respin a
board with more protection. I know the stuff I have built had specs on
what it had to withstand and I never depended on poorly specified ESD
diodes for protection.

You didn't really answer the question. Why would you expect the ESD
diodes to protect the part while in use without problems?

--

Rick

[John Larkin]

Lots of people have confirmed that our timing is correct. Tweaking
clock and data ehges with capacitors is the usual way to spot marginal
timing, and that does nothing to the error rate.

>
>"warming it up doesn't fix it" is strange but perhaps its configuration
>registers get written to accidentally? Do you write to the chip
>continually or just at startup?

We initialize it once at startup, run it in continuous mode, and read
it out now and then. The data sheet and FAQ make it clear that if it
ever once misses one clock count, it's hosed thereafter. Deasserting
CS does not initialize anything in the SPI interface.

>
>
>>
>> "Faraday shield" is mentioned twice in this FAQ. "Corrupt" appears 8
>> times.
>>
>> The last paragraph on page 2 is ominous. Blame the customer.

--

[John Larkin]

The clock input is claimed to be Schmitted. Using a fast fet probe at
the clock input, it looks fine.

We tried adding 75 pF caps to clock, then data lines, to push the
timing left and right; no better.

[Tom Del Rosso]

Tim Williams wrote:
>
> There was a case of peculiar latchup, let's see, it was the Raspberry
> Pi board. When photographing it with flash, the power supply would
> conk out.
> Turns out, by masking off everything but the PSU controller (which
> happened to be a CSP thing), it would still fail, and masking that one
> part, it was fine.
>
> EMC is sometimes more than just "low bandwidth" (up to ~GHz)
> electrical signals!

CSP?

--

[John Larkin]

Chip Scale Package, generally a piece of silicon with solder bumps on
the bottom and little or no epoxy case.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Tom Del Rosso]

John Larkin wrote:
>
> They also suggest that the chip can latch up (which is generally
> destructive) from about a 100 mA ESD diode spike.

How often is that destructive? Several times I've had a PC or
peripheral malfunction and only removing power would fix it, even if
there was a hard reset button.

Last night I plugged my secondary monitor into my laptop and it had a
smeared picture as if the resolution or frequency was invalid. I could
change settings on the main screen and lower resolutions worked. Only
removing the battery fixed it.

--

[John Larkin]

On Fri, 15 Jan 2016 07:38:53 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"Chris Jones" wrote in message news:J3%ly.447323$yN6.2...@fx17.fr7...
>> When debugging a chip on a probe station, it is usually easy to trigger
>> any latchup hazards using a pulsed laser (which is often fitted to the
>> microscope because it is used for cutting tracks etc.). If the laser is
>> de-focussed (to prevent cutting anything) and then fired at a part of
>> the chip, it will inject carriers and trigger any latchup hazards in
>> that region. By going around a chip looking for these, I was able to fix
>> most of them one by one such that eventually it was much harder to latch
>> up the chip. I don't think it is normally something people bother with,
>> provided the chip passes the test where they try to latch it up by
>> injecting currents into the external pins.
>
>
>There was a case of peculiar latchup, let's see, it was the Raspberry Pi
>board. When photographing it with flash, the power supply would conk out.
>
>Turns out, by masking off everything but the PSU controller (which
>happened to be a CSP thing), it would still fail, and masking that one
>part, it was fine.
>
>EMC is sometimes more than just "low bandwidth" (up to ~GHz) electrical
>signals!

Several terahertz.

>
>Tim

Windowed eproms had that issue, too.

Some opamps have optical DC offset.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[rickman]

There are so many things with PCs that are designed poorly that you
don't need to invoke an ESD caused latchup to explain it. My Lenovo is
terrible in that regard with the battery being reported as missing only
getting straight by pulling it out and reinserting it and many other
problems.

--

Rick

[John Larkin]

One school of thought is that nothing should ever go wrong in a
digital system, so one shouldn't expect a gadget to survive missing
even one clock, once. After all, the program counter of a computer
doesn't count wrong, and the system crashes if it ever does.

Inside an FPGA, we often assume that nothing will ever be done wrong,
in things like state machines or sinc filters. An ADC chip, with a
shared SPI interface, and flakey ESD diodes, and flakey temperature
behavior, is another matter. No harm would have been done if
de-asserting CS were to reset the SPI machine.

--

John Larkin Highland Technology, Inc

[rickman]

I remember several decades ago when LCCs were a popular option, a
colleague was working with a quite brilliant scientist to explore new
packaging methods. They were already using solder bumps which require
"large" pads for the solder. The chip makers didn't like the "waste" of
silicon area, so they didn't get used in anything but military designs
for another decade or two. I guess there was no push for such levels of
miniaturization until cell phones came out. Even in DoD stuff the
contractors preferred hybrids because they were already geared up for
that.

--

Rick

[rickman]

I believe you said there is a data related reset function, right? So
clearly they did give this consideration. The only difference is
whether you reset at the end of every transaction (which does not fix
the problem completely because you still may have one corrupt
transaction) or only when you detect the problem and send the reset
sequence.

In most cases there won't be significant difference in disruption of
system operation whether it is one transaction or 100 that is corrupted.

You should talk to ADI about the temperature thing and forget the idea
of ESD diodes being useful in circuit unless you stay within spec. To
deal with your transient problem, you can always add your own limit
diodes externally along with a small series resistor to the IO pin which
should prevent the possibility of the ESD diodes being a problem.

Consider the millions of AD7793 parts they ship and ask yourself if the
problem is you or the chip? Better, ask ADI.

--

Rick

[Les Cargill]

If the SPI state machine does not reliably "state machine", you
can no longer trust the part and I'd just as soon not go beyond that.

I suppose you could put Vcc on an I/O pin or as an output from an FPGA,
but that's indecent.

>
>>
>> "Faraday shield" is mentioned twice in this FAQ. "Corrupt" appears 8
>> times.
>>
>> The last paragraph on page 2 is ominous. Blame the customer.
>

--

Les Cargill

[Les Cargill]

BSD is exactly how a software system should behave when presented with
unwinnable state.

It's "Ah canna change th' laws of physics, cap'n." done loudly.

--
Les Cargill

[John Larkin]

On Fri, 15 Jan 2016 12:41:54 -0500, "Tom Del Rosso"
<fizzbin...@that-google-mail-domain.com> wrote:

>John Larkin wrote:
>>
>> They also suggest that the chip can latch up (which is generally
>> destructive) from about a 100 mA ESD diode spike.
>
>How often is that destructive? Several times I've had a PC or
>peripheral malfunction and only removing power would fix it, even if
>there was a hard reset button.

If there's enough power supply amps available, SCR latchup is
generally destructive. The 'a' series 4000 CMOS logic was notorious
for latchup. Modern HC-type logic is a lot less sensitive, but few
semi processes claim to be latchup-free. If you're lucky, a data sheet
will specify some allowable ESD diode current that won't trigger
latchup.

Mixed-signal parts seem to be more sensitive to latchup than pure
analog or digital parts, seems to me.

Oh, I think we fixed the product with the AD7793: we added a 75 pF cap
from the ADC SPI clock pin to ground. We're going to temperature cycle
it all weekend and verify the fix. The longer term fix is to use a TI
part.

Some guy rang the doorbell this afternoon. It was a TI FAE sort of
knocking on doors at random. He was too late to buy us lunch, so he'll
have to come back.

[John Larkin]

You can send it a stream of 31 1's, which resets everything in,
depending on the paragraph you believe, 500us or 1 ms.

I think we'll do the capacitor kluge, and also read the status and
chip ID registers after every conversion. If they don't look right,
we'll ignore that ADC data and reset the chip.

We can expect the ID register to conveniently display the hex value
0xXB.

All ugly.

[Lasse Langwadt Christensen]

that the capacitor works could suggest that you are using the wrong
clock edge

-Lasse

[John Larkin]

Yes, but the waveforms look exactly like the data sheet.

It was once observed that bad data was coming out on the wrong clock
edge, after it was run cold.

[Tim Wescott]

On Thu, 14 Jan 2016 15:26:44 -0800, John Larkin wrote:

> The FAQ for this ADC is sort of terrifying:
>
> http://www.analog.com/media/en/technical-documentation/frequently-asked-
questions/AD779x_FAQ_Instru_Conv.pdf
>
> Basically, the internal SPI state machine counts bits forever, and
> deasserting CS doesn't initialize anything. If anything in the system
> ever misses one clock, it's hosed forever after.

Thank you for this post. Yesterday, when I noticed that my smart(?)
phone wasn't receiving, even though it was right next to a cell phone
tower, it occurred to me that rather than just resetting the processor, I
should power the thing down and back up.

And voila -- it worked.

Maybe you could make "chip select" for the ADC power it down entirely?

--
www.wescottdesign.com

[John Larkin]

On Sat, 16 Jan 2016 12:24:02 -0600, Tim Wescott <t...@seemywebsite.com>
wrote:

All sorts of gadgets hang up and need to be power cycled to fix them.

There is a serial command to the ADC to reset everything; send it 32
1's. I guess we should do that now and then, to unfreeze it if it
messes up. But then we'll have occasional transient errors instead of
permanent errors.

[krw]

On Sat, 16 Jan 2016 11:35:35 -0800, John Larkin
<jjla...@highlandtechnology.com> wrote:

>On Sat, 16 Jan 2016 12:24:02 -0600, Tim Wescott <t...@seemywebsite.com>
>wrote:
>
>>On Thu, 14 Jan 2016 15:26:44 -0800, John Larkin wrote:
>>
>>> The FAQ for this ADC is sort of terrifying:
>>>
>>> http://www.analog.com/media/en/technical-documentation/frequently-asked-
>>questions/AD779x_FAQ_Instru_Conv.pdf
>>>
>>> Basically, the internal SPI state machine counts bits forever, and
>>> deasserting CS doesn't initialize anything. If anything in the system
>>> ever misses one clock, it's hosed forever after.
>>
>>Thank you for this post. Yesterday, when I noticed that my smart(?)
>>phone wasn't receiving, even though it was right next to a cell phone
>>tower, it occurred to me that rather than just resetting the processor, I
>>should power the thing down and back up.
>>
>>And voila -- it worked.
>>
>>Maybe you could make "chip select" for the ADC power it down entirely?
>
>All sorts of gadgets hang up and need to be power cycled to fix them.

Particularly gadgets heavily relying on software.

>
>There is a serial command to the ADC to reset everything; send it 32
>1's. I guess we should do that now and then, to unfreeze it if it
>messes up. But then we'll have occasional transient errors instead of
>permanent errors.

We had to do that in the widget that used the TI 5K DSP. We used a
spare CODEC wrapped on itself to detect when the channels were out of
sync and then reset the DSP rather than glitch the system regularly.
It's not a good solution, to be sure, but that's the solution
management wanted (my suggestion was to do the I2S/TDM interface the
right way, in a CPLD or FPGA).

[RBlack]

On Fri, 15 Jan 2016 21:00:37 -0800, John Larkin
(jjla...@highlandtechnology.com) said:
> On Fri, 15 Jan 2016 12:41:54 -0500, "Tom Del Rosso"
> <fizzbin...@that-google-mail-domain.com> wrote:
>
> >John Larkin wrote:

[snip]

>
> Oh, I think we fixed the product with the AD7793: we added a 75 pF cap
> from the ADC SPI clock pin to ground. We're going to temperature cycle
> it all weekend and verify the fix. The longer term fix is to use a TI
> part.
>

We had exactly this problem with another AD part, a DDS chip. There
were 3 of them on the PCB, all driven by separate SPI controllers in an
FPGA. The problem was worst on the one furthest from the FPGA, trace
length was a few inches.
Adding the cap to ground on the SCLK pin fixed it, we source terminated
all the outputs from the FPGA (used 33R IIRC) for good measure.

And yes, the SPI-registers side of the DDS chip was a nightmare to
figure out. It took multiple tech support requests to discover basic
stuff which should have been in the data sheet, like how to cleanly re-
initialise the chip in software. Sending the commands in the wrong
sequence would lock the chip up and require a power-cycle.
Our latest spin of this board has designed this part out. I wonder if
AD know or care that this stuff loses them business?

[John Larkin]

On Mon, 18 Jan 2016 10:33:09 -0000, RBlack <ne...@rblack01.plus.com>
wrote:

They do the analog parts of their chips very well, and the digital
parts are horrors.

[Phil Hobbs]

Hence the name. ;)

I used to have an old AD databook with a FAQ. One entry read something
like:

"Digital: You've got to be joking. See the name."

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net