Low noise, high bias voltage on picoAmp TIA's input, howto?

[timo.k...@ibtk.de]

Dear all,

at first I want to thank all the experienced guys, Phil, Winfield, Gerhard... who share their valuable knowledge. That helps a lot! Thank you!
I'm working at a Helmholtz facility in Germany/Dresden on equipment used in fundamental research.

To measure e- and ion beam currents down to sub-pA I built up Fameio, a module including TIA (9 decadic ranges), diffamp, ADC/DAC, supplies, bias -200V to +200V:
https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
The variable 2mA current limited bias, which has to sit on the measuring tip (in relation to GND), is a deadly for the TIA input in the case of Triax cabling errors (shorts).
The TIA is very sensitive to bias noise, if the bias node is not perfectly AC-coupled to the front-ends OPA supply. As well as any differences between its +in and Guard_ext couple into the measured signal due to the cable capacitance.
For lowering the noise I will throw out the iseg modules and use a Royer.

Question:
I'd like to have a more robust bias-solution.
I thought about photocouplers to feed the DC voltage in series to the TIA tip directly, it's open voltage is nice (30V) but the current is way too low (Isc=4uA).
It could be possible to use an DCDC instead the same way, but it may be challenging due to the needs of isolation, screening and guarding.

Any idea would be appreciated.
Thank you very much!
Cheers, Timo

[Bill Sloman]

On Friday, May 21, 2021 at 10:08:25 PM UTC+10, timo.k...@ibtk.de wrote:
> Dear all,

> For lowering the noise I will throw out the iseg modules and use a Royer.

If you want a DC-DC converter, think about using a a Baxandall reseonant Class-D inverter rather than Royer.

The problem with square wave inverters are the switching spikes, and Baxanadall resonant inverters switch more smoothly.

You still have to worry pumping capacitative currents across isolation barriers, but there's less high-frequency trash around.

Peter Baxandall invented the circuit back in 1959, but he published it in a British journal and Americans didn't know about it. Jim Williams eventually picked it up and ran with it, but clearly didn't know where it came from. He first mentioned it in the Linear Technology application note AN-45 which is dated as June 1991, and but AN49, AN51, AN55, AN61, AN65 concentrate on using it to generate high voltages to drive cold-cathode back-lights.

http://sophia-elektronica.com/Baxandall_parallel-resonant_Class-D_oscillator1.htm

has a link to Peter Baxandall's original paper, and some of my own variations on the circuit.

--
Bill Sloman, Sydney

[timo.k...@ibtk.de]

Hello,

Bill Sloman schrieb am Freitag, 21. Mai 2021 um 15:25:53 UTC+2:
> If you want a DC-DC converter, think about using a a Baxandall reseonant Class-D inverter rather than Royer.

Oh yes, I did not know about Baxandall, nevertheless I used it already (and mixed the names, excuse me, please).
A magic circuit, started below 1V(!) and worked nicely to 30V on my bench...
Please see the updated link, I added it's first simulations and measures (in German):
https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
The AN118 helped a lot. Thank you for the additional hints! I did not know the great AN65 for example.
One additional restriction is the allowable height below 10mm on the module's bottom side, so the core has to remain small.

> You still have to worry pumping capacitative currents across isolation barriers, but there's less high-frequency trash around.

If the circuit stays inside the module, these currents are not harmful. The bias generation is GND-related.
It will be a problem, if located outside, in series to the TIA input. So the first option still seems to be easier.

I'll have to go through the information you provided, thank you!

Cheers, Timo

[Chris Jones]

I don't think connecting the bias voltage in series with the input pin
is very practical - the voltage source would have to be very small
physically in order to avoid excessive capacitance. If a
transformer-based DC-DC converter were used, it would also be hard to
get the inter-winding capacitance small enough to not suffer from
interference from the AC voltage on the windings, even with quite
careful screening. A photovoltaic device (perhaps driving a step-up
autotransformer) might be ok, if it is small enough, but I think your
existing approach is better.

Anyway, I don't think that putting the voltage source in series with the
input terminal has any advantage for the robustness against damage when
the input is short-circuited, as the bias will still appear at the
amplifier input. To make it more robust, I think you need to add more
series resistance (perhaps with some measures to stop that from causing
degraded performance) and/or add more protection diodes (which should be
chosen carefully and operated at zero bias).

From what I can see, it looks like you have floated the entire
front-end at the bias voltage, including the shield cans (which would
minimise collection of current from ions generated in the air inside the
shield can). This is what I would have done. I presume that the power
supplies for the op-amps are provided by DC-DC converters with their
outputs referenced to the bias voltage. I could not find any diagram of
the front-end that included the isolated power supplies, and the power
pins of the op-amps seem to be hidden so I can't really tell what you
have connected them to.

It seems to me that you would need an instrumentation amplifier to shift
the signal to be ground-referenced. I guess U7A is doing that, but I
don't know what part number U7A is as it isn't labelled. If it is a
difference amplifier then I can't understand why you connect the
feedback resistor to its output (ground-referenced) rather than to the
output of U5A.

I do wonder whether it is worth considering replacing the switchable
feedback resistors by a p-n junction (a diode-connected transistor, JL
and PH could suggest one with low leakage and good log-conformance) and
then digitising the result of that (as well as a replica diode at the
same temperature and known current). That way you get a voltage
proportional to kt/q log the current ratio. Whilst I would not expect
much better than 5% accuracy that way, it might still be better than the
tolerance of a 1 Teraohm resistor, and removes the need for
auto-ranging, relays etc.

[timo.k...@ibtk.de]

Hello Chris,
thank you for the hints!

Chris Jones schrieb am Montag, 24. Mai 2021 um 11:59:35 UTC+2:

> If a transformer-based DC-DC converter were used,
> it would also be hard to get the inter-winding
> capacitance small enough to not suffer from interference
> from the AC voltage on the windings, even with quite careful screening.

Here are some interesting ideas to minimise the coupling capacitance:
https://www.eevblog.com/forum/metrology/power-supply-for-voltage-references/

> ...floated the entire front-end at the bias voltage,
> including the shield cans...

Yes, at first. But it measured ungly, maybe due to the "non-optimum" layout.
So I put the inner shield back to GND with reasonable results - on the bench.

Yes, the bias drives the common and the supplies of the floating DCDC used
for all the OPAs related to the TIA, to bee seen at p. 13 of the document:
20210316_SuperSIMS_FAMEIO_MV40-Ersatz_Praesentation_Kirschke.pdf.

The U7-A at p10 is an INA149, a TI HV-Diffamp. I like to simplify the structure a bit,
omitting the composite amp. It's power is GND-referenced, of course.
But it's input draws already ~0,5mA from bias and ~0.5mA from the TIA's output.
Because the bias current possibly available at any in/out of the module must be
limited to remain <3mA under all conditions for safety purposes,
all power sinks should be kept at minimum.

Yes, the INAout-connection is a mistake, it is really connected to R107
(U6-B: composite, to bring the voltage to +/-10V inside the loop,
lowering the noise a bit). As well as the schematic was not actualised
after correcting all the failures. Excuse me please.
The schematics, layouts and production are done by our technicians,
sometimes the information flow is not good enough. So my second job
for troubleshootimg remains necessary. ;)

> ...replacing the switchable feedback resistors by a p-n junction...

Our "customer" physicists asked for an idea of such a version, so I simulated one, see
20210522_FAMEIO_SuperSIMS-MV40-Ersatz_S45-46.pdf
which document was added to the link above.
But it's still not realised by them, will take some additional weeks.
For our purposes we'd like to get some more reliable accuracy at least at the higher ranges.
We bought the resisors at SRT-Restech, the 1T in 2512 has 5% TK250, you're right.
But the range _could_ be calibrated digitally, if necessary.
But the log-idea itself is really good, i believe.
On the other hand I do not have any practical experience with logamps...

Thank you!
Cheers, Timo

[Chris Jones]

On 24/05/2021 21:14, timo.k...@ibtk.de wrote:
> Hello Chris,
> thank you for the hints!

Sorry I didn't have time to read your documents more thoroughly before
replying so I missed some things you had already provided.

>
> Chris Jones schrieb am Montag, 24. Mai 2021 um 11:59:35 UTC+2:
>
>> If a transformer-based DC-DC converter were used,
>> it would also be hard to get the inter-winding
>> capacitance small enough to not suffer from interference
>> from the AC voltage on the windings, even with quite careful screening.
>
> Here are some interesting ideas to minimise the coupling capacitance:
> https://www.eevblog.com/forum/metrology/power-supply-for-voltage-references/

Thanks!

I have to do something like this, I would use two cascaded toroidal
transformers, on opposite sides of a metal wall with two holes in it,
each toroidal core having its axis of symmetry parallel to the plane of
the wall. The first transformer would have many turns primary : 2 turns
secondary, and the ends of the 2-turn winding would pass through the
holes in the metal wall. On the other side, there would be the other
transformer with 2 turns primary to many turns secondary. The centre-tap
of one 2-turn winding would be grounded to the metal wall so that the
wires passing through the wall have equal and opposite voltages on them.
Even with this arrangement and with PTFE insulated wire, I would not
expect it to be useful below nanoampere signal levels unless I could
arrange for the transformer operating frequency to be so far above the
frequency of any wanted signals that it could be filtered out very well.

>
>> ...floated the entire front-end at the bias voltage,
>> including the shield cans...
>
> Yes, at first. But it measured ungly, maybe due to the "non-optimum" layout.

I can't understand why that would happen, but it might be interesting to
investigate it further, as I think that the problems are more likely to
be ones that can be solved than with the other approach.

> So I put the inner shield back to GND with reasonable results - on the bench.

But I presume with zero bias....

> Yes, the bias drives the common and the supplies of the floating DCDC used
> for all the OPAs related to the TIA, to bee seen at p. 13 of the document:
> 20210316_SuperSIMS_FAMEIO_MV40-Ersatz_Praesentation_Kirschke.pdf.
>
> The U7-A at p10 is an INA149, a TI HV-Diffamp. I like to simplify the structure a bit,
> omitting the composite amp. It's power is GND-referenced, of course.
> But it's input draws already ~0,5mA from bias and ~0.5mA from the TIA's output.
> Because the bias current possibly available at any in/out of the module must be
> limited to remain <3mA under all conditions for safety purposes,
> all power sinks should be kept at minimum.

It might be interesting to float the ADC and just transfer the digital
result from the vbias-referenced ADC to the rest of the system with an
optocoupler or one of the newer equivalent transformer or capacitive
coupler devices. Especially since you are not going to get super-high
accuracy with teraohm resistors, the ADC and voltage reference might as
well be cheap ones (even the built-in ones of a microcontroller) so
there is less incentive to share one expensive reference + ADC amongst
multiple channels.

>> ...replacing the switchable feedback resistors by a p-n junction...
>
> Our "customer" physicists asked for an idea of such a version, so I simulated one, see
> 20210522_FAMEIO_SuperSIMS-MV40-Ersatz_S45-46.pdf
> which document was added to the link above.
> But it's still not realised by them, will take some additional weeks.

Perhaps you can have a try at home. Sometimes it is faster and if it is
promising then you can guide them to replicate it at work.

> For our purposes we'd like to get some more reliable accuracy at least at the higher ranges.
> We bought the resisors at SRT-Restech, the 1T in 2512 has 5% TK250, you're right.

Thanks for that info. I did not even really know where to get ones that
good, I think mine are 30% or worse, even before I take them out of the
packet.

> But the range _could_ be calibrated digitally, if necessary.
> But the log-idea itself is really good, i believe.
> On the other hand I do not have any practical experience with logamps...

Nor do I. I think the main challenges would be bandwidth variation and
getting the compensation right for all current levels, as well as
getting good accuracy in spite of temperature gradients and poor log
conformance at high currents. If the input current signal has a high
peak-to-average ratio and higher bandwidth than the circuit, then such a
scheme might also suffer from the same problem as older spectrum
analysers where one can measure "the average of the log of the signal"
which is not the same as "the log of the average of the signal" that one
would prefer to measure.

[Bill Sloman]

On Monday, May 24, 2021 at 10:23:28 PM UTC+10, Chris Jones wrote:
> On 24/05/2021 21:14, timo.k...@ibtk.de wrote:

<snip>

> > But the log-idea itself is really good, i believe.
> > On the other hand I do not have any practical experience with logamps...

I've used them, and they do work. Bob Pease has published quite a bit on the practical problems.

Setting up a circuit where an op amp makes the voltage at the collector is the same as the at the base can give you good logarithmic behavior over about seven orders of magnitude.

"The Art of Electronics" makes the point in fig 2.41 in the third edition, 2.39 in the second edition.

> Nor do I. I think the main challenges would be bandwidth variation and getting the compensation right for all current levels, as well as getting good accuracy in spite of temperature gradients and poor log conformance at high currents.

If you use one half of a monolithic pair of transistors as your logging device, temperature compensation can be pretty accurate. The voltage drop in the base resistance can be a problem at higher currents, but you can compensate it out if you monitor the base current and correct for the drop - I worked with hyperboloc function generator which did that.

> If the input current signal has a high peak-to-average ratio and higher bandwidth than the circuit, then such a scheme might also suffer from the same problem as older spectrum analysers where one can measure "the average of the log of the signal" which is not the same as "the log of the average of the signal" that one would prefer to measure.

That's always a problem with non-linear circuits.

--
Bill Sloman, Sydney

[timo.k...@ibtk.de]

Chris Jones schrieb am Montag, 24. Mai 2021 um 14:23:28 UTC+2:
Hello Chris,
> Sorry I didn't have time to read your documents...

You couldn't do that, because I added some afterwards. ;)

> I have to do something like this, I would use two cascaded toroidal

> transformers...

That sounds very interesting.
Are you sure, that toroidals are best-suited with respect to their stray field? Years ago I read anywhere, they're not, I believe from Bruno Putzeys.
So the best classD-Amp modules (as far as I know) have RM-cores instead of toroidals. See here (lower left):
https://ibtk.de/project/amplifier/Power-Amp/Fotos/20191004_Power-Amp_4xNC252MP_open_IMG_2149_1k.jpg
The cap coupling could be worse, don't know...

> I would not
> expect it to be useful below nanoampere signal levels unless I could
> arrange for the transformer operating frequency to be so far above the
> frequency of any wanted signals that it could be filtered out very well.

I'm lucky to have just this case. The (higher) currents to be measured are well below 10kHz, the rest will be 4th order lowpassed before the ADC, the (sine driven) transformer will be ~100kHz or above.

> > So I put the inner shield back to GND with reasonable results - on the bench.
> But I presume with zero bias....

For a short period with bias too. Very noisy, but seemed to be stable. And when I switched off the bias, it's 1uF buffer cap put the charge into the +In of the ADA4530-1. One shot only. Expensive and sometimes hard to get...
The layout is a little bit complex, the Rogers is sensitive to multiple times soldering, there are some more Guard-related mistakes, so went back to design a more robust version, hopefully.

> It might be interesting to float the ADC and just transfer...

It would throw out the INA at least, worth to think about, thanks.

Maybe I find the chance to build up a log version too...

I added the offer list from SRT to the small website, if you are interested.

Thank you!
Cheers, Timo

[timo.k...@ibtk.de]

Hello,

Thank you Bill, for your hints!
I will study the AoE chapters.
So it seems to be worth an practical try.

Cheers, Timo

[Bill Sloman]

On Tuesday, May 25, 2021 at 12:10:50 AM UTC+10, timo.k...@ibtk.de wrote:
> Chris Jones schrieb am Montag, 24. Mai 2021 um 14:23:28 UTC+2:
> Hello Chris,
> > Sorry I didn't have time to read your documents...
>
> You couldn't do that, because I added some afterwards. ;)
> > I have to do something like this, I would use two cascaded toroidal
> > transformers...
>
> That sounds very interesting.
>
> Are you sure, that toroidals are best-suited with respect to their stray field? Years ago I read anywhere, they're not, I believe from Bruno Putzeys.

Toroidal transformers have no stray field, if they are non-progressively wound.

If you just wind wire around the toroid, you end up with a turn in the plane of the toroid, and you have to organise the winding to avoid this. One scheme is to wind clockwise half-way around the toroid, then wind back anticlockwise all the way around the toroid - eventually going over the top of the first winding - and then wind back anticlockwise over the top of the second layer until you get to your original starting point.

I first found out about this by reading

https://www.amazon.com/Coaxial-AC-Bridges-B-Kibble/dp/0852743890

The Kibble involved is the one remembered in the Kibble Balance. Later, I looked at using a pair stacked toroids to measure the conductivity of a fluid, and that only works if both coils are non-progressively wound.

> So the best classD-Amp modules (as far as I know) have RM-cores instead of toroidals. See here (lower left):
> https://ibtk.de/project/amplifier/Power-Amp/Fotos/20191004_Power-Amp_4xNC252MP_open_IMG_2149_1k.jpg

Toroids are a pig to wind. There are special machines for the job, but RM core parts are a lot easier to put together in production.

Pot cores (and RM cores are particular sort of pot core ) don't have much stray field. Topologically they are the inverse of the toroid - you wrap the core material around the winding, rather than the winding around the core - but the slots to let the wires out means that they aren't as perfect as a toroid.

<snip>

--
Bill Sloman, Sydney

[jla...@highlandsniptechnology.com]

If you ever need a really low noise floating voltage or current
source, consider a PV photodiode. Good for maybe 9 volts and 10s of
uA.

The next best is maybe the Murata dc/dc converters, but still pretty
noisy.

https://www.dropbox.com/s/0e9lzg2fcbhsd04/Murata_7.jpg?raw=1

I needed about a watt there, but it adds a lot of jitter, so I use the
off-the-board option.



--

John Larkin Highland Technology, Inc

The best designs are necessarily accidental.

[Gerhard Hoffmann]

Am 24.05.21 um 17:47 schrieb jla...@highlandsniptechnology.com:

>
> If you ever need a really low noise floating voltage or current
> source, consider a PV photodiode. Good for maybe 9 volts and 10s of
> uA.

Yes, I wanted to propose a small flock of
< https://www.digikey.de/products/de?keywords=VO1263 >
or similar.
I have used similar ones for BF862 or CE3520K3 bias.

Alternatively rising the frequency of the DC/DC above
the frequency band of interest, where it can easily be filtered.

At 400 mW you can probably do great things with
LC step-up networks or these Macom wideband transformers.

Cheers, Gerhard

[John Larkin]

On Mon, 24 May 2021 18:10:48 +0200, Gerhard Hoffmann <dk...@arcor.de>
wrote:

We have used audio-type transformers, driven by sine waves, as fairly
quiet floating power supplies. Low frequency gives less coupled AC
current and no spikes.

I think I've seen that done in SMU's, with a custom shielded
transformer.

[Chris Jones]

On 25/05/2021 00:10, timo.k...@ibtk.de wrote:
>> I have to do something like this, I would use two cascaded toroidal
>> transformers...
> That sounds very interesting.
> Are you sure, that toroidals are best-suited with respect to their stray field? Years ago I read anywhere, they're not, I believe from Bruno Putzeys.
> So the best classD-Amp modules (as far as I know) have RM-cores instead of toroidals. See here (lower left):
> https://ibtk.de/project/amplifier/Power-Amp/Fotos/20191004_Power-Amp_4xNC252MP_open_IMG_2149_1k.jpg
> The cap coupling could be worse, don't know...
>

I meant to write "if I had to do something like this". I haven't though
about it enough yet though. I agree that RM cores might be just as good
or better than toroids, and I now realise that making one winding have
only a couple of turns and operate at very low, balanced voltage is of
limited benefit unless the other winding also has only a couple of turns
with little voltage between them. (Or, if it has more turns with more
voltage between parts of it, it will need excellent screening against
capacitive coupling.)

It is strange that as far as I know there isn't any off-the-shelf DC-DC
converter for instrumentation, with a well screened transformer and
quiet drive circuit.

[timo.k...@ibtk.de]

Bill Sloman
24.05.2021, 17:11:16 (gestern)

> Toroidal transformers have no stray field, if they are non-progressively wound.

Didn't here about that, so I have to learn a bit.

> https://www.amazon.com/Coaxial-AC-Bridges-B-Kibble/dp/0852743890

$900 and up? Hmmm...
Beginning from p.101 it's of practical interest. Thank you!
All that stuff is important, if the "DCDC" powers the bias, which is inserted before the TIA.
If I can place it on the bottom of the PCB and let drive bias the preamp reference similar to the recent situation, the radiated field is of much less concern, at least I hope that.

jla...@highlandsniptechnology.com
24.05.2021, 17:48:05 (gestern)

> If you ever need a really low noise floating voltage or current
> source, consider a PV photodiode. Good for maybe 9 volts and 10s of uA.

Gerhard Hoffmann
24.05.2021, 18:10:54 (gestern)
> Yes, I wanted to propose a small flock of...VO1263...

Thanks, looks a lot better than the Toshiba TLP3924.

> The next best is maybe the Murata dc/dc converters, but still pretty
> noisy.

I'm a little bit done with DCDC modules. Most of them do not specify no load in currents. So I was surprised about the ~8W power consumption of the Fameio module, containing 5 DCDCs. The TDKs consume ~30mA @24V each!
I tested a LT8302 flyback with EFD15, it's Iq was ~2mA, the efficiency >80%, which is okay. Additionally it produces all needed voltages from _one_ flyback, except the bias. Because there are linear regs afterwards, this seems to be the better solution.

If I could drive the Baxandall sine converter to efficiencies significantly above 50%, this one could produce all voltages.

> Alternatively rising the frequency of the DC/DC above
> the frequency band of interest, where it can easily be filtered.

That's already the case: 100kHz power supply >> 10kHz max to be measured.

> At 400 mW you can probably do great things with
> LC step-up networks or these Macom wideband transformers.

That principle looks interesting, I did not know of it before. But still seems to use square drive instead of sine?

> We have used audio-type transformers, driven by sine waves...

The "lower end" would be a mains transformer, followed by a Delon circuit. Yes, very simple.
All these are followed by at least one rectifier which produces noise.
And if the frequency rises, trr becomes visible.
https://ibtk.de/project/hzdr/Fameio-presentation/20210522_FAMEIO_SuperSIMS-MV40-Ersatz_S38-39.pdf
The STTH112UFY shows it in Abb. 7.21 (without installed parallel caps).
The smallest SiC devices seem to be for 2A, big and with high Cj.
Is there another small (Schottky?) diode without or very low reverse recovery for >500V?

Chris Jones
13:25 (vor 1 Stunde)

> It is strange that as far as I know there isn't any off-the-shelf DC-DC
> converter for instrumentation, with a well screened transformer and
> quiet drive circuit.

I fear you're right...

Thank you!
Cheers, Timo

[Bill Sloman]

On Tuesday, May 25, 2021 at 10:54:45 PM UTC+10, timo.k...@ibtk.de wrote:
> Bill Sloman
> 24.05.2021, 17:11:16 (gestern)
> > Toroidal transformers have no stray field, if they are non-progressively wound.
> Didn't here about that, so I have to learn a bit.
>
> > https://www.amazon.com/Coaxial-AC-Bridges-B-Kibble/dp/0852743890
>
> $900 and up? Hmmm...
> Beginning from p.101 it's of practical interest. Thank you!
> All that stuff is important, if the "DCDC" powers the bias, which is inserted before the TIA.
> If I can place it on the bottom of the PCB and let drive bias the preamp reference similar to the recent situation, the radiated field is of much less concern, at least I hope that.
>
> jla...@highlandsniptechnology.com
> 24.05.2021, 17:48:05 (gestern)
> > If you ever need a really low noise floating voltage or current
> > source, consider a PV photodiode. Good for maybe 9 volts and 10s of uA.
> Gerhard Hoffmann
> 24.05.2021, 18:10:54 (gestern)
> > Yes, I wanted to propose a small flock of...VO1263...
>
> Thanks, looks a lot better than the Toshiba TLP3924.
> > The next best is maybe the Murata dc/dc converters, but still pretty
> > noisy.
> I'm a little bit done with DCDC modules. Most of them do not specify no load in currents. So I was surprised about the ~8W power consumption of the Fameio module, containing 5 DCDCs. The TDKs consume ~30mA @24V each!
> I tested a LT8302 flyback with EFD15, it's Iq was ~2mA, the efficiency >80%, which is okay. Additionally it produces all needed voltages from _one_ flyback, except the bias. Because there are linear regs afterwards, this seems to be the better solution.
>
> If I could drive the Baxandall sine converter to efficiencies significantly above 50%, this one could produce all voltages.

Jim Williams - in his Linear Technology application notes N49, AN51, AN55, AN61, and AN65 - was getting around 92% efficiency.The Baxandall Class-D inverter is pretty good. If you want a a better sine wave my variation on it is only about 50% efficient.

> > Alternatively rising the frequency of the DC/DC above
> > the frequency band of interest, where it can easily be filtered. That's already the case: 100kHz power supply >> 10kHz max to be measured.
> > At 400 mW you can probably do great things with
> > LC step-up networks or these Macom wideband transformers.
> That principle looks interesting, I did not know of it before. But still seems to use square drive instead of sine?
>
> > We have used audio-type transformers, driven by sine waves...
>
> The "lower end" would be a mains transformer, followed by a Delon circuit. Yes, very simple.
> All these are followed by at least one rectifier which produces noise.

Synchronous rectifiers, with properly driven MOSFet switches, are much quieter.

<snip>

> > It is strange that as far as I know there isn't any off-the-shelf DC-DC converter for instrumentation, with a well screened transformer and quiet drive circuit.

It's not a big market. It's been around since Ralph Morrison wrote the first edition of "Grounding and Shielding Techniques in Instrumentation" back in 1967 - I read it back then, but the copy on my bookshelf is the 4th edition from 1998 - but it isn't a mass market.

--
Bill Sloman, Sydney

[whit3rd]

On Tuesday, May 25, 2021 at 4:25:56 AM UTC-7, Chris Jones wrote:

> It is strange that as far as I know there isn't any off-the-shelf DC-DC
> converter for instrumentation, with a well screened transformer and
> quiet drive circuit.

The drive (for a DC low-ripple output) would best be a triangle wave, so
the rectifiers after the transformer only make a short blip twice per cycle.
Some square-triangle generation schemes make a small step at the
turnover, which can be tuned to be the same as the forward voltage step
required to turn on the rectifiers.

That makes for a relatively quiet conversion, but it's not energy-efficient,
which is why it's not similar to the non-instrumentation DC/DC conversion
we see in mass-produced items.

[timo.k...@ibtk.de]

Bill Sloman
> Coaxial-AC-Bridges-B-Kibble
Found it in the web, thank you!

> Jim Williams - in his Linear Technology application notes N49, AN51, AN55, AN61, and AN65 - was getting around 92% efficiency.

Ahh, I see, it looks good. It seems to be very dependent on the core and it's winding numbers (not only).
Unfortunately I'm restricted concerning the transformer's height to remain below 10mm, so I am fiddling with the small EFD15. Gives up to 80% over all in LTSpice now...

> The Baxandall Class-D inverter is pretty good. If you want a a better sine wave my variation on it is only about 50% efficient.

Maybe I did not understand what means "Baxandall Class-D inverter". Is it the Baxandall oscillator driven/regulated by a classD- or simply a PWM-switcher?
Tight regulation is not necessary in my case, so the constant input voltage and the relatively constant conversion ratio should be sufficient.

> Synchronous rectifiers, with properly driven MOSFet switches, are much quieter.

Is that trua in the case of 500Vpp and a few milliamps also? Properly driven - that could become complex in comparison to the rest of the converter. At least I do not know an appropriate scheme for this situation, working at 100kHz.

whit3rd schrieb am Dienstag, 25. Mai 2021 um 21:08:34 UTC+2:
> The drive (for a DC low-ripple output) would best be a triangle wave, so
> the rectifiers after the transformer only make a short blip twice per cycle.

The "blip" stimulates trr-ringing, at least in my case.
Does triangle differ from sine significantly in this regard?

I put a short videoclip onto the website, Fameio measures 20pApp (last link):
https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
20pApp rectangle, 0.1Hz, 10 samples moving average.

Thanks!
Cheers, Timo

[Phil Hobbs]

timo.k...@ibtk.de wrote:
> Bill Sloman
>> Coaxial-AC-Bridges-B-Kibble
> Found it in the web, thank you!

Would you post the link?

Thanks

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[Bill Sloman]

On Friday, May 28, 2021 at 12:04:01 AM UTC+10, timo.k...@ibtk.de wrote:
> Bill Sloman
> > Coaxial-AC-Bridges-B-Kibble
> Found it in the web, thank you!
> > Jim Williams - in his Linear Technology application notes N49, AN51, AN55, AN61, and AN65 - was getting around 92% efficiency.
>
> Ahh, I see, it looks good. It seems to be very dependent on the core and it's winding numbers (not only).

You get losses in the core and in the resistance of the windings. The absence of fast edges and the fairly rapid roll-off of the high frequency harmonics helps - ferrites are more lossy at high frequencies.

> Unfortunately I'm restricted concerning the transformer's height to remain below 10mm, so I am fiddling with the small EFD15. Gives up to 80% over all in LTSpice now...

It should be just as good on a small core, unless you manage to saturate the core.
You could e-mail me the L-Spice simulation (to bill.sloman at ieee.org)- or post it here as the text version of the .asc file.

> > The Baxandall Class-D inverter is pretty good. If you want a a better sine wave my variation on it is only about 50% efficient.
>
> Maybe I did not understand what means "Baxandall Class-D inverter". Is it the Baxandall oscillator driven/regulated by a classD- or simply a PWM-switcher?

Back in 1959 Baxandall distinguished his two transistor resonant oscillator from the one-transistor Class-C oscillators by calling it a Class-D oscillator.

Class -D amplifiers came quite a bit later. Somebody like John Woodgate might know the history.

> Tight regulation is not necessary in my case, so the constant input voltage and the relatively constant conversion ratio should be sufficient.
>
> > Synchronous rectifiers, with properly driven MOSFet switches, are much quieter.
>

> Is that true in the case of 500Vpp and a few milliamps also? Properly driven - that could become complex in comparison to the rest of the converter. At least I do not know an appropriate scheme for this situation, working at 100kHz.

Probably. Too many rectifiers act as step recovery diodes when you don't want them to.

> > whit3rd schrieb am Dienstag, 25. Mai 2021 um 21:08:34 UTC+2:
> > The drive (for a DC low-ripple output) would best be a triangle wave, so
> > the rectifiers after the transformer only make a short blip twice per cycle.
> The "blip" stimulates trr-ringing, at least in my case.
> Does triangle differ from sine significantly in this regard?

Probably not.

[timo.k...@ibtk.de]

Hi Phil,

excuse the delay please, I got my second vaccination 2 hours ago.
direct link:
https://de1lib.org/dl/5420567/4762b2
It seems to change the hash daily (the part following last slash).
alternatively:
https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c
Thank you for sharing your valuable experiences!

Cheeers, Timo

[whit3rd]

On Thursday, May 27, 2021 at 8:04:12 AM UTC-7, Bill Sloman wrote:

> > > whit3rd schrieb am Dienstag, 25. Mai 2021 um 21:08:34 UTC+2:
> > > The drive (for a DC low-ripple output) would best be a triangle wave, so
> > > the rectifiers after the transformer only make a short blip twice per cycle.

> > The "blip" stimulates trr-ringing, at least in my case.
> > Does triangle differ from sine significantly in this regard?

> Probably not.

The voltage output of a transformer is proportional to the d/dt of its primary
current. Constant voltage output results from a triangle-wave input current,
except at turnovers.
So, the output-side rectified output only has a blip to cover with
its filter capacitor, rather than the second harmonic of the drive frequency

[timo.k...@ibtk.de]

Bill Sloman
17:04 (vor 3 Stunden)

> It should be just as good on a small core, unless you manage to saturate the core.
> You could e-mail me the L-Spice simulation (to bill.sloman at ieee.org)- or post it here as the text version of the .asc file.

I put the zip onto the little site (last position):
https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
I got the symbol idea for the saturable transformer here:
https://www.mikrocontroller.net/topic/373488#4226728

Thank you!

[Phil Hobbs]

Thanks. I made an OCRed version using https://djvu.org/any2djvu, which
seems to work fine.

(I already have a copy of the paper book, but it ain't searchable.)

Cheers

[Joe Gwinn]

On Thu, 27 May 2021 16:50:51 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>timo.k...@ibtk.de wrote:
>> Hi Phil,
>>
>> excuse the delay please, I got my second vaccination 2 hours ago.
>> direct link:
>> https://de1lib.org/dl/5420567/4762b2
>> It seems to change the hash daily (the part following last slash).
>> alternatively:
>> https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c
>> Thank you for sharing your valuable experiences!
>>
>> Cheeers, Timo
>>
>Thanks. I made an OCRed version using https://djvu.org/any2djvu, which
>seems to work fine.

It wants a password, and my security software was wailing about it.

Joe

[Gerhard Hoffmann]

Am 21.05.21 um 14:08 schrieb timo.k...@ibtk.de:

Hi, Timo!
since you are interested in measuring small currents, you might like
this one:

< https://sci-hub.do/10.1063/1.4997963 >

They even T-compensated the FET bias current.


I'm currently out of sync with the wall clock but happy since I repaired
and calibrated my no longer booting HP 54750A sampling scope mainframe
today. In the end, it was an empty Lithium battery on the CPU board.
It was COMPLETELY empty, not a mV! With the new battery, it complained
about missing cal-factors. I wonder how that thing worked the last years
at all. Wow! 68020 with floating point coprocessor!

Note to selfes: Don't try to remove the box/handles/bottom feet etc.
Impossible or futile. Spot-welded, unlike the usual HP/Agilent boxes.
Just remove the backplate.

Cheers, Gerhard

[Bill Sloman]

> its filter capacitor, rather than the second harmonic of the drive frequency.

Except that the blip is the current moving from one rectifier to another. The two alternative paths both have inductance, and the rectifiers have been known to act as step-recovery diodes, and that can generate some very high rates of change of current, and corresponding large voltage spikes.

--
Bill Sloman, Sydney

[Bill Sloman]

On Friday, May 28, 2021 at 1:42:57 PM UTC+10, Bill Sloman wrote:

> The zip file isn't easy to open as text, and LTSpice 4 threatens to dump most of the content. E-mail of an un-zipped file would be easier. I can read German - if not all that well - but my wife could help with any difficult bits.

LTSpice 17 did better, but the circuit is horribly messed up with resistors not hooked up and in the wrong place. I've made a start at making the schematic look more like something that would work, but it isn't going quickly, and the saturatable transformer model doesn't seem to have made it.

Using the John Chan model for saturation is nice, but does it seem to make the schematic very messy.

Using a bipolar transistor to drive the transformer may not help the efficiency - they do need base drive (though the FTZ694B is a high gain part) and they don't pull the collector as low as a good MOSFET pulls it drain, particularly when you have Schottky diodes in series with the emitters ....

--
Bill Sloman, Sydney

[timo.k...@ibtk.de]

Bill Sloman schrieb am Freitag, 28. Mai 2021 um 07:24:52 UTC+2:

> LTSpice 17 did better, but the circuit is horribly messed up with resistors not hooked up and in the wrong place. I've made a start at making the schematic look more like something that would work, but it isn't going quickly, and the saturatable transformer model doesn't seem to have made it.
> Using the John Chan model for saturation is nice, but does it seem to make the schematic very messy.
> Using a bipolar transistor to drive the transformer may not help the efficiency - they do need base drive (though the FTZ694B is a high gain part) and they don't pull the collector as low as a good MOSFET pulls it drain, particularly when you have Schottky diodes in series with the emitters ....
>

Good morning Bill,

excuse me please, I did not tell about usage.
You should expand the zip with another program than LTSpice and put all files in _one_ (working) directory. You may prefer a new one but not necessarily. LTSpice grabs all needed symbols from there, also the modified res.asy.
This is explained here:
https://www.mikrocontroller.net/topic/373488#4226728

I sent you an email containing the single files.

The chan model or the schematics become much more clear by using the Symbols:
Trafo_1pri_1sek.asy
or
Trafo_3pri_2sek.asy
which has to carry the identical name as ist's nets:
trafo_1pri_1sek.asc
or
Trafo_3pri_2sek.asc

The model description is put into the *.asc files, the upper-/lowercase does not seem to be a problem.

The original resistors use a bad placed origin, it should be in the middle of the symbol. Additionaly I like to know, which is pin 1 in the schematic (e.g. to determine the direction of the current flow).

One may prove the power wasted by e.g. the bipolars using [Alt]+[left mouse button] on it. It is low in comparison to the whole efficiency loss.
If I prefer FETs, I have to watch Vgs or complicate the gate-controls due to the 24V power which translates into (Pi)*24V=75V at the drains.

I am still not sure which version would be the more suitable for that application. At least I saw the bipolar version working. ;)
The Schottkys are a try only together with the BE-diodes. Delete them...

Cheers,
Timo Kirschke

[timo.k...@ibtk.de]

Hi Gerhard,

Gerhard Hoffmann
04:40 (vor 6 Stunden)
> since you are interested in measuring small currents, you might like this one:...

You provide very interesting ideas every time! I remember your amplifier attempts.
Our "customers" like to see 0,5pA as resolution, not accuracy, so I'm in a relaxed situation with the ADA4350-1. Much simpler than the swiss approach. Interesting, that they seem to use ordinary FR4 instead of ceramic based layers.
Congratulations, that you managed the scope fail! In earlier times we left the disco at that time, not the lab...

Thank you very much!
Cheers, Timo

[Bill Sloman]

On Friday, May 28, 2021 at 6:03:40 PM UTC+10, timo.k...@ibtk.de wrote:
> Bill Sloman schrieb am Freitag, 28. Mai 2021 um 07:24:52 UTC+2:
>
> > LTSpice 17 did better, but the circuit is horribly messed up with resistors not hooked up and in the wrong place. I've made a start at making the schematic look more like something that would work, but it isn't going quickly, and the saturatable transformer model doesn't seem to have made it.
> > Using the John Chan model for saturation is nice, but does it seem to make the schematic very messy.
> > Using a bipolar transistor to drive the transformer may not help the efficiency - they do need base drive (though the FTZ694B is a high gain part) and they don't pull the collector as low as a good MOSFET pulls it drain, particularly when you have Schottky diodes in series with the emitters ....
> >
> Good morning Bill,
>
> excuse me please, I did not tell about usage.
> You should expand the zip with another program than LTSpice and put all files in _one_ (working) directory. You may prefer a new one but not necessarily. LTSpice grabs all needed symbols from there, also the modified res.asy.
> This is explained here:
> https://www.mikrocontroller.net/topic/373488#4226728
>
> I sent you an email containing the single files.
>
> The chan model or the schematics become much more clear by using the Symbols:
> Trafo_1pri_1sek.asy
> or
> Trafo_3pri_2sek.asy
> which has to carry the identical name as ist's nets:
> trafo_1pri_1sek.asc
> or
> Trafo_3pri_2sek.asc

Thanks. I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list - and add a Spice model for the FTZ694B - but after that the circuit did simulate and produced sensible waveforms. I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.

> The model description is put into the *.asc files, the upper-/lowercase does not seem to be a problem.
>
> The original resistors use a bad placed origin, it should be in the middle of the symbol. Additionaly I like to know, which is pin 1 in the schematic (e.g. to determine the direction of the current flow).
>
> One may prove the power wasted by e.g. the bipolars using [Alt]+[left mouse button] on it. It is low in comparison to the whole efficiency loss.
> If I prefer FETs, I have to watch Vgs or complicate the gate-controls due to the 24V power which translates into (Pi)*24V=75V at the drains.

I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room.

75V isn't a problem. The Rohm RSQ030N08HZG - at 3A peak current - is a bit bigger than you'd need, but element-14 have 102 in stock for about a dollar each.

http://www.farnell.com/datasheets/2918432.pdf

> I am still not sure which version would be the more suitable for that application. At least I saw the bipolar version working. ;)

Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture.

--
Bill Sloman, Sydney

[Phil Hobbs]

No password required when I use it.

[Joe Gwinn]

On Fri, 28 May 2021 10:32:27 -0400, Phil Hobbs

<pcdhSpamM...@electrooptical.net> wrote:

>Joe Gwinn wrote:
>> On Thu, 27 May 2021 16:50:51 -0400, Phil Hobbs
>> <pcdhSpamM...@electrooptical.net> wrote:
>>
>>> timo.k...@ibtk.de wrote:
>>>> Hi Phil,
>>>>
>>>> excuse the delay please, I got my second vaccination 2 hours ago.
>>>> direct link:
>>>> https://de1lib.org/dl/5420567/4762b2
>>>> It seems to change the hash daily (the part following last slash).
>>>> alternatively:
>>>> https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c
>>>> Thank you for sharing your valuable experiences!
>>>>
>>>> Cheeers, Timo
>>>>
>>> Thanks. I made an OCRed version using https://djvu.org/any2djvu, which
>>> seems to work fine.
>>
>> It wants a password, and my security software was wailing about it.
>>
>> Joe
>>
>
>No password required when I use it.

I just checked again, got the djvu password request.

You may have your credentials cached, so it doesn't keep asking you.

If you come in using a private browser window, what happens?

Joe Gwinn

[Bill Sloman]

On Friday, May 28, 2021 at 11:26:41 PM UTC+10, Bill Sloman wrote:
> On Friday, May 28, 2021 at 6:03:40 PM UTC+10, timo.k...@ibtk.de wrote:
> > Bill Sloman schrieb am Freitag, 28. Mai 2021 um 07:24:52 UTC+2:

<snip>

> Thanks. I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list - and add a Spice model for the FTZ694B - but after that the circuit did simulate and produced sensible waveforms. I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.

<snip>

> Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture.

In fact, that seems to have been what was gong on from 2.0 msec to about 2.7msec.

The current through L7 started going negative - to about -5mA, and there were a negative current spikes through Q1 and Q2.

The problem is that this goes away in Spice simulations, but have been known to persist in real life. In real life you'd probably reduce the inductance of L7 until it went away.

--
Bill Sloman, Sydney

[Phil Hobbs]

Weird. If I just type djvu.org into the address bar, it comes up in
http:// and works normally. The https:// thing works as you say.

Use the http:// one. ;0

[Joe Gwinn]

On Sat, 29 May 2021 16:29:27 -0400, Phil Hobbs

Using plain http did get rid of the password dialog, and did get me to
the any2djvu page, which is not an OCRed copy of anything.

Joe Gwinn

[Phil Hobbs]

Try it out on an actual PDF. There are several options for getting
embedded text, two of which involve OCR. I've done hundreds of
documents that way, from one-pagers up to full-length books. It's Good
Medicine.

[Joe Gwinn]

On Sat, 29 May 2021 18:24:16 -0400, Phil Hobbs

Ahh. I thought that an already OCRed pdf was there. I don't have the
original pdf yet. Where do I find that?

Thanks,

Joe Gwinn

[Phil Hobbs]

Timo's link above.

[Joe Gwinn]

On Sun, 30 May 2021 13:16:15 -0400, Phil Hobbs

Got it. Thanks.

I have already read a library copy, but wanted a copy for reference.

The key idea that is useful outside of metrology is using toroid cores
around the coaxial cables to force center and shield currents to be
exactly equal but opposite, like a transmission-line balun.

Joe Gwinn

[Bill Sloman]

Here's a more conventional LT Spice model of a MOSFet driven inverter.

Version 4
SHEET 1 1668 1056
WIRE -1088 -688 -1312 -688
WIRE -944 -688 -1088 -688
WIRE -304 -688 -944 -688
WIRE -32 -688 -304 -688
WIRE 160 -688 -32 -688
WIRE 1488 -688 160 -688
WIRE -304 -624 -304 -688
WIRE -32 -592 -32 -688
WIRE 160 -576 160 -688
WIRE -32 -464 -32 -512
WIRE 160 -464 160 -512
WIRE 160 -464 -32 -464
WIRE -304 -432 -304 -544
WIRE 112 -432 -304 -432
WIRE -304 -352 -304 -432
WIRE 112 -352 112 -432
WIRE -944 -320 -944 -688
WIRE -176 -304 -240 -304
WIRE -32 -304 -32 -464
WIRE -32 -304 -96 -304
WIRE 0 -304 -32 -304
WIRE 48 -304 0 -304
WIRE -944 -176 -944 -240
WIRE -1312 -112 -1312 -688
WIRE -640 -112 -704 -112
WIRE -448 -112 -640 -112
WIRE -128 -112 -384 -112
WIRE 320 -112 -128 -112
WIRE -944 -16 -944 -112
WIRE -544 -16 -944 -16
WIRE -384 -16 -544 -16
WIRE -704 48 -704 -112
WIRE -672 48 -704 48
WIRE -384 48 -384 -16
WIRE -384 48 -592 48
WIRE -240 48 -384 48
WIRE 320 48 320 -112
WIRE 320 48 -160 48
WIRE -1088 144 -1088 -688
WIRE -528 208 -624 208
WIRE 608 208 -448 208
WIRE 720 208 608 208
WIRE 848 208 784 208
WIRE 896 208 848 208
WIRE 1040 208 960 208
WIRE 1232 208 1120 208
WIRE 1440 208 1232 208
WIRE -624 288 -624 208
WIRE -400 288 -624 288
WIRE -208 288 -400 288
WIRE 560 288 -128 288
WIRE 720 288 560 288
WIRE 848 288 848 208
WIRE 848 288 784 288
WIRE -704 352 -704 48
WIRE 320 368 320 48
WIRE 1440 384 1440 208
WIRE -592 432 -656 432
WIRE -304 432 -304 -256
WIRE -304 432 -512 432
WIRE 0 448 0 -304
WIRE 112 448 112 -256
WIRE 160 448 112 448
WIRE 272 448 240 448
WIRE 1232 480 1232 208
WIRE -304 560 -304 432
WIRE 112 576 112 448
WIRE -1312 736 -1312 -32
WIRE -1088 736 -1088 208
WIRE -1088 736 -1312 736
WIRE -704 736 -704 448
WIRE -704 736 -1088 736
WIRE -400 736 -400 288
WIRE -400 736 -704 736
WIRE -304 736 -304 640
WIRE -304 736 -400 736
WIRE 0 736 0 528
WIRE 0 736 -304 736
WIRE 112 736 112 656
WIRE 112 736 0 736
WIRE 320 736 320 464
WIRE 320 736 112 736
WIRE 1232 736 1232 544
WIRE 1232 736 320 736
WIRE 1312 736 1232 736
WIRE 1440 736 1440 464
WIRE 1440 736 1312 736
WIRE 1472 736 1440 736
WIRE 1552 736 1472 736
WIRE -1312 768 -1312 736
WIRE 1312 784 1312 736
WIRE 1472 832 1472 736
WIRE 608 864 608 208
WIRE 752 864 608 864
WIRE 944 864 816 864
WIRE 560 992 560 288
WIRE 752 992 560 992
WIRE 944 992 944 864
WIRE 944 992 816 992
WIRE 992 992 944 992
WIRE 1088 992 1056 992
WIRE 1312 992 1312 848
WIRE 1312 992 1168 992
WIRE 1472 992 1472 912
WIRE 1472 992 1312 992
FLAG -1312 768 0
FLAG -544 -16 Vct
FLAG -640 -112 tank-
FLAG -128 -112 tank+
DATAFLAG 1328 208 ""
SYMBOL ind2 -688 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.088 Cpar=10p
SYMBOL ind2 -256 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.022
SYMBOL cap -384 -128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 46 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2n
SYMBOL voltage -1312 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL ind2 -192 -320 M90
WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L5
SYMATTR Value 780n
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.004 Cpar=1pF
SYMBOL res -304 -592 R0
SYMATTR InstName R14
SYMATTR Value 2k2
SYMBOL res 192 448 M90
WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2
SYMATTR InstName R1
SYMATTR Value 22
SYMBOL nmos 272 368 R0
SYMATTR InstName M1
SYMATTR Value Si3440DV
SYMBOL nmos -656 352 M0
SYMATTR InstName M2
SYMATTR Value Si3440DV
SYMBOL res -560 432 M90
WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2
SYMATTR InstName R2
SYMATTR Value 22
SYMBOL ind2 -960 -336 R0
SYMATTR InstName L6
SYMATTR Value 2.2m
SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p
SYMBOL diode 720 224 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RFU02VS8S
SYMBOL diode 720 304 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RFU02VS8S
SYMBOL diode 816 848 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D3
SYMATTR Value RFU02VS8S
SYMBOL diode 816 976 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D4
SYMATTR Value RFU02VS8S
SYMBOL cap 1216 480 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 1296 784 R0
WINDOW 3 17 75 Left 2
SYMATTR Value 10n
SYMATTR InstName C3
SYMBOL FerriteBead 928 208 R90
WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L7
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p
SYMBOL FerriteBead 1024 992 R90
WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L8
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p mfg="Würth Elektronik" pn="7427501 WE-UKW 40060"
SYMBOL res 1440 416 R0
SYMATTR InstName R4
SYMATTR Value 820k
SYMBOL res 1472 864 R0
SYMATTR InstName R5
SYMATTR Value 820k
SYMBOL res 1136 992 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 1088 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL cap -1104 144 R0
SYMATTR InstName C4
SYMATTR Value 100nF
SYMBOL pnp -240 -256 R180
SYMATTR InstName Q1
SYMBOL pnp 48 -256 M180
SYMATTR InstName Q2
SYMBOL res -304 592 R0
SYMATTR InstName R3
SYMATTR Value 1k5
SYMBOL res 112 608 R0
WINDOW 3 13 26 Left 2
SYMATTR Value 1k5
SYMATTR InstName R9
SYMBOL res -32 -560 R0
SYMATTR InstName R10
SYMATTR Value 11k
SYMBOL res 0 480 R0
SYMATTR InstName R11
SYMATTR Value 13k
SYMBOL cap 144 -576 R0
SYMATTR InstName C5
SYMATTR Value 10n
SYMBOL FerriteBead -944 -144 R180
SYMATTR InstName L3
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p
SYMBOL ind2 -544 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 5m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL ind2 -224 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -2 57 VBottom 2
SYMATTR InstName L9
SYMATTR Value 5m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n
TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99

Seems to work. Startup is messy. The MOSFet was picked from what LT Spice offered - it isn't all that cheap. The transformer is what Timo seems to have used, but I haven't worked out wire sizes and layering. The single turn winding - L5 - would presumably be at the bottom pf the stack, tucked in a corner under the centre-tapped primary, which I'd probably wind as as 15 turns of twisted pair. The secondaries are 80 turns each, which might be one layer each of 0.1mm wire - maybe 0.6mm with there layers of 0.06mm tape - but you still have 1.6 mm of height for the primaries, which should be plenty. Two layer secondaries might work too.

--
Bill Sloman, Sydney

[timo.k...@ibtk.de]

Bill Sloman
28.05.2021, 15:26:41 (vor 4 Tagen)

Hi Bill,

Excuse for the delay, please!

> I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list...

The simulation run always better without ferrites at the end, the inductance produced ringing.

> I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.

Yes, it should! Because the load changes at this time.

> I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room.

I fiddled around with some vriations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits.
The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.

> but element-14 have 102 in stock for about a dollar each.

Wer are "lucky" to have the "time" problem only. I am the only one working on the analog part of this (and a few other) projects. Mostly we have to deliver only a few modules/systems to our scientific customers. So the part costs are not the main issue in most cases.

> Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture.

> In fact, that seems to have been what was gong on from 2.0 msec to about 2.7msec.
> The current through L7 started going negative - to about -5mA, and there were a negative current spikes through Q1 and Q2.
> The problem is that this goes away in Spice simulations, but have been known to persist in real life. In real life you'd probably reduce the inductance of L7 until it went away.

Hmm, for sure? I don't know exactly.
See https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S40.pdf

Abb. 7.25: The oscillator was not optimised for no-load conditions, see Ic(Q1/2) spikes and it’s negative part. Raising the value of R11 compensates it.
Even the choke current goes partly negative. Raising the choke’s value lowers amplitude of the current and prevents it from going negative.
Abb. 7.26: Effects of raising the values of R11 and the choke.

In my opinion the BJT based variant seems to be more robust, more simple and has a smoother startup.
The latest simulations showed >80% overall efficiency at 250kHz except core losses, which haven't been simulated. The no load power consumption is safely below 500mW (partly below 250mW).
After all I trust the simulation in principle (because the circuit behaved very similar on the bench) and will build up (wind the transformer) the latest version for tests.

Your last circuit runs the simulation promptly but does not start nor oscillate normally. One cycle in 2ms. At least on my PC (LTSpice17). Maybe, the LTSpice versions behave different?

Thank you!
Cheers, Timo

[Bill Sloman]

On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote:
> Bill Sloman
> 28.05.2021, 15:26:41 (vor 4 Tagen)
>
> Hi Bill,
>
> Excuse for the delay, please!
>
> > I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list...
>
> The simulation run always better without ferrites at the end, the inductance produced ringing.

Real circuits use ferrite beads to contain ringing.

> > I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.
>
> Yes, it should! Because the load changes at this time.

That doesn't tie up with what was going on.

> > I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room.
>

> I fiddled around with some variations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits.

> The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.

If you use a large inductor (as you did) start up does involve the centre-tap voltage going well above what you see when the circuit has settled down, and the inductor pulling the centre-tap below ground during start-up. With bipolar transistors this gets you into squegging, which persists. If you put a high voltage zener between the centre-tap and ground - something like 40V - it will cap the centre tap-voltage, when it goes over 38V, and divert the negative current to ground, and the start-up would be briefer and cleaner.

The messy start-up isn't a consequence of the FET drive.

> > but element-14 have 102 in stock for about a dollar each.
>

> We are "lucky" to have the "time" problem only. I am the only one working on the analog part of this (and a few other) projects. Mostly we have to deliver only a few modules/systems to our scientific customers. So the part costs are not the main issue in most cases.

>
> > Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture.
> > In fact, that seems to have been what was gong on from 2.0 msec to about 2.7msec.
> > The current through L7 started going negative - to about -5mA, and there were a negative current spikes through Q1 and Q2.
> > The problem is that this goes away in Spice simulations, but have been known to persist in real life. In real life you'd probably reduce the inductance of L7 until it went away.
>
> Hmm, for sure? I don't know exactly.
> See https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
> 20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S40.pdf

Simulations aren't real life.

> Abb. 7.25: The oscillator was not optimised for no-load conditions, see Ic(Q1/2) spikes and it’s negative part. Raising the value of R11 compensates it.
> Even the choke current goes partly negative. Raising the choke’s value lowers amplitude of the current and prevents it from going negative.
> Abb. 7.26: Effects of raising the values of R11 and the choke.
>
> In my opinion the BJT based variant seems to be more robust, more simple and has a smoother startup.

You may need to revise that opinion. The start-up isn't a problem with actual circuits I've worked with, unless it persists - when it is called squegging.

Baxandall's paper only refers to it in a footnote on page 752. I've run into it in real life, and the late Tony Williams had seen more of it than he liked. It's not problem that persists with MOSFet drive.

> The latest simulations showed >80% overall efficiency at 250kHz except core losses, which haven't been simulated. The no load power consumption is safely below 500mW (partly below 250mW).
> After all I trust the simulation in principle (because the circuit behaved very similar on the bench) and will build up (wind the transformer) the latest version for tests.
>
> Your last circuit runs the simulation promptly but does not start nor oscillate normally. One cycle in 2ms. At least on my PC (LTSpice17). Maybe, the LTSpice versions behave different?

Starting oscillators in LTSpice is pest. Real circuits have enough asymmetry so they start up fast. Simulated circuits are much more symmetrical.

My circuit did take a few msec start, which is why I let the simulation run for 10msec to let it settle down. You can fiddle the initial conditions to get them to start faster, but that takes work and it's rarely worth the effort.

--
Bill Sloman, Sydney

[Bill Sloman]

On Wednesday, June 2, 2021 at 12:27:56 AM UTC+10, Bill Sloman wrote:
> On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote:
> > Bill Sloman
> > 28.05.2021, 15:26:41 (vor 4 Tagen)
> >
> > Hi Bill,
> >
> > Excuse for the delay, please!
> >
> > > I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list...
> >
> > The simulation run always better without ferrites at the end, the inductance produced ringing.
>
> Real circuits use ferrite beads to contain ringing.
>
> > > I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.
> >
> > Yes, it should! Because the load changes at this time.
>
> That doesn't tie up with what was going on.
>
> > > I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room.
> >
> > I fiddled around with some variations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits.
> > The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.
>
> If you use a large inductor (as you did) start up does involve the centre-tap voltage going well above what you see when the circuit has settled down, and the inductor pulling the centre-tap below ground during start-up. With bipolar transistors this gets you into squegging, which persists. If you put a high voltage zener between the centre-tap and ground - something like 40V - it will cap the centre tap-voltage, when it goes over 38V, and divert the negative current to ground, and the start-up would be briefer and cleaner.
>
> The messy start-up isn't a consequence of the FET drive.

In fact what was going on was that the current though feed inductor L6 - went up to 12.6A before the oscillator started oscillating at all, and it started off at 7kHz, moving up to 100kHz with about a millisecond.

You power supply isn't going to deliver 12A and real components are different enough that the oscillation would have got going earlier.

--
Bill Sloman, Sydney

[Dmitriy Pshonkin]

You can eliminate interference in active ways:
https://arxiv.org/pdf/1609.03607.pdf

[JM]

On 27/05/2021 18:52, timo.k...@ibtk.de wrote:
> Hi Phil,
>
> excuse the delay please, I got my second vaccination 2 hours ago.
> direct link:
> https://de1lib.org/dl/5420567/4762b2
> It seems to change the hash daily (the part following last slash).
> alternatively:
> https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c
> Thank you for sharing your valuable experiences!
>
> Cheeers, Timo
>

Note that the IET published a book co-authored by Kibble called "Coaxial
Electrical Circuits for Interference-free Measurements" which is still
in print. It covers the information in Kibble's earlier book.

[Bill Sloman]

On Wednesday, June 2, 2021 at 1:10:25 PM UTC+10, Bill Sloman wrote:
> On Wednesday, June 2, 2021 at 12:27:56 AM UTC+10, Bill Sloman wrote:
> > On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote:
> > > Bill Sloman
> > > 28.05.2021, 15:26:41 (vor 4 Tagen)

<snip>

> In fact what was going on was that the current though feed inductor L6 - went up to 12.6A before the oscillator started oscillating at all, and it started off at 7kHz, moving up to 100kHz with about a millisecond.
>
> You power supply isn't going to deliver 12A and real components are different enough that the oscillation would have got going earlier.

I've tweaked my simulation by adding 22R to the 24V source, which pulls the initial peak current through L6 down to less than an amp. I threw in a zener to limit the peak centre tap voltage, but added a ferrite bead to kill some very high frequency ringing which showed up on the capacitative current through the zener in regular operatoin.

Version 4
SHEET 1 1668 1056

WIRE -1232 -688 -1312 -688
WIRE -1088 -688 -1152 -688

WIRE -944 384 -944 -16

WIRE 1440 384 1440 208
WIRE -592 432 -656 432
WIRE -304 432 -304 -256
WIRE -304 432 -512 432
WIRE 0 448 0 -304
WIRE 112 448 112 -256
WIRE 160 448 112 448
WIRE 272 448 240 448
WIRE 1232 480 1232 208

WIRE -944 512 -944 448

WIRE -304 560 -304 432
WIRE 112 576 112 448
WIRE -1312 736 -1312 -32
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WIRE -1088 736 -1312 736

WIRE -944 736 -944 576
WIRE -944 736 -1088 736

WIRE -704 736 -704 448

WIRE -704 736 -944 736

SYMBOL zener -928 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMATTR Value 1N5371B
SYMBOL FerriteBead -944 544 R180
SYMATTR InstName L10

SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL res -1136 -704 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName R8
SYMATTR Value 22

TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n
TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99

--
Bill Sloman, Sydney

[Dmitriy Pshonkin]

A Resonant DC-DC transformer with Zero Current Ripple
https://www.semanticscholar.org/paper/A-Resonant-DC-DC-transformer-with-Zero-Current-Abramovitz-Smedley/25b64c261fbe69200035b905ad8010814d8a0535

[Bill Sloman]

On Saturday, June 12, 2021 at 7:19:41 PM UTC+10, Dmitriy Pshonkin wrote:
> A Resonant DC-DC transformer with Zero Current Ripple
> https://www.semanticscholar.org/paper/A-Resonant-DC-DC-transformer-with-Zero-Current-Abramovitz-Smedley/25b64c261fbe69200035b905ad8010814d8a0535

It costs money to see it. The Cuk converter from 1983

https://ieeexplore.ieee.org/document/1062238

offered ripple-free output (if I remember rightly - and I had to dig a bit to come up with the name). I looked at it at the time, and it looked a bit expensive for what it offered.

--
Bill Sloman, Sydney

[Gerhard Hoffmann]

Am 12.06.21 um 11:19 schrieb Dmitriy Pshonkin:

> A Resonant DC-DC transformer with Zero Current Ripple
> https://www.semanticscholar.org/paper/A-Resonant-DC-DC-transformer-with-Zero-Current-Abramovitz-Smedley/25b64c261fbe69200035b905ad8010814d8a0535
>

< https://sci-hub.do/10.1109/tpel.2007.909192 >

[Bill Sloman]

It looks cute. I particularly like the idea of winding the input inductor and the output filter inductance on the same core - they are coping with the same series of half-sine wave voltages, after all. To paraphrase Thomas Huxley on Darwin's Theory of evolution, I do feel a bit stupid for not thinking of it for myself.

Here's a version of Timo's +/-200V inverter that incorporates the idea. It's not in the least ripple free - there's about 80mA of ripple on the roughly 12mA DC current through the inductor L6, but there's very little voltage ripple on the 200V output - some 200mV. The turns ratio had to be pushed up appreciably to get 200V DC out - the circuit isn't peak-clipping any more.

There is a significant 1.8MHz component in the ripple current - it should be possible to work out where this coming from and damp it down, but it's not worth the trouble on a Spice simulation, though it would be worth doing if it showed up on a real circuit.

Version 4
SHEET 1 1668 1056

WIRE -1216 -688 -1312 -688
WIRE -1088 -688 -1136 -688

WIRE 1072 208 976 208
WIRE 1232 208 1136 208

WIRE 976 992 944 992
WIRE 1152 992 1056 992

WIRE 1312 992 1312 848

WIRE 1312 992 1216 992

WIRE 1472 992 1472 912
WIRE 1472 992 1312 992
FLAG -1312 768 0
FLAG -544 -16 Vct
FLAG -640 -112 tank-
FLAG -128 -112 tank+

SYMBOL ind2 -688 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.088 Cpar=10p
SYMBOL ind2 -256 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.022
SYMBOL cap -384 -128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 46 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2n

SYMBOL ind2 -192 -320 M90
WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L5
SYMATTR Value 780n
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.004 Cpar=1pF
SYMBOL res -304 -592 R0
SYMATTR InstName R14
SYMATTR Value 2k2
SYMBOL res 192 448 M90
WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2
SYMATTR InstName R1
SYMATTR Value 22
SYMBOL nmos 272 368 R0
SYMATTR InstName M1
SYMATTR Value Si3440DV
SYMBOL nmos -656 352 M0
SYMATTR InstName M2

SYMATTR Value Si3440DV1

SYMBOL res 1440 416 R0
SYMATTR InstName R4
SYMATTR Value 820k
SYMBOL res 1472 864 R0
SYMATTR InstName R5
SYMATTR Value 820k

SYMBOL cap -1104 144 R0
SYMATTR InstName C4

SYMATTR Value 1µF

SYMATTR Value 5.5m

SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL ind2 -224 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -2 57 VBottom 2
SYMATTR InstName L9

SYMATTR Value 5.5m

SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL zener -928 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMATTR Value 1N5371B
SYMBOL FerriteBead -944 544 R180
SYMATTR InstName L10
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL res -1168 -688 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 22

SYMBOL ind2 992 192 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName L7
SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=1p

SYMBOL voltage -1312 -128 R0
WINDOW 123 0 0 Left 0

WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1

SYMATTR InstName V1
SYMATTR Value 24

SYMBOL ind2 1072 976 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName L8
SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=1p
SYMBOL FerriteBead 1104 208 R90

WINDOW 0 -16 0 VBottom 2

SYMATTR InstName L11
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"
SYMBOL FerriteBead 1184 992 R90

WINDOW 0 -16 0 VBottom 2

SYMATTR InstName L12
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"

TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n
TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99

TEXT -1312 -752 Left 2 !.model Si3440DV1 VDMOS(Rg=3 Vto=3.6 Rd=150m Rs=112.5m Rb=188m Kp=50 Cgdmax=.2n Cgdmin=.02n Cgs=.2n Cjo=.05n Is=11p ksubthres=.1 mfg=Siliconix Vds=150 Ron=375m Qg=5.4n)
TEXT -856 792 Left 2 !.ic I(l6=15m I(L1=15m))
TEXT -848 856 Left 2 !K2 L6 L7 L8 0.99

--
Bill Sloman, Sydney

[Dmitriy Pshonkin]

Good job.
High voltage linear regulated source.
https://agenda.infn.it/event/14074/contributions/22751/attachments/16171/18319/FEE-summary.pdf
https://webthesis.biblio.polito.it/15762/1/tesi.pdf
page 104

[tiki]

Thank you guys, fro all your valaubel hints!
I do not have enough time to answer something useful in the moment.
Nevertheless I try to understand and "replay" all the ideas, especially the coupled inductors one, which looks very interesting.
Unfortunately I am very bad in math, so I have to "guess" the right Lin/Lf values out of the paper.
My version of the HV linear regulator for Bias seems to be okay, an AC simulation shows up to 100dB ripple rejection, I didn't measure it on the bench until now. It does not need to have high upper frequency corner. The amplitude response of 1Hz max. is enough for this application.
See 20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S44.pdf in the actualised link https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html
Bill, your last *.asc does not oscillate in my environment, maybe, I did something wrong.
Thanks!
Cheers, Timo

[Bill Sloman]

Works fine for me. I updated LT Spice 17 a couple weeks ago. If you've done it more recently it may not be quite the same environment.

My start-up is still pretty horrible - Vtank peaks at 128V at about 12 usec, and I(6) at 1.34A at about 7.5usec. Regular oscillation sets in at about 56usec and it has more or less settled down by 500usec.

--
Bill Sloman, Sydney

[Bill Sloman]

On Sunday, June 13, 2021 at 3:27:59 PM UTC+10, Dmitriy Pshonkin wrote:
> Good job.

Oops. Not such a good job after all. I should have flipped L8 though 180 degrees when I originally cut and pasted it from L7.

Woke up in the middle of the night wondering whether I'd bother to do it. and when I checked. I hadn't.

I've done it here. Doesn't seem to have made much difference to the waveforms that I'd bothered to look at, which doesn't say anything good about my attention to detail

WIRE 1008 992 944 992
WIRE 1152 992 1088 992

SYMBOL ind2 992 1008 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2

[Bill Sloman]

On Monday, June 14, 2021 at 12:34:08 PM UTC+10, Bill Sloman wrote:
> On Sunday, June 13, 2021 at 3:27:59 PM UTC+10, Dmitriy Pshonkin wrote:
> > Good job.
>
> Oops. Not such a good job after all. I should have flipped L8 though 180 degrees when I originally cut and pasted it from L7.
>
> Woke up in the middle of the night wondering whether I'd bother to do it. and when I checked. I hadn't.
>

> I've done it here. Doesn't seem to have made much difference to the waveforms that I'd bothered to look at, which doesn't say anything good about my attention to detail.

Even more oops. The extra windings were in the wrong place, and when I put them where I think they ought to go the circuit behaves in a way that it shouldn't.

I found a couple more bugs when I started looking harder, and I don't think I've got rid of all of them yet. Depressing, but design is like that, until you get it right, if you can.

--
Bill Sloman, Sydney
--
> Bill Sloman, Sydney

[tiki]

Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:
> Even more oops...

Hello,

same to me. Didn't get it working in a meaninful manner. ;)
Neither did my attempt work as shown in the paper. So I strip it down to the bones now, but still...

On the other hand does the heavily loaded BJT based version for all the lower voltages (without the second L in the output) produce somewhat irregular waveforms, getting closer to rectangle shape but still much less harmonics than a hard switching version.
It seems to be clear due to the energy, which the load draws out of the output, so the rectifiers must cut the tops of sine. Something like an in-between of Baxandall and hard-switched Push pull, but still resonating.
And load helps to prevent "squegging" - safely in my tries.
Thank you for your effort! It's still very interesting! :)

Cheers, Timo

[Bill Sloman]

The oops wasn't as bad as I first thought. This is the current version, which isn't all that different from the last one. It seems to work for me, despite a slightly more realistic
value (10pF rather than 1pF) for the parallel capacitances of the overwindings (l7 and L8) on the feed-inductor - L6. The overwindings just cancel out the half-sine component of the voltages applied to L11 and L12 leaving something closer to a constant voltage. It still strikes me as a neat idea.

Version 4
SHEET 1 1668 1056
WIRE -1216 -688 -1312 -688
WIRE -1088 -688 -1136 -688
WIRE -944 -688 -1088 -688
WIRE -304 -688 -944 -688
WIRE -32 -688 -304 -688
WIRE 160 -688 -32 -688
WIRE 1488 -688 160 -688
WIRE -304 -624 -304 -688
WIRE -32 -592 -32 -688
WIRE 160 -576 160 -688
WIRE -32 -464 -32 -512
WIRE 160 -464 160 -512
WIRE 160 -464 -32 -464

WIRE -304 -416 -304 -544
WIRE 112 -416 -304 -416
WIRE -304 -352 -304 -416
WIRE 112 -352 112 -416

WIRE -944 -320 -944 -688
WIRE -176 -304 -240 -304
WIRE -32 -304 -32 -464
WIRE -32 -304 -96 -304
WIRE 0 -304 -32 -304
WIRE 48 -304 0 -304

WIRE -944 -208 -944 -240

WIRE -1312 -112 -1312 -688
WIRE -640 -112 -704 -112
WIRE -448 -112 -640 -112
WIRE -128 -112 -384 -112
WIRE 320 -112 -128 -112

WIRE -944 -16 -944 -144

WIRE -544 -16 -944 -16
WIRE -384 -16 -544 -16
WIRE -704 48 -704 -112
WIRE -672 48 -704 48
WIRE -384 48 -384 -16
WIRE -384 48 -592 48
WIRE -240 48 -384 48
WIRE 320 48 320 -112
WIRE 320 48 -160 48
WIRE -1088 144 -1088 -688
WIRE -528 208 -624 208
WIRE 608 208 -448 208
WIRE 720 208 608 208
WIRE 848 208 784 208

WIRE 928 208 848 208
WIRE 1072 208 1008 208

WIRE 1232 208 1136 208
WIRE 1440 208 1232 208
WIRE -624 288 -624 208
WIRE -400 288 -624 288

WIRE -224 288 -400 288
WIRE 560 288 -144 288

WIRE 1024 992 944 992
WIRE 1152 992 1104 992

SYMATTR Value 3k3

SYMBOL res 192 448 M90
WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2
SYMATTR InstName R1

SYMATTR Value 2.2

SYMBOL nmos 272 368 R0
SYMATTR InstName M1
SYMATTR Value Si3440DV
SYMBOL nmos -656 352 M0
SYMATTR InstName M2
SYMATTR Value Si3440DV

SYMBOL res -560 432 M90
WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2
SYMATTR InstName R2

SYMATTR Value 2.2

SYMBOL ind2 -544 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4

SYMATTR Value 12.2m

SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p

SYMBOL ind2 -128 272 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName L3
SYMATTR Value 12.2m

SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL zener -928 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMATTR Value 1N5371B
SYMBOL FerriteBead -944 544 R180
SYMATTR InstName L10
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p
SYMBOL res -1168 -688 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 22

SYMBOL ind2 1008 1008 R270

WINDOW 0 32 56 VTop 2

WINDOW 3 -6 69 VBottom 2

SYMATTR InstName L7
SYMATTR Value 153m

SYMATTR SpiceLine Rser=1 Cpar=10p

SYMBOL voltage -1312 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value 24

SYMBOL ind2 1024 192 R90

WINDOW 0 4 56 VBottom 2

WINDOW 3 48 56 VTop 2

SYMATTR InstName L8
SYMATTR Value 153m

SYMATTR SpiceLine Rser=1 Cpar=10p

SYMBOL FerriteBead 1104 208 R90
WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L11
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"
SYMBOL FerriteBead 1184 992 R90
WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L12
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"

SYMBOL FerriteBead -944 -176 R180
SYMATTR InstName L9

SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n
TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99

[Bill Sloman]

On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote:
> On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote:
> > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:

<snip>

> > Thank you for your effort! It's still very interesting! :)

I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them.

This is about as simple as the circuit can get. The MOSFets are driven by a centre-tapped 6-turn winding (L5 and L6) and the EFD55-8 former has only got eight pins, which means that on a real circuit you'd have to improvise a bit.

For the circuit to start the bias voltage on the centre tap has to be just high enough for both MOSFets to be turned on, which is a bit too high to let the circuit work properly once it running as intended. The network around D6, D7 and D8 lets bias voltage get pulled down to the point where the circuit will work correctly, once it is operating as intended.

With values chosen, each of D7 and D8 is pulling current out of the bias node for about a quartrer the time, and I imagine that that will probably work over the tolerance range for the MOSFets M1 and M2 - Siliconix Si3.440DV parts which happened to be in the LT Spice component range.

R8 damps the 2.5MHz parastic oscillation driven by the switching transients. A more complex design could have smaller switching transients, but it wouldn't be worth posting here.

L14 is a totally dummy part - it exists to create the waveform V(cancelingV) which is there to make it easier to explain what L8 an L9 were put in to do. If you plot V(n009) + V(cancellingv) or V(n018) - V(cancellingv) you get pretty close to flat +200V and -200V traces, which are a lot easier to filter than the voltage coming out of the rectifiers.

The circuit seems to deliver 4mA at +200V and -200V - 1.6 Watt - and draw 81mA at 24V - 1.95 Watt, which 82% efficiency. Two mA of the current drawn is setting up bias voltages. The inductor resistances aren't properly worked out, so this isn't all that reliable.

I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across.

Version 4
SHEET 1 1944 1284
WIRE -1200 -848 -1312 -848
WIRE -1088 -848 -1136 -848
WIRE -944 -848 -1088 -848
WIRE 0 -848 -944 -848
WIRE 832 -848 0 -848
WIRE 1712 -848 832 -848
WIRE -944 -784 -944 -848
WIRE 0 -704 0 -848
WIRE -944 -672 -944 -704
WIRE 832 -624 832 -848
WIRE -656 -464 -704 -464
WIRE -272 -464 -656 -464
WIRE 96 -464 -208 -464
WIRE 464 -464 176 -464
WIRE 624 -464 464 -464
WIRE -944 -368 -944 -608
WIRE -544 -368 -944 -368
WIRE -384 -368 -544 -368
WIRE -704 -304 -704 -464
WIRE -672 -304 -704 -304
WIRE -384 -304 -384 -368
WIRE -384 -304 -592 -304
WIRE -240 -304 -384 -304
WIRE 624 -304 624 -464
WIRE 624 -304 -160 -304
WIRE 832 -288 832 -544
WIRE 1872 -288 832 -288
WIRE 1872 -224 1872 -288
WIRE 352 -160 -496 -160
WIRE 464 -160 352 -160
WIRE 704 -160 544 -160
WIRE 832 -160 832 -288
WIRE 832 -160 768 -160
WIRE -1312 -112 -1312 -848
WIRE 832 -80 832 -160
WIRE -496 -64 -496 -160
WIRE 352 -64 352 -160
WIRE -1088 144 -1088 -848
WIRE -400 176 -624 176
WIRE 960 176 -320 176
WIRE 1072 176 960 176
WIRE 1200 176 1136 176
WIRE 1280 176 1200 176
WIRE 1424 176 1360 176
WIRE 1584 176 1488 176
WIRE 1792 176 1584 176
WIRE -624 288 -624 176

WIRE -400 288 -624 288

WIRE -288 288 -400 288
WIRE 912 288 -208 288
WIRE 1072 288 912 288
WIRE 1200 288 1200 176
WIRE 1200 288 1136 288
WIRE -944 384 -944 -368
WIRE 1792 384 1792 176
WIRE 624 400 624 -304
WIRE -704 448 -704 -304
WIRE 0 480 0 -624
WIRE 240 480 0 480
WIRE 352 480 352 0
WIRE 352 480 320 480
WIRE 432 480 352 480
WIRE 576 480 512 480
WIRE 1584 480 1584 176

WIRE -944 512 -944 448

WIRE -608 528 -656 528
WIRE -496 528 -496 0
WIRE -496 528 -528 528

WIRE -288 528 -496 528

WIRE -112 528 -208 528
WIRE 0 528 0 480
WIRE 0 528 -112 528
WIRE 0 688 0 528
WIRE 0 688 -240 688
WIRE -240 768 -240 688
WIRE 0 816 0 688
WIRE -1312 976 -1312 -32
WIRE -1088 976 -1088 208
WIRE -1088 976 -1312 976
WIRE -944 976 -944 576
WIRE -944 976 -1088 976
WIRE -704 976 -704 544
WIRE -704 976 -944 976
WIRE -400 976 -400 288
WIRE -400 976 -704 976
WIRE -240 976 -240 832
WIRE -240 976 -400 976
WIRE 0 976 0 896
WIRE 0 976 -240 976
WIRE 624 976 624 496
WIRE 624 976 0 976
WIRE 832 976 832 -16
WIRE 832 976 624 976
WIRE 1264 976 1264 592
WIRE 1264 976 832 976
WIRE 1584 976 1584 544
WIRE 1584 976 1264 976
WIRE 1664 976 1584 976
WIRE 1792 976 1792 464
WIRE 1792 976 1664 976
WIRE 1824 976 1792 976
WIRE 1872 976 1872 -160
WIRE 1872 976 1824 976
WIRE 1920 976 1872 976
WIRE -1312 1008 -1312 976
WIRE 1664 1024 1664 976
WIRE 1824 1072 1824 976
WIRE 960 1104 960 176
WIRE 1104 1104 960 1104
WIRE 1296 1104 1168 1104
WIRE 912 1232 912 288
WIRE 1104 1232 912 1232
WIRE 1296 1232 1296 1104
WIRE 1296 1232 1168 1232
WIRE 1376 1232 1296 1232
WIRE 1504 1232 1456 1232
WIRE 1664 1232 1664 1088
WIRE 1664 1232 1568 1232
WIRE 1824 1232 1824 1152
WIRE 1824 1232 1664 1232
FLAG -1312 1008 0
FLAG -544 -368 Vct
FLAG -656 -464 tank-
FLAG 1264 512 CancellingV
FLAG 464 -464 tank+
FLAG -112 528 Bias
SYMBOL ind2 -688 -288 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.088 Cpar=10p

SYMBOL ind2 -256 -288 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.022

SYMBOL cap -208 -480 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 46 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2n

SYMBOL res 464 480 M90

WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2
SYMATTR InstName R1

SYMATTR Value 10
SYMBOL nmos 576 400 R0

SYMATTR InstName M1
SYMATTR Value Si3440DV

SYMBOL nmos -656 448 M0

SYMATTR InstName M2
SYMATTR Value Si3440DV

SYMBOL res -576 528 M90

WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2
SYMATTR InstName R2

SYMATTR Value 10
SYMBOL ind2 -960 -800 R0
SYMATTR InstName L7

SYMATTR Value 2.2m
SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p

SYMBOL diode 1072 192 R270

WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RFU02VS8S

SYMBOL diode 1072 304 R270

WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RFU02VS8S

SYMBOL diode 1168 1088 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D3
SYMATTR Value RFU02VS8S

SYMBOL diode 1168 1216 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D4
SYMATTR Value RFU02VS8S

SYMBOL cap 1568 480 R0

SYMATTR InstName C2
SYMATTR Value 10n

SYMBOL cap 1648 1024 R0

WINDOW 3 17 75 Left 2
SYMATTR Value 10n
SYMATTR InstName C3

SYMBOL res 1792 416 R0
SYMATTR InstName R4
SYMATTR Value 47k
SYMBOL res 1824 1104 R0
SYMATTR InstName R5
SYMATTR Value 47k

SYMBOL cap -1104 144 R0
SYMATTR InstName C4
SYMATTR Value 1µ

SYMBOL res 0 848 R0
WINDOW 3 21 18 Left 2
SYMATTR Value 4k3
SYMATTR InstName R11
SYMBOL ind2 -416 192 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 12.2m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p

SYMBOL ind2 -192 272 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L3
SYMATTR Value 12.2m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL zener -928 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMATTR Value 1N5371B
SYMBOL FerriteBead -944 544 R180

SYMATTR InstName L15

SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL ind2 1360 1248 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 -6 69 VBottom 2

SYMATTR InstName L9

SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=10p
SYMBOL voltage -1312 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value 24

SYMBOL ind2 1376 160 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 48 56 VTop 2
SYMATTR InstName L8
SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=10p

SYMBOL FerriteBead 1456 176 R90

WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L11
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f

SYMBOL FerriteBead 1536 1232 R90

WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L12
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"

SYMBOL FerriteBead -944 -640 R180
SYMATTR InstName L16

SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL FerriteBead -1168 -848 R90

WINDOW 0 -16 0 VBottom 2

SYMATTR InstName L13

SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f

SYMBOL ind2 1248 496 R0
SYMATTR InstName L14
SYMATTR Value 153m
SYMBOL ind2 -192 512 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName L5
SYMATTR Value 7.02µ
SYMBOL ind2 336 464 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName L6
SYMATTR Value 7.02µ
SYMBOL res 0 -672 R0
WINDOW 3 21 18 Left 2
SYMATTR Value 18k
SYMATTR InstName R3
SYMBOL cap -256 768 R0
SYMATTR InstName C5
SYMATTR Value 100n
SYMBOL res 832 -592 R0
WINDOW 3 21 18 Left 2
SYMATTR Value 15k
SYMATTR InstName R6
SYMBOL diode -480 0 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2

SYMATTR InstName D7
SYMATTR Value 1N4148
SYMBOL diode 368 0 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2

SYMATTR InstName D8
SYMATTR Value 1N4148
SYMBOL res 512 -160 R90

WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2

SYMATTR InstName R7
SYMATTR Value 820
SYMBOL cap 1856 -224 R0
SYMATTR InstName C6
SYMATTR Value 100n
SYMBOL zener 848 -16 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2

SYMATTR InstName D6
SYMATTR Value BZX84C10L
SYMBOL res 128 -464 M90

WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2

SYMATTR InstName R8
SYMATTR Value 33
SYMBOL FerriteBead 736 -160 R90

WINDOW 0 -16 0 VBottom 2

SYMATTR InstName L10
SYMATTR Value 12µ

SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f
TEXT -1232 1032 Left 2 !.tran 0 10m 0m 10n
TEXT -1232 1096 Left 2 !K1 L1 L2 L3 L4 L5 L6 0.99
TEXT -856 1032 Left 2 !.ic I(L7=1u) I(L1=1u) V(Bias)=3.824
TEXT -848 1096 Left 2 !K2 L7 L8 L9 L14 0.99

--
Bill Sloman, Sydney

[Piglet]

About half the resistors in that ASC schematic came misplaced and needed
editting back onto their wires. I don't see the point of those ferrite
beads. It works well. Looks to me like you have re-invented the Weinberg
converter!

piglet

[Bill Sloman]

On Saturday, June 19, 2021 at 5:37:42 PM UTC+10, piglet wrote:
> On 19/06/2021 04:55, Bill Sloman wrote:
> > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote:
> >> On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote:
> >>> Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:
> >
> > <snip>
> >
> >>> Thank you for your effort! It's still very interesting! :)
> >
> > I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them.

<snip>

> About half the resistors in that ASC schematic came misplaced and needed

> editing back onto their wires.

That's disappointing.

> I don't see the point of those ferrite beads.

Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the wrost possible moment.

> It works well. Looks to me like you have re-invented the Weinberg converter!

Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by.

https://www.ti.com/seclit/ug/slyu036/slyu036.pdf

What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out

You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across."

Cursitor Doom would probably explain to me that this is because it isn't much of an idea, but he'd say that even if were a stroke of genius (which is unlikely to be any more correct).

--
Bill Slona, Sydney

[Piglet]

On 19/06/2021 12:30, Bill Sloman wrote:
>
> Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the wrost possible moment.
>

Well, L10 is probably not doing much seeing as it is in series with 820
ohms R7?

>> It works well. Looks to me like you have re-invented the Weinberg converter!
>
> Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by.
>
> https://www.ti.com/seclit/ug/slyu036/slyu036.pdf
>
> What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out
>
> You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across."
>

I don't see why it should be hard to explain, the ripple cancellation
scheme seems sound enough. I still contend it is conceptually broadly
similar to Weinberg's low noise converter of ca 50 years ago.

However I am worried that the parasitics of your simulated coils may be
too low to be realizable easily in real life. For instance the 153mH L8
L9 were only given 10pF shunt capacitance. The secondary windings L3 L4
would probably be bifilar or at least share the same bobbin section but
you gave them no end-to-end interwinding capacitance. The moment larger
strays are included the rectifier current waveform changes radically.

While the ripple cancellation scheme could be great at higher powers I
think at this low power good enough results could be got using single
coil off the peg discrete inductors for primary center-tap feed and
choke input rectifiers. That also reduces primary side-secondary side
capacitance as only one transformer is needed.

BJTs can be easier to bias at these low powers. Here is my
bastardization of your circuit, using off-the-shelf L7 L8 L9 inductors
and a brute force second stage RC output filter to get 9mV p-p ripple.

Version 4
SHEET 1 1944 1284

WIRE -128 -320 -592 -320
WIRE -32 -320 -128 -320
WIRE -32 -160 -32 -320
WIRE -128 -112 -128 -320
WIRE -592 -96 -592 -320
WIRE 384 -80 320 -80
WIRE 528 -80 464 -80
WIRE 640 -80 528 -80
WIRE 704 -80 640 -80
WIRE 816 -80 768 -80
WIRE 864 -80 816 -80
WIRE 1104 -80 944 -80
WIRE 1152 -80 1104 -80
WIRE 1280 -80 1232 -80
WIRE 1344 -80 1280 -80
WIRE 528 -48 528 -80
WIRE 1104 16 1104 -80
WIRE 320 32 320 -80
WIRE 384 32 320 32
WIRE 528 32 528 16
WIRE 528 32 464 32
WIRE 592 32 528 32
WIRE 704 32 592 32
WIRE 816 32 816 -80
WIRE 816 32 768 32
WIRE -32 64 -32 -80
WIRE 1280 144 1280 -80
WIRE -288 160 -320 160
WIRE -32 160 -32 64
WIRE -32 160 -208 160
WIRE 96 160 -32 160
WIRE 240 160 176 160
WIRE 640 160 640 -80
WIRE 592 256 592 32
WIRE 1104 288 1104 80
WIRE 1280 288 1280 208
WIRE 1280 288 1104 288
WIRE -320 336 -320 160
WIRE -272 336 -320 336
WIRE -16 336 -272 336
WIRE 112 336 48 336
WIRE 240 336 240 160
WIRE 240 336 192 336
WIRE 592 400 592 320
WIRE 640 400 640 224
WIRE 640 400 592 400
WIRE 688 400 640 400
WIRE 816 400 768 400
WIRE 848 400 816 400
WIRE 1008 400 928 400
WIRE 1040 400 1008 400
WIRE 1056 400 1040 400
WIRE 1344 400 1344 -80
WIRE 1008 432 1008 400
WIRE -320 448 -320 336
WIRE -272 448 -320 448
WIRE 240 448 240 336
WIRE 240 448 -208 448
WIRE 1056 448 1056 400
WIRE -320 544 -320 448
WIRE 240 544 240 448
WIRE 816 560 816 400
WIRE -128 592 -128 -32
WIRE -128 592 -256 592
WIRE -48 592 -128 592
WIRE 176 592 32 592
WIRE -592 720 -592 -16
WIRE -320 720 -320 640
WIRE -320 720 -592 720
WIRE 240 720 240 640
WIRE 240 720 -320 720
WIRE 320 720 320 32
WIRE 816 720 816 624
WIRE 816 720 320 720
WIRE 1008 720 1008 512
WIRE 1008 720 816 720
WIRE 1056 720 1056 512
WIRE 1056 720 1008 720
WIRE 1104 720 1104 288
WIRE 1104 720 1056 720
WIRE 1344 720 1344 480
WIRE 1344 720 1104 720
WIRE -592 752 -592 720
WIRE 1344 768 1344 720
FLAG -592 752 0
FLAG -32 64 Vct
FLAG -272 336 tank-
FLAG 240 336 tank+
FLAG 1344 768 0
FLAG 1344 -80 VOUT_P
FLAG 1040 400 VOUT_N
SYMBOL ind2 -304 176 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.176m
SYMATTR Type ind

SYMATTR SpiceLine Rser=0.5 Cpar=8p
SYMBOL ind2 80 176 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.176m
SYMATTR Type ind

SYMATTR SpiceLine Rser=0.5 Cpar=8p
SYMBOL cap 48 320 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 46 32 VTop 2
SYMATTR InstName C1

SYMATTR Value 1n
SYMBOL ind -48 -176 R0
SYMATTR InstName L7
SYMATTR Value 3.3m
SYMATTR SpiceLine Rser=8 Cpar=18p
SYMATTR Type ind2
SYMBOL diode 704 -64 R270

WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RFU02VS8S

SYMBOL diode 704 48 R270

WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RFU02VS8S

SYMBOL diode 656 224 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2

SYMATTR InstName D3
SYMATTR Value RFU02VS8S

SYMBOL diode 608 320 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2

SYMATTR InstName D4
SYMATTR Value RFU02VS8S

SYMBOL cap 1088 16 R0
SYMATTR InstName C5
SYMATTR Value 47n
SYMBOL cap 832 624 R180
WINDOW 3 24 8 Left 2
WINDOW 0 24 56 Left 2
SYMATTR Value 47n
SYMATTR InstName C4
SYMBOL res 1328 384 R0
SYMATTR InstName R6
SYMATTR Value 47k
SYMBOL res 1024 528 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2

SYMATTR InstName R5
SYMATTR Value 47k

SYMBOL ind2 368 -64 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 12.2m
SYMATTR Type ind

SYMATTR SpiceLine Rser=10 Cpar=14p
SYMBOL ind2 480 16 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L3
SYMATTR Value 12.2m
SYMATTR Type ind

SYMATTR SpiceLine Rser=10 Cpar=14p
SYMBOL ind 672 416 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 -6 69 VBottom 2
SYMATTR InstName L9

SYMATTR Value 100m
SYMATTR SpiceLine Rser=190 Cpar=38p
SYMATTR Type ind2
SYMBOL voltage -592 -112 R0

WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2

SYMATTR InstName V1
SYMATTR Value 24

SYMBOL ind 960 -96 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 48 56 VTop 2
SYMATTR InstName L8

SYMATTR Value 100m
SYMATTR SpiceLine Rser=190 Cpar=38p
SYMATTR Type ind2
SYMBOL ind2 48 576 R90

WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L5

SYMATTR Value 3µ
SYMATTR SpiceLine Cpar=1.5p
SYMBOL res -144 -128 R0

WINDOW 3 21 18 Left 2

SYMATTR Value 22k
SYMATTR InstName R1
SYMBOL res 96 320 M90

WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2
SYMATTR InstName R2

SYMATTR Value 56
SYMBOL npn 176 544 R0
SYMATTR InstName Q1
SYMATTR Value 2N5550
SYMBOL npn -256 544 M0
SYMATTR InstName Q2
SYMATTR Value 2N5550
SYMBOL cap 512 -48 R0
SYMATTR InstName C3
SYMATTR Value 220p
SYMBOL cap -208 432 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2

SYMATTR InstName C2
SYMATTR Value 15p
SYMBOL res 1136 -64 R270

WINDOW 0 32 56 VTop 2

WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 832 416 R270

WINDOW 0 32 56 VTop 2

WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL cap 1040 448 R0
SYMATTR InstName C6
SYMATTR Value 10n
SYMBOL cap 1264 144 R0
SYMATTR InstName C7
SYMATTR Value 10n
TEXT -648 832 Left 2 !.tran 0 10m 0m 10n
TEXT -648 896 Left 2 !K1 L1 L2 L3 L4 L5 0.99
TEXT 920 -304 Left 2 ;EPW-BS-SED Jun 2021 P-P HV Converter
TEXT -272 504 Left 2 ;Cprim stray

piglet

[Bill Sloman]

On Sunday, June 20, 2021 at 8:54:44 PM UTC+10, piglet wrote:
> On 19/06/2021 12:30, Bill Sloman wrote:
> >

> > Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the worst possible moment.

> >
> Well, L10 is probably not doing much seeing as it is in series with 820
> ohms R7?
> >> It works well. Looks to me like you have re-invented the Weinberg converter!
> >
> > Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by.
> >
> > https://www.ti.com/seclit/ug/slyu036/slyu036.pdf
> >
> > What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out
> >
> > You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across."
> >
> I don't see why it should be hard to explain, the ripple cancellation scheme seems sound enough. I still contend it is conceptually broadly similar to Weinberg's low noise converter of ca 50 years ago.

Which wasn't a resonant converter, and hasn't shown up on my radar at all.

> However I am worried that the parasitics of your simulated coils may be too low to be realizable easily in real life. For instance the 153mH L8 L9 were only given 10pF shunt capacitance.

I was figuring that they'd have to be bank wound to get them that low. There was a time when you could buy four-section coil formers for some RM cores that made that reasonably practical. I posted a bit on calculating these capacitances here, back in 2013.

> The secondary windings L3 L4 would probably be bifilar or at least share the same bobbin section but you gave them no end-to-end interwinding capacitance.

You certainly wouldn't wind the output windings as twisted pair - as you say, it would introduce a lot of inter-winding capacitance. It's perfectly calculable, once you've worked out the wire diameter, got the thickness of the insulation and worked out the length of twisted pair in the winding.

If at all possible I'd put them on separate bobbin sections.

> The moment larger strays are included the rectifier current waveform changes radically.

They form part of the tank circuit - that's what make the Baxandall approach attractive, since all the strays are all coupled into one closely coupled tank circuit.

If you do it exactly right , you don't need a tank capacitor at all, because the strays will do the whole job. The dielectric isn't ideal.

> While the ripple cancellation scheme could be great at higher powers I think at this low power good enough results could be got using single coil off the peg discrete inductors for primary center-tap feed and choke input rectifiers.

Obviously - that's what everybody has been doing since 1959. There are a lot of products on the market that demonstrate exactly this point.

> That also reduces primary side-secondary side capacitance as only one transformer is needed.

You definitely need the primary side inductor, if you want Baxandall level efficiencies. My point was that if you added two over-windings to that inductor you could use them to cancel the AC voltage on the rectified output.

> BJTs can be easier to bias at these low powers.

But - as Baxandall pointed out in 1959 - if you make the primary side inductor too big, the circuit can "squeg". He didn't know what was going on, and I don't either (though I do have my suspoicions), but if you use LT Spice to look at a version of a BJTdriven circuit with a big primary side inductor it won't squeg - during startup the inductor pulls the centre-tap below the rail, but this eventually goes away in the simulation, which doesn't happen in real life My guess is that reflects a defect in the Gummel-Poon model of the BJT in inverted operation. The VBIC model might do better, but the semi-conductor business treats VBIC models as commercial in confidence. MOSFet drivers don't seem to have the same problem.

Your circuit reverse biases your transistor base-emitter junction by about 4V. Anything more than 6V blows them up. Your 3u (actually 3.12u) is two turns on the EFD15-5-8 core. Don't get greedy and use three.

> Here is my bastardization of your circuit, using off-the-shelf L7 L8 L9 inductors and a brute force second stage RC output filter to get 9mV p-p ripple.

It's perfectly sensible, and that's what people have been doing since 1959. It consequently isn't actually all that interesting.

--
Bill Sloman, Sydney

[Bill Sloman]

On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote:
> On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote:
> > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote:
> > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:
> <snip>
> > > Thank you for your effort! It's still very interesting! :)
> I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them.
>
> This is about as simple as the circuit can get. The MOSFets are driven by a centre-tapped 6-turn winding (L5 and L6) and the EFD55-8 former has only got eight pins, which means that on a real circuit you'd have to improvise a bit.
>
> For the circuit to start the bias voltage on the centre tap has to be just high enough for both MOSFets to be turned on, which is a bit too high to let the circuit work properly once it running as intended. The network around D6, D7 and D8 lets bias voltage get pulled down to the point where the circuit will work correctly, once it is operating as intended.
>
> With values chosen, each of D7 and D8 is pulling current out of the bias node for about a quartrer the time, and I imagine that that will probably work over the tolerance range for the MOSFets M1 and M2 - Siliconix Si3.440DV parts which happened to be in the LT Spice component range.
>
> R8 damps the 2.5MHz parastic oscillation driven by the switching transients. A more complex design could have smaller switching transients, but it wouldn't be worth posting here.
>
> L14 is a totally dummy part - it exists to create the waveform V(cancelingV) which is there to make it easier to explain what L8 an L9 were put in to do. If you plot V(n009) + V(cancellingv) or V(n018) - V(cancellingv) you get pretty close to flat +200V and -200V traces, which are a lot easier to filter than the voltage coming out of the rectifiers.
>
> The circuit seems to deliver 4mA at +200V and -200V - 1.6 Watt - and draw 81mA at 24V - 1.95 Watt, which 82% efficiency. Two mA of the current drawn is setting up bias voltages. The inductor resistances aren't properly worked out, so this isn't all that reliable.
>
> I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across.

I've been thinking about a more complicated solution, and the one that comes to mind would use a 4046 to generate a roughly 5MHz clock and a cheap programmable logic device - the XC2C64A-7VQG44C comes to mind, though it isn't all that cheap - to divide this down to generate two roughly 100kHz non-over-lapping drive waveforms for the MOSFets, plus a square wave to drive one of the phase comparators on the 4046, to lock it to the nominally 100kHz sine wave coming out of a one turn winding on the transformer (L5 in the "simple' circuit).

Divide by fifty is a six-stage binary counter, so the XC2C64A with it's 64 cells is bigger than necessary. The ICT PA7024 which I used back in 1992 would probably be quite big enough.

The tank circuit doesn't do anything silly if you drive it off-resonance - the peak voltages move away from 90 degrees and 270 degrees, which the phase comparator can detect and use to lock the actual operating frequency to the resonant frequency, even if moves as the inductor warms up
--
Bill Sloman, Sydney

[Bill Sloman]

On Thursday, June 24, 2021 at 12:09:31 AM UTC+10, Bill Sloman wrote:
> On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote:
> > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote:
> > > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote:
> > > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:

<snip>

I finally got around to reading the "zero ripple" paper

< https://sci-hub.do/10.1109/tpel.2007.909192 >

more carefully and it looks as if they want to run a Baxandall-like inverter a bit below resonance, which sort of works, but the centre tap voltage sits at 0V for an appreciable period each cycle, and peaks higher ( 46.14V in the example circuit below - versus 37.7V for an ideal Baxandall converter) while the current through the feed inductor peaks a bit higher.

My ripple cancelling scheme doesn't work as well either but there's not a lot in it. It strikes that you could start the converter at a frequency that is guaranteed to be below the resonant frequency - 17% below the on-tolerance value should be enough for the circuit we've been looking at - and monitor the length of time that the centre tap stays close to the negative rail with something relatively slow (like a cheap single chip microprocessor) and inch it up until it gets close to value you'd see at the resonant frequency, and stick with that.

Version 4
SHEET 1 1944 1396
WIRE -1888 -848 -2000 -848
WIRE -1776 -848 -1824 -848
WIRE -1632 -848 -1776 -848
WIRE 1712 -848 -1632 -848
WIRE -1632 -784 -1632 -848
WIRE -1632 -672 -1632 -704

WIRE -656 -464 -704 -464
WIRE -272 -464 -656 -464

WIRE 16 -464 -208 -464
WIRE 464 -464 96 -464

WIRE 624 -464 464 -464

WIRE -1632 -368 -1632 -608
WIRE -544 -368 -1632 -368

WIRE -384 -368 -544 -368
WIRE -704 -304 -704 -464
WIRE -672 -304 -704 -304
WIRE -384 -304 -384 -368
WIRE -384 -304 -592 -304
WIRE -240 -304 -384 -304
WIRE 624 -304 624 -464
WIRE 624 -304 -160 -304

WIRE 1872 -224 1872 -288

WIRE -2000 -112 -2000 -848
WIRE -1776 144 -1776 -848

WIRE -400 176 -624 176
WIRE 960 176 -320 176
WIRE 1072 176 960 176
WIRE 1200 176 1136 176
WIRE 1280 176 1200 176
WIRE 1424 176 1360 176
WIRE 1584 176 1488 176
WIRE 1792 176 1584 176
WIRE -624 288 -624 176
WIRE -400 288 -624 288
WIRE -288 288 -400 288
WIRE 912 288 -208 288
WIRE 1072 288 912 288
WIRE 1200 288 1200 176
WIRE 1200 288 1136 288

WIRE -1632 384 -1632 -368
WIRE 320 384 -1456 384

WIRE 1792 384 1792 176
WIRE 624 400 624 -304

WIRE -1456 480 -1456 384
WIRE 320 480 320 384
WIRE 432 480 320 480

WIRE 576 480 512 480
WIRE 1584 480 1584 176

WIRE -1632 512 -1632 448
WIRE -704 560 -704 -304
WIRE -912 640 -1008 640

WIRE -752 640 -832 640

WIRE -1008 816 -1008 640
WIRE -2000 1088 -2000 -32
WIRE -1776 1088 -1776 208
WIRE -1776 1088 -2000 1088
WIRE -1632 1088 -1632 576
WIRE -1632 1088 -1776 1088
WIRE -1456 1088 -1456 560
WIRE -1456 1088 -1632 1088
WIRE -1008 1088 -1008 896
WIRE -1008 1088 -1456 1088
WIRE -704 1088 -704 656
WIRE -704 1088 -1008 1088
WIRE -400 1088 -400 288
WIRE -400 1088 -704 1088
WIRE 624 1088 624 496
WIRE 624 1088 -400 1088
WIRE 1264 1088 1264 592
WIRE 1264 1088 624 1088
WIRE 1584 1088 1584 544
WIRE 1584 1088 1264 1088
WIRE 1664 1088 1584 1088
WIRE 1792 1088 1792 464
WIRE 1792 1088 1664 1088
WIRE 1824 1088 1792 1088
WIRE 1920 1088 1824 1088
WIRE -2000 1120 -2000 1088
WIRE 1664 1136 1664 1088
WIRE 1824 1184 1824 1088
WIRE 960 1216 960 176
WIRE 1104 1216 960 1216
WIRE 1296 1216 1168 1216
WIRE 912 1344 912 288
WIRE 1104 1344 912 1344
WIRE 1296 1344 1296 1216
WIRE 1296 1344 1168 1344
WIRE 1376 1344 1296 1344
WIRE 1504 1344 1456 1344
WIRE 1664 1344 1664 1200
WIRE 1664 1344 1568 1344
WIRE 1824 1344 1824 1264
WIRE 1824 1344 1664 1344
FLAG -2000 1120 0

FLAG -544 -368 Vct
FLAG -656 -464 tank-
FLAG 1264 512 CancellingV
FLAG 464 -464 tank+

SYMBOL ind2 -688 -288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.088 Cpar=10p
SYMBOL ind2 -256 -288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.176m
SYMATTR Type ind
SYMATTR SpiceLine Rser=0.022
SYMBOL cap -208 -480 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 46 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2n
SYMBOL res 464 480 M90
WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2
SYMATTR InstName R1

SYMATTR Value 22

SYMBOL nmos 576 400 R0
SYMATTR InstName M1
SYMATTR Value Si3440DV

SYMBOL nmos -752 560 R0

SYMATTR InstName M2
SYMATTR Value Si3440DV

SYMBOL res -880 640 M90

WINDOW 0 -18 21 VBottom 2
WINDOW 3 19 15 VTop 2
SYMATTR InstName R2

SYMATTR Value 22
SYMBOL ind2 -1648 -800 R0

SYMATTR InstName L7
SYMATTR Value 2.2m
SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p
SYMBOL diode 1072 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RFU02VS8S
SYMBOL diode 1072 304 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RFU02VS8S

SYMBOL diode 1168 1200 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D3
SYMATTR Value RFU02VS8S

SYMBOL diode 1168 1328 R90

WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D4
SYMATTR Value RFU02VS8S
SYMBOL cap 1568 480 R0
SYMATTR InstName C2
SYMATTR Value 10n

SYMBOL cap 1648 1136 R0

WINDOW 3 17 75 Left 2
SYMATTR Value 10n
SYMATTR InstName C3
SYMBOL res 1792 416 R0
SYMATTR InstName R4
SYMATTR Value 47k

SYMBOL res 1824 1216 R0

SYMATTR InstName R5
SYMATTR Value 47k

SYMBOL cap -1792 144 R0

SYMATTR InstName C4
SYMATTR Value 1µ

SYMBOL ind2 -416 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 12.2m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p
SYMBOL ind2 -192 272 R90
WINDOW 0 4 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L3
SYMATTR Value 12.2m
SYMATTR Type ind
SYMATTR SpiceLine Rser=10 Cpar=10p

SYMBOL zener -1616 448 R180

WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5

SYMATTR Value 1N5375B
SYMBOL FerriteBead -1632 544 R180

SYMATTR InstName L15
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL ind2 1360 1360 R270

WINDOW 0 32 56 VTop 2
WINDOW 3 -6 69 VBottom 2
SYMATTR InstName L9
SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=10p

SYMBOL voltage -2000 -128 R0

WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL ind2 1376 160 R90
WINDOW 0 4 56 VBottom 2
WINDOW 3 48 56 VTop 2
SYMATTR InstName L8
SYMATTR Value 153m
SYMATTR SpiceLine Rser=1 Cpar=10p
SYMBOL FerriteBead 1456 176 R90
WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L11
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f

SYMBOL FerriteBead 1536 1344 R90

WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L12
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050"

SYMBOL FerriteBead -1632 -640 R180

SYMATTR InstName L16
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p

SYMBOL FerriteBead -1856 -848 R90

WINDOW 0 -16 0 VBottom 2
SYMATTR InstName L13
SYMATTR Value 12µ
SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f
SYMBOL ind2 1248 496 R0
SYMATTR InstName L14
SYMATTR Value 153m

SYMBOL voltage -1008 800 R0

WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1

SYMATTR InstName V2
SYMATTR Value PULSE(0 8 0u 25n 25n 5.95u 12u 11000)
SYMBOL voltage -1456 464 R0

WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=1

SYMATTR InstName V3
SYMATTR Value PULSE(0 8 6u 25n 25n 5.95u 12u 11000)
SYMBOL res 48 -464 M90

WINDOW 0 -26 11 VBottom 2
WINDOW 3 22 8 VTop 2

SYMATTR InstName R3
SYMATTR Value 33
TEXT -1920 1144 Left 2 !.tran 0 10m 0m 10n
TEXT -1792 1208 Left 2 !K1 L1 L2 L3 L4 0.99
TEXT -856 1144 Left 2 !.ic I(L7=1u) I(L1=1u) V(Bias)=5)
TEXT -848 1208 Left 2 !K2 L7 L8 L9 L14 0.99

--
Bill Sloman, Sydney

[Anthony William Sloman]

On Saturday, June 26, 2021 at 6:50:39 PM UTC+10, Anthony William Sloman wrote:
> On Thursday, June 24, 2021 at 12:09:31 AM UTC+10, Bill Sloman wrote:
> > On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote:
> > > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote:
> > > > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote:
> > > > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:
>
> <snip>
> I finally got around to reading the "zero ripple" paper
>
> < https://sci-hub.do/10.1109/tpel.2007.909192 >
>
> more carefully and it looks as if they want to run a Baxandall-like inverter a bit below resonance, which sort of works, but the centre tap voltage sits at 0V for an appreciable period each cycle, and peaks higher ( 46.14V in the example circuit below - versus 37.7V for an ideal Baxandall converter) while the current through the feed inductor peaks a bit higher.
>
> My ripple cancelling scheme doesn't work as well either but there's not a lot in it. It strikes that you could start the converter at a frequency that is guaranteed to be below the resonant frequency - 17% below the on-tolerance value should be enough for the circuit we've been looking at - and monitor the length of time that the centre tap stays close to the negative rail with something relatively slow (like a cheap single chip microprocessor) and inch it up until it gets close to value you'd see at the resonant frequency, and stick with that.

Cheap single chip microcontrollers seem to be quite quick these days. I've just had a look at the dsPIC33EPXXXGP50X data sheet

http://ww1.microchip.com/downloads/en/devicedoc/ds-70657b.pdf

It's 470 pages, and I only looked at the bit about the clock - pages 143-152 - which seems to suggest that you could clock at at 140Mz if you keep the chip cooler than 85C.

Element 14 has 33 DSPIC33CK64MC105-I/PT in stock in Australia for couple of dollars each $A3.23 ($A3.55 including GST which I would have to pay). The programming kit would be more expensive.

That's fast enough to do a proper non-overlapping drive for the Siliconix Si3440DV which has a worst case turn-on delay time of 15nsec, and a worst case turn-off delay time of 30nsec, which does imply half an amp of gate drive (or 1.6mA averaged over the whole duty cycle). The microcontroller draws up 35mA from 3.3Vwhen running at 70MIPs (which you probably wouldn't want to draw directly from a 24V rail) so you might be able to get a bit of current gain out of the 3.3V rail to make this happen relatively cheaply.

--
Bill Sloman, Sydney