ftp://jjlarkin.lmi.net/Quantizer.jpg
It wasn't hard, but the HELP is really obscure about syntax, and there
is no example of a schematic with a b-source that I could find.
There is a sample-and-hold schematic symbol, so one can simulate the
effects of a clocked ADC or a DAC on a control loop.
John
Version 4
SHEET 1 880 680
WIRE 48 48 0 48
WIRE 112 48 48 48
WIRE 384 48 320 48
WIRE 432 48 384 48
WIRE 0 96 0 48
WIRE 112 112 112 48
WIRE 320 112 320 48
WIRE 432 128 432 48
WIRE 0 224 0 176
WIRE 112 224 112 192
WIRE 320 240 320 192
WIRE 432 240 432 208
FLAG 0 224 0
FLAG 320 240 0
FLAG 112 224 0
FLAG 432 240 0
FLAG 48 48 X
FLAG 384 48 OUT
SYMBOL bv 320 96 R0
WINDOW 3 36 198 Left 0
SYMATTR InstName B1
SYMATTR Value V=int(5.1*V(X))*0.2
SYMBOL voltage 0 80 R0
WINDOW 3 16 199 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k 0 0 0 3)
SYMBOL res 96 96 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 416 112 R0
SYMATTR InstName R2
SYMATTR Value 1k
TEXT 144 40 Left 0 !.tran 0 .005 0 1u
Use round() instead of int():
SYMATTR Value V=round(5*V(X))/5
Hello John,
Here is an example with the "Sample"-device.
Best regards,
Helmut
Version 4
SHEET 1 920 680
WIRE -112 -16 -160 -16
WIRE 176 0 144 0
WIRE -160 32 -160 -16
WIRE 448 48 352 48
WIRE 592 48 544 48
WIRE 176 64 144 64
WIRE 544 80 544 48
WIRE -160 144 -160 112
WIRE -112 208 -160 208
WIRE 544 208 544 160
WIRE -160 256 -160 208
WIRE -160 368 -160 336
FLAG 544 208 0
FLAG 592 48 sq
IOPIN 592 48 Out
FLAG -160 144 0
FLAG -112 -16 s0
FLAG 144 0 s0
FLAG -160 368 0
FLAG -112 208 fs
FLAG 144 64 fs
FLAG 448 48 vs0
SYMBOL bv 544 64 R0
SYMATTR InstName B1
SYMATTR Value V=int(V(vs0))
SYMBOL voltage -160 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 7.5 {f0})
SYMBOL SpecialFunctions\\sample 256 32 R0
WINDOW 3 0 0 Invisible 0
SYMATTR InstName A1
SYMATTR Value2 vhigh=1e6 vlow=-1e6
SYMATTR Value vt=0.5
SYMBOL voltage -160 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1n 1n 10u {1/fs})
TEXT -176 -160 Left 0 !.tran 0 3m 0 1u
TEXT -176 -128 Left 0 !.options plotwinsize=0
TEXT -176 -96 Left 0 !.param f0=1k fs=20k
>
>Here's a quantizer in LT Spice:
>
>ftp://jjlarkin.lmi.net/Quantizer.jpg
>
>It wasn't hard, but the HELP is really obscure about syntax, and there
>is no example of a schematic with a b-source that I could find.
>
>There is a sample-and-hold schematic symbol, so one can simulate the
>effects of a clocked ADC or a DAC on a control loop.
>
>John
>
>
[snip]
Where's the CLOCK?
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The only thing bipartisan in this country is hypocrisy
That depends on your personal definition of "quantizer." Once the
structure is there, one can play with the equation. I'll be simulating
a 12-bit ADC and a 10-bit DAC, so exactly where the transitions happen
doesn't matter much.
John
That does look a little nicer.
John
Hmm, I like zero accumulated errors, so your staircase waveform
looked somewhat anorexic to me ;) I imagine the quantised waveform
being filtered back to sinewave.
> Once the
>structure is there, one can play with the equation. I'll be simulating
>a 12-bit ADC and a 10-bit DAC, so exactly where the transitions happen
>doesn't matter much.
Yep, except I had no idea where to find the 'lever' to change it, but
another poster already pointed that out.
Only recently did I start playing with LTSpice, much to learn as I've
not used spice before (returning to electronics design after a 'short'
break in 1993).
Grant.
--
http://bugs.id.au/
"round" does look nicer, in having zero average errors through the
quantizer. I'm mostly interested in how using the ADC and DAC in the
NXP ARM will change the dynamics of a loop that I'm simulating as all
analog but will in fact be digital. The uP has a 10-bit DAC, which
isn't good enough, so if we oversample hard (100 KHz) and add some
lowpass filtering downstream of the dac, we should be able to dither a
few more bits. That part will be interesting to simulate, but doesn't
care much how the quantizers round. The actual NXP ADC and DAC will do
whatever they do.
>
>> Once the
>>structure is there, one can play with the equation. I'll be simulating
>>a 12-bit ADC and a 10-bit DAC, so exactly where the transitions happen
>>doesn't matter much.
>
>Yep, except I had no idea where to find the 'lever' to change it, but
>another poster already pointed that out.
>
>Only recently did I start playing with LTSpice, much to learn as I've
>not used spice before (returning to electronics design after a 'short'
>break in 1993).
I find the HELP in LT Spice to be a bit abstract and not terribly
consistent. More examples would be great. At least one can come to
s.e.d. and ususlly find somebody who knows how to do what you need.
For basic stuff, LT Spice is great and eesy to drive. I can't imagine
how much it has cost the people who sell simulators.
John
[...]
>
> I find the HELP in LT Spice to be a bit abstract and not terribly
> consistent. More examples would be great. At least one can come to
> s.e.d. and ususlly find somebody who knows how to do what you need.
>
> For basic stuff, LT Spice is great and eesy to drive. I can't imagine
> how much it has cost the people who sell simulators.
Yeah, Mike E should be arrested for "using a computer to destroy their
business model"... Why did you do it Mike?? :) :)
Seriously, LTSPice is great, thank you LTC.
--
John Devereux
The quantizer works fine. But when I poke a couple of quantizers into
my control loop model, to simulate ADC quantization, it runs for hours
instead of a fraction of a second. I don't know if it will ever
finish.
There's a message at the bottom of the screen:
Damped Pseudo-Transient Analysis: 0.xxxxx time constants; blah blah
press ESC to quit.
where xxx is increasing like an RC exponential, ie slower and slower.
What does all that mean?
I could program this system, quantization and all, in PowerBasic and I
know it would run fast. But I may as well just build the board and see
what happens, the best model being the thing itself. We can always
tweak the code (or the specs!) as required.
John
>On Sat, 17 Apr 2010 22:10:09 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>
>>Here's a quantizer in LT Spice:
>>
>>ftp://jjlarkin.lmi.net/Quantizer.jpg
>>
>>It wasn't hard, but the HELP is really obscure about syntax, and there
>>is no example of a schematic with a b-source that I could find.
>>
>>There is a sample-and-hold schematic symbol, so one can simulate the
>>effects of a clocked ADC or a DAC on a control loop.
>>
>>John
>>
>>TEXT 144 40 Left 0 !.tran 0 .005 0 1u
>>
>>
>
>The quantizer works fine. But when I poke a couple of quantizers into
>my control loop model, to simulate ADC quantization, it runs for hours
>instead of a fraction of a second. I don't know if it will ever
>finish.
>
>There's a message at the bottom of the screen:
>
>Damped Pseudo-Transient Analysis: 0.xxxxx time constants; blah blah
>press ESC to quit.
>
>where xxx is increasing like an RC exponential, ie slower and slower.
>
>What does all that mean?
>
Which simulator are you using? Perhaps the infinite steepness of the
steps are causing problems. Maybe try to use an RC filter on the
output.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
[snip]
>>
>>The quantizer works fine. But when I poke a couple of quantizers into
>>my control loop model, to simulate ADC quantization, it runs for hours
>>instead of a fraction of a second. I don't know if it will ever
>>finish.
>>
>>There's a message at the bottom of the screen:
>>
>>Damped Pseudo-Transient Analysis: 0.xxxxx time constants; blah blah
>>press ESC to quit.
>>
>>where xxx is increasing like an RC exponential, ie slower and slower.
>>
>>What does all that mean?
>>
>
>Which simulator are you using? Perhaps the infinite steepness of the
>steps are causing problems. Maybe try to use an RC filter on the
>output.
Most home-brew behavioral modeling fails because the inexperienced
modeler makes the function ideal, failing to understand what
arbitrarily fast edges do to simulators.
Ideal diodes can do that :-)
That's why much of the behavioral stuff I've posted uses the TANH
function... smooth, with ALL derivatives existing and finite.
Good mixed-mode simulators (like what you find in Matlab or Scilab)
"understand" sampled-time, and can naturally shift from continuous-time
to sampled time. This is one of the things that I was "asking" for when
I expressed an interest in mixing processor behavior with analog.
The simulator I pine for neither needs nor wants to simulate all the
electrical states of the processor or controller -- it wants to do all
of that numerically, and on a strictly sampled-time basis. But to do
that it needs a clean break between continuous-time simulation and
sampled time simulation.
(note too that when you're 'behind' the sampled-time firewall you can do
things like quantization without causing problems with infinite slopes,
as long as you don't have any algebraic loops).
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
I have the "fancy" mixed-mode version of PSpice A/D+, handling mixed
analog/digital circuitry.
Plus I've made a number of personalized D2A and A2D "tools" to keep
digital separated from analog... keeping the screaming speed.
My behavioral 10-bit A-to-D runs in minutes, while the fully
device-level version takes all night :-)
>Jim Thompson wrote:
The nice thing about using Spice to simulate a mostly-digital control
system (I'm using LT Spice here) is that I can drop in models of
mosfets and opamps and zeners and such, the actual analog parts that
will be outside the uP. And all the schematic/sim/graphing tools are
familiar. The more general system sim programs probably don't do a
very good, or at least very easy, model of electronic components. And
LT Spice is free!
I'd do it in PowerBasic except that I think the sampling and
quantizations are unlikely to have much practical effect on my control
loop, and we can tweak the ARM code as needed to make it work. I was
interested to see if/how the loop would self-dither itself, but I'll
just wait to see the real thing.
John