T PHL and T PLH: why can they be different?
Merciadri Luca
Consider the propagation time from H (high) to L (low): T PHL.
Consider the propagation time from L to H: T PLH. Why are they
generally different (in value)? Note that I'm not here speaking about
the propagation delay, T PD defined as max(T PHL, T PLH).
Thanks.
Phil Hobbs
Did you read anything about how the circuits work? Look for asymmetries
in the device properties and circuit topology.
Hint: the physics of PMOS and NMOS devices are not as similar as they
might seem.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
Merciadri Luca
Thanks!
Rich Grise
bottom.
These days, with CMOS, that difference is being eroded.
Hope This Helps!
Rich
whit3rd
> Merciadri Luca wrote:
>
> > Consider the propagation time from H (high) to L (low): T PHL.
> > Consider the propagation time from L to H: T PLH. Why are they
> > generally different (in value)?
> Generally, because bipolar transistors aren't symmetrical, top to
> bottom.
I think it has more to do with circuit design, actually, in bipolar
ICs.
Look at 100k ECL for a counterexample.
> These days, with CMOS, that difference is being eroded.
Physically, the different mobility of p and n carriers means PMOS
and NMOS transistors can't simultaneously be matched for conductance
and capacitance, in Si. CMOS isn't as symmetric as ECL.
k...@att.bizzzzzzzzzzzz
>On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
>> Merciadri Luca wrote:
>>
>> > Consider the propagation time from H (high) to L (low): T PHL.
>> > Consider the propagation time from L to H: T PLH. Why are they
>> > generally different (in value)?
>
>> Generally, because bipolar transistors aren't symmetrical, top to
>> bottom.
>
>I think it has more to do with circuit design, actually, in bipolar
>ICs.
>Look at 100k ECL for a counterexample.
Your forgetting the output emitter follower. It's hardly symmetrical.
Bipolars are asymmetrical because lateral PNPs suck (so no PNPs).
>> These days, with CMOS, that difference is being eroded.
>
>Physically, the different mobility of p and n carriers means PMOS
>and NMOS transistors can't simultaneously be matched for conductance
>and capacitance, in Si.
A lot closer than PNPs can be matched to NPNs (in a monolithic process).
>CMOS isn't as symmetric as ECL.
ECL isn't symmetric because of the output difference.
whit3rd
<k...@att.bizzzzzzzzzzzz> wrote:
> On Wed, 12 Jan 2011 17:59:32 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
> >> Merciadri Luca wrote:
>
> >> > Consider the propagation time from H (high) to L (low): T PHL.
> >> > Consider the propagation time from L to H: T PLH. Why are they
> >> > generally different (in value)?
> >Look at 100k ECL for a counterexample.
>
> Your forgetting the output emitter follower. It's hardly symmetrical.
Hah! 100k ECL is differential. You kind of walked into that...
> >CMOS isn't as symmetric as ECL.
>
> ECL isn't symmetric because of the output difference.
The relatively small logic margin of ECL means the outputs are
mainly the same impedance whether high or low.
k...@att.bizzzzzzzzzzzz
>On Jan 12, 6:09 pm, "k...@att.bizzzzzzzzzzzz"
><k...@att.bizzzzzzzzzzzz> wrote:
>> On Wed, 12 Jan 2011 17:59:32 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
>> >On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
>> >> Merciadri Luca wrote:
>>
>> >> > Consider the propagation time from H (high) to L (low): T PHL.
>> >> > Consider the propagation time from L to H: T PLH. Why are they
>> >> > generally different (in value)?
>
>
>> >Look at 100k ECL for a counterexample.
>>
>> Your forgetting the output emitter follower. It's hardly symmetrical.
>
>Hah! 100k ECL is differential. You kind of walked into that...
You got a link to a schematic?
whit3rd
<k...@att.bizzzzzzzzzzzz> wrote:
> On Thu, 13 Jan 2011 12:17:34 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >On Jan 12, 6:09 pm, "k...@att.bizzzzzzzzzzzz"
> ><k...@att.bizzzzzzzzzzzz> wrote:
> >> On Wed, 12 Jan 2011 17:59:32 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >> >On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
> >> >> Merciadri Luca wrote:
>
> >> >> > Consider the propagation time from H (high) to L (low): T PHL.
> >> >> > Consider the propagation time from L to H: T PLH. Why are they
> >> >> > generally different (in value)?
>
>
> >> Your forgetting the output emitter follower. It's hardly symmetrical.
>
>
> You got a link to a schematic?
Try this one...
<http://www.micrel.com/_PDF/HBW/sy10-100el05.pdf>
I think it was a family originally from Motorola, MC100xxx part
numbers.
The current suppliers include ON and Micrel.
DigiKey has these in stock...
k...@att.bizzzzzzzzzzzz
>On Jan 13, 3:43 pm, "k...@att.bizzzzzzzzzzzz"
><k...@att.bizzzzzzzzzzzz> wrote:
>> On Thu, 13 Jan 2011 12:17:34 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
>> >On Jan 12, 6:09 pm, "k...@att.bizzzzzzzzzzzz"
>> ><k...@att.bizzzzzzzzzzzz> wrote:
>> >> On Wed, 12 Jan 2011 17:59:32 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
>> >> >On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
>> >> >> Merciadri Luca wrote:
>>
>> >> >> > Consider the propagation time from H (high) to L (low): T PHL.
>> >> >> > Consider the propagation time from L to H: T PLH. Why are they
>> >> >> > generally different (in value)?
>>
>> >> >Look at100k ECLfor a counterexample.
>>
>> >> Your forgetting the output emitter follower. It's hardly symmetrical.
>>
>> >Hah! 100k ECLis differential. You kind of walked into that...
>>
>> You got a link to a schematic?
>
>Try this one...
><http://www.micrel.com/_PDF/HBW/sy10-100el05.pdf>
I don't see a schematic.
whit3rd
<k...@att.bizzzzzzzzzzzz> wrote:
> On Sun, 16 Jan 2011 11:51:18 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >On Jan 13, 3:43 pm, "k...@att.bizzzzzzzzzzzz"
> ><k...@att.bizzzzzzzzzzzz> wrote:
> >> On Thu, 13 Jan 2011 12:17:34 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >> >On Jan 12, 6:09 pm, "k...@att.bizzzzzzzzzzzz"
> >> ><k...@att.bizzzzzzzzzzzz> wrote:
> >> >> On Wed, 12 Jan 2011 17:59:32 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >> >> >On Jan 11, 3:11 pm, Rich Grise <ri...@example.net.invalid> wrote:
> >> >> >> Merciadri Luca wrote:
>
> >> >> >> > Consider the propagation time from H (high) to L (low): T PHL.
> >> >> >> > Consider the propagation time from L to H: T PLH. Why are they
> >> >> >> > generally different (in value)?
>
> >> >> >Look at100k ECLfor a counterexample.
>
> >> >> Your forgetting the output emitter follower. It's hardly symmetrical.
>
> >> >Hah! 100k ECLis differential. You kind of walked into that...
>
> >> You got a link to a schematic?
>
> >Try this one...
> ><http://www.micrel.com/_PDF/HBW/sy10-100el05.pdf>
>
> I don't see a schematic.
No, the data sheet lacks a schematic. It's a sign of the times.
All ECL inputs are basically differential, and the fully-differential
outputs
are just two standard ECL output circuits. So, the manufacturer's
data
doesn't show anything but the block diagram. The 'reference
generator'
that satisfied the second input to the ECL input pair of 10k ECL just
isn't provided
in the 100k series chips.
The data sheet DOES illustrate the point about rise and fall times
matching,
though; it explicitly specifies the "rise/fall" time as one value.
k...@att.bizzzzzzzzzzzz
I really need a schematic to see the big picture.
>The data sheet DOES illustrate the point about rise and fall times
>matching,
>though; it explicitly specifies the "rise/fall" time as one value.
Datasheets are known to lie.
whit3rd
<k...@att.bizzzzzzzzzzzz> wrote:
> On Mon, 17 Jan 2011 16:41:58 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
> >The data sheet DOES illustrate the point about rise and fall times
> >matching,
> >though; it explicitly specifies the "rise/fall" time as one value.
>
> Datasheets are known to lie.
NO, you need to stop asking for a schematic and THINK.
It's a differential logic scheme; high-to-low transition is done by
one output going down, the other going up. And low-to-high is
done by one output going down, the other going up. It's the same
operation either way, just swap the pin numbers next to the
description of the transition.
Don't get hung up jonesing to see a schematic; it's trivial to
get an ECL AND gate and make its inputs and outputs differential.
The magic is in the differential nature, not in the transistor
by transistor implementation detail.
k...@att.bizzzzzzzzzzzz
>On Jan 17, 8:24 pm, "k...@att.bizzzzzzzzzzzz"
><k...@att.bizzzzzzzzzzzz> wrote:
>> On Mon, 17 Jan 2011 16:41:58 -0800 (PST), whit3rd <whit...@gmail.com> wrote:
>
>> >The data sheet DOES illustrate the point about rise and fall times
>> >matching,
>> >though; it explicitly specifies the "rise/fall" time as one value.
>>
>> Datasheets are known to lie.
>
>NO, you need to stop asking for a schematic and THINK.
Don't be ridiculous.
>It's a differential logic scheme; high-to-low transition is done by
>one output going down, the other going up. And low-to-high is
>done by one output going down, the other going up. It's the same
>operation either way, just swap the pin numbers next to the
>description of the transition.
I want to *SEE* the differential output topology, dummy! <sheesh!>
>Don't get hung up jonesing to see a schematic; it's trivial to
>get an ECL AND gate and make its inputs and outputs differential.
>The magic is in the differential nature, not in the transistor
>by transistor implementation detail.
Don't be so stupid.
Rich Grise
> On Tue, 18 Jan 2011 12:50:21 -0800 (PST), whit3rd <whi...@gmail.com>
>
Something like this?
http://upload.wikimedia.org/wikipedia/commons/5/5f/ECL_structure_1000.jpg
Cheers!
Rich
k...@att.bizzzzzzzzzzzz
wrote:
Nah, that's the classical (MECL-2, MST-1, or before) current-switch
emitter-follower topology. I want to see the symmetrical output stage Whit is
talking about.