HV creepage requirements on internal layers of PCB

[sea moss]

For my day job I'm attempting to design a planar transformer for an LLC converter, which pushes up to 50W. The tricky part is that some of the secondary windings require 3.5kV of isolation between them.

This will go on a board which will be potted, and we use 100V/mil clearance and 20V/mil creepage as our design rules for everything once it's been potted.

However, I'm trying to figure out what spacing guideline I should use between traces on the same internal layer of the planar PCB. Specifically, the spacing between a through-hole via and a trace which need 3.5kV of separation.

Then google told me this:

1. For FR4 you can assume 1000V/mil between separate layers, and 300V/mil if you want to derate heavily.

2. IPC-2221: 300mil separation for 3.5kV in internal layers (around 12V/mil)

So why so low as 12V/mil, when the prepreg between the traces is also FR4? I figured it must be the creepage along the boundary of the prepreg. How pure is the insulator along the prepreg/core boundary??

Then google told me this:

1. Industry standard is 1% voids (air pockets) by volume, for any prepreg material.
2. The boundary between prepreg and core is hermetic, unless delamination occurs. Delamination can be caused by humidity or by overheating during soldering.

Assuming I can ensure the unit is potted without exposure to excessive humidity, and since the only thing soldered to this PCB are the pins, can I forget about the 12V/mil spacing? I would be happy to use 100V/mil.

I appreciate any wisdom you all might have on this topic.

P.S. The backup plan is to use a toroid wound with HV insulated wire, but I am looking to reduce the number of manufacturing steps and take advantage of the repeatable circuit values of a planar.

[gnuarm.del...@gmail.com]

What were the actual references for this info. Saying Google doesn't make that clear. I see where you cite IPC-2221, but what about the other info?

Rick C.

[sea moss]

I was worried someone was going to ask that. I didn't save any of these references, let me see if I can find them again...

[gnuarm.del...@gmail.com]

On Saturday, May 26, 2018 at 1:10:52 PM UTC-4, sea moss wrote:
> I was worried someone was going to ask that. I didn't save any of these references, let me see if I can find them again...

Don't sweat it. I'm just wondering how it could be as low as 12V/mil. I was thinking maybe it is much higher like 12kV/mil although that seems rather high. I thought there might be a typo on the web page.

Rick C.

[Tim Williams]

Circuit board and potting both count as a "cemented joint" in IEC/UL
60950-1. YMMV for other standards, but I imagine most are similar.

IPC-2221 is deprecated; follow a current standard.

Obviously enough -- find which standards /are/ actually applicable to your
product! Consult a compliance/test lab if you need help finding these
(their expertise is well worth it).

There is no such thing as creepage under potting, as long as it is free of
voids. You only need to use the direct, through-material dielectric
breakdown figure. (Handy!)

Do take lengths to ensure good potting. Make sure the correct mixing and
pouring methods are used. Use vacuum. Do not use a rigid compound, which
can crack components off the board; rubbery formulations are best. Where
high voltages reach components, ensure underfill by adding a hole or slot
beneath the component.

It sounds like this will probably not apply anywhere in your circuit, except
if you're using SMTs for Y-caps, and except for the planar transformer core,
which would be difficult to ensure good underfill on. In that case, make
sure the core doesn't see voltage, by putting the same circuit on the outer
layers of the stackup, or using two extra layers so the outer layers can be
bare, or shield layers.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: https://www.seventransistorlabs.com/

"sea moss" <danlu...@gmail.com> wrote in message
news:e6deef96-d113-46e7...@googlegroups.com...

[sea moss]

Here's a copy of IPC-2221 online:
http://us.jetpcb.com/Cht/Document/ipc-2221all.pdf

on page 39 there's a formula for HV spacing on internal layers.
for 3.5kV, the formula gives 305mil, which comes out to 11.5V/mil

[sea moss]

Thanks for the input Tim. Glad to hear that IPC-2221 is outdated. I'll ask around about which compliance labs we use.

We do our potting in-house, and it is a rubbery material. I have been asking questions about our process but haven't seen it with my own eyes yet. We do use vacuum.

I have kept in mind the separation between the planar windings and the core as you mentioned. I am planning to have the top and bottom of the PCB be bare material. However the problem of spacing on internal layers applies equally to where the edge of the board can touch the core. Whatever rule I end up with for the internal spacing will apply to this region as well.

[DecadentLinux...@decadence.org]

sea moss <danlu...@gmail.com> wrote in

news:e6deef96-d113-46e7...@googlegroups.com:

I would not attempt a multi-layer PCB with that level of isolation
requisite. Your design should place a single "winding" on a single PCB.
And other windings on their own PCB, then place a 5 mil sheet of
"Nomex" brand transformer paper between them It is around 1 or 2 kV per
mil.

https://tinyurl.com/y7boqf4c

This is the right stuff. You can order rolls or sheets, etc, and then
you can die cut them or have them die cut in the shapes you need.

This method also makes the entire "transformer" a serviceable device
too, and one does not sacrifice an entire PCB assembly for one blown
xformer winding.

Just an idea.

[DecadentLinux...@decadence.org]

"Tim Williams" <tiw...@seventransistorlabs.com> wrote in
news:pec57a$q5j$1...@dont-email.me:

> There is no such thing as creepage under potting, as long as it is
> free of voids.

Bullshitzski. :-)

Potting detatchment opens the assembly up for failure. And a creeping
conduction path is nearly always the failure mode. If not an instantaneous
arc failure.

If NOT detached, you are correct.

However, many potting compounds have poor surface to surface adhesion and
particualrly against shear force. Most require the assembly be "primed"
with a media that binds to the assembly surfaces better than the potting,
and then to the potting better than the potting would attach to those same
surfaces bare.

I found another nomex...

https://tinyurl.com/yalshx9e

[sea moss]

> I would not attempt a multi-layer PCB with that level of isolation
> requisite. Your design should place a single "winding" on a single PCB.
> And other windings on their own PCB, then place a 5 mil sheet of
> "Nomex" brand transformer paper between them It is around 1 or 2 kV per
> mil.
>
> https://tinyurl.com/y7boqf4c
>
> This is the right stuff. You can order rolls or sheets, etc, and then
> you can die cut them or have them die cut in the shapes you need.
>
> This method also makes the entire "transformer" a serviceable device
> too, and one does not sacrifice an entire PCB assembly for one blown
> xformer winding.
>
> Just an idea.

Good idea, I will definitely consider it. Won't you run into the same original spacing issue at the pins though? For proper alignment of the stack of PCBs the pins for each PCB should go through the whole stack. So then we have to mind the separation from one winding to the pins of the other windings. Unless there's another way to stack the PCBs that I haven't imagined.

[DecadentLinux...@decadence.org]

sea moss <danlu...@gmail.com> wrote in

news:83101844-7ad4-4059...@googlegroups.com:

You can have open holes in the winding layers that require a pass thru,
and the place silicone (teflon actually) tubing over the pins. Then you
could use transformer wire leads (instead of pins) to go to better
spaced holes on the main assembly or wire direct to the HV destination.
Then, the LV primary could be the place where the LV and stationing
holes/pins go. The secondary and feedback pcbs (if applicable) could be
where the double strength (or even kevlar) coated xformer wire would get
used. Or even Teflon sheathed "HV wire" with SPC inside.

[Jasen Betts]

On 2018-05-26, DecadentLinux...@decadence.org <DecadentLinux...@decadence.org> wrote:
> sea moss <danlu...@gmail.com> wrote in
> news:e6deef96-d113-46e7...@googlegroups.com:
>

> I would not attempt a multi-layer PCB with that level of isolation
> requisite. Your design should place a single "winding" on a single PCB.
> And other windings on their own PCB, then place a 5 mil sheet of
> "Nomex" brand transformer paper between them It is around 1 or 2 kV per
> mil.
>
> https://tinyurl.com/y7boqf4c
>
> This is the right stuff. You can order rolls or sheets, etc, and then
> you can die cut them or have them die cut in the shapes you need.

kapton seems stronger.

--
ت

[sea moss]

> You can have open holes in the winding layers that require a pass thru,
> and the place silicone (teflon actually) tubing over the pins. Then you
> could use transformer wire leads (instead of pins) to go to better
> spaced holes on the main assembly or wire direct to the HV destination.
> Then, the LV primary could be the place where the LV and stationing
> holes/pins go. The secondary and feedback pcbs (if applicable) could be
> where the double strength (or even kevlar) coated xformer wire would get
> used. Or even Teflon sheathed "HV wire" with SPC inside.

Yeah something like that would work. Keep in mind that the LV pins would need just as much isolation from the HV windings too, so all pins would have to be insulated. But this is adding a couple more manufacturing steps which I was trying to avoid... I guess I could draw this all up and have a magnetics house build it for us. A better case would be to use something like 100V/mil on internal trace/pin/core spacing, because the prepreg won't delaminate...

[John Larkin]

There are some numbers in here:

https://www.dropbox.com/s/cwxbwah9pfi7wc3/High-Voltage-PCDesign.pdf?dl=0

They mention 800 v/mil internal to FR4, but that sounds ambitious.

The do talk about planar transformers.




--

John Larkin Highland Technology, Inc trk

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[sea moss]

>
> There are some numbers in here:
>
> https://www.dropbox.com/s/cwxbwah9pfi7wc3/High-Voltage-PCDesign.pdf?dl=0
>
> They mention 800 v/mil internal to FR4, but that sounds ambitious.
>
> The do talk about planar transformers.
>

Good to have another reference, thank you. The section on planar transformers basically says that you can forget about using FR4 for simultaneous high current and high isolation, and go to high voltage polyimide film instead. I don't need high current but that construction might be useful anyway.

[Klaus Kragelund]

Just for insight, is it integrated magnetically? Because that is hard on a planar, you need to do asymmetric leg windings

About the isolation of FR4, our Q guy told me a couple of years ago the for SELV you need 0.4 mm prepeg in z direction

X direction if pottet you can look up in the UL standard tables.

Cheers

Klaus

[sea moss]

On Sunday, May 27, 2018 at 3:13:03 PM UTC-7, Klaus Kragelund wrote:
> Just for insight, is it integrated magnetically? Because that is hard on a planar, you need to do asymmetric leg windings

By integrated you mean having more than one lumped magnetic element on the same core? Like transformer and output chokes integrated? In that case, no, this is a transformer with multiple secondary windings, some of which need 3.5kV isolation between them.

> About the isolation of FR4, our Q guy told me a couple of years ago the for SELV you need 0.4 mm prepeg in z direction

> X direction if pottet you can look up in the UL standard tables.

I'm concerned with the x direction between internal traces on the same layer; so potting doesn't apply. (Except that maybe I can hand-wave and say that the potting will help prevent the PCB from any future delamination)

[John Larkin]

Coilcraft makes some nice planar transformers. The power density is
insane.

https://www.coilcraft.com/prod_planar.cfm

[sea moss]

>
> Coilcraft makes some nice planar transformers. The power density is
> insane.
>
> https://www.coilcraft.com/prod_planar.cfm
>

Yeah I've got one of those on my desk at work, I dig the look of that "bus bar + kapton" or whatever it is, maybe that's the HV polyimide film mentioned in the other reference you posted.

[Klaus Kragelund]

On Monday, May 28, 2018 at 1:55:10 AM UTC+2, sea moss wrote:
> On Sunday, May 27, 2018 at 3:13:03 PM UTC-7, Klaus Kragelund wrote:
> > Just for insight, is it integrated magnetically? Because that is hard on a planar, you need to do asymmetric leg windings
>
> By integrated you mean having more than one lumped magnetic element on the same core? Like transformer and output chokes integrated? In that case, no, this is a transformer with multiple secondary windings, some of which need 3.5kV isolation between them.
>

Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction

[John Larkin]

I have one too; very nice looking. Seems to be thin kapton layers.
That construcrion can get HV clearances from cheap air instead of
expensive kapton. And one could blow air between the layers (put the
tranny near a fan) to increase power handling.

I was considering a Pockels Cell driver that used PCB-trace
transformers for the stacked-fet gate drivers, 7KV sort of isolation.
But the customer went away.

[John Larkin]

On Mon, 28 May 2018 00:04:26 -0700 (PDT), Klaus Kragelund
<klau...@hotmail.com> wrote:

>On Monday, May 28, 2018 at 1:55:10 AM UTC+2, sea moss wrote:
>> On Sunday, May 27, 2018 at 3:13:03 PM UTC-7, Klaus Kragelund wrote:
>> > Just for insight, is it integrated magnetically? Because that is hard on a planar, you need to do asymmetric leg windings
>>
>> By integrated you mean having more than one lumped magnetic element on the same core? Like transformer and output chokes integrated? In that case, no, this is a transformer with multiple secondary windings, some of which need 3.5kV isolation between them.
>>
>Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction

Seems like you could just offset the traces between windings, or add
little loops off to the side, away from the core, to get leakage
inductance.

[sea moss]

> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>

Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)

Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.

Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.

[Deepak Bikkina]

Hi Sea Moss,

I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?

Thankyou in advance!

[sea moss]

Hi Deepak,

For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.

[Deepak Bikkina]

Thankyou for your immediate response. This information really helps me with my project!

Regards
Deepak B

[John Walliker]

If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
will give you a lot of useful information about pcb requirements.

John

[John Larkin]

On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
<jrwal...@gmail.com> wrote:

>On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:

I've seen UL and CE limits for surface clearances but not seen
anything for pcb internal clearances, nearby traces or between layers.
Do you know of any specs for these?

Of course, you have to pay big to purchase the IEC standards, and
every one references a bunch of other ones.

[Phil Hobbs]

You can sometimes find late drafts of the standards online.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[Joe Gwinn]

Yes. Also, many IEC standards are largely copped from other non-IEC
standards, and can be found with a little work. It may be that each
chapter in the donor standard becomes an individual IEC standard.

Joe Gwinn

[John Walliker]

Most of JL's products probably count as test and measurement equipment
which is subject to IEC61010-1. This standard has tables of internal clearances
and thicknesses required for various voltages, environments and frequencies.

John

[Joe Gwinn]

On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker

Yes, but where did these clearances et al come from? I've been
involved in such standards, and the corresponding IEC standard is very
close to the contributing standard, and the donor is often enough.
And, one can get the donor standard, but the IEC standards are often
prohibitively expensive, and change too fast to follow.

Joe Gwinn

[John Larkin]

On Wed, 22 Mar 2023 17:52:16 -0400, Joe Gwinn <joeg...@comcast.net>

That spec is $850, but there are drafts online.

[Joe Gwinn]

It that IEC spec complete, or do you need a swarm of them to have the
entire story?

Joe Gwinn

[John Walliker]

The IEC61010-1 document is 157 pages long and is reasonably complete. None
of the standards are completely standalone, but this one is not too bad.
The 62368.1 2018 standard for information technology and audio-visual equipment
is 338 pages long and also contains most of what is needed to design a compliant
product. These standards are just for safety. EMC compliance requires a different
set of standards. One good thing is that there has been a lot of effort to harmonise
standards in recent years so that a single design has a good chance of being
compliant worldwide. Unfortunately, the FCC does like to do things slightly differently
to everyone else which complicates compliance testing.
John

[Joe Gwinn]

On Thu, 23 Mar 2023 01:53:20 -0700 (PDT), John Walliker

I worked at the FCC in the mid 1970s. As befits a US Federal
regulatory agency, it is lawyer dominated, with a very loose grip on
engineering. I learned more law than they learned engineering.

Joe Gwinn