"Kevin Aylward" wrote in message
news:mZ-dnWN2AsZz11vF...@giganews.com...
>"Cursitor Doom" wrote in message news:oa4gd2$h3o$1...@dont-email.me...
>On Sun, 12 Mar 2017 14:16:22 -0700, John Larkin wrote:
>> I don't design ICs, I buy them. I design and sell boards. LT Spice is a
>> great tool for helping me do that.
>>Kev is obviously heavily biased against LT because he views it as a free
>>and unwelcome alternative to his SS, so his denigratory remarks have to
>>be seen in that light.
>Simply not true.
I will expand on that, in part this will give a bit of general knowledge as
to what "pro ic design is all about" that readers here may find useful.
Key parameters in producing a commercial IC product are.
1 It takes several months to get a design back from the fab after tapeout.
2 ICs, typically today, are complicated, 10,000s of transistors for an
analog ASIC
3 A 0.18u process might take $100k in prototype fab costs
4 Fab process have extensive variations
5 Millions sold per month must work, reliably, for many years.
So, prior to tapeout, an ic designs are required to have extensive design
effort and verification.
The process of designing, say a BiCMOS chip, involves going through a range
of design optimisations and simulations. This consists of designing for DC,
AC TRAN, NOISE, in an iterative manner.
The details of the design involve selecting, for example, gate lengths and
widths, and how many in parallel and series, and emitter areas. For example,
shorter gate lengths get you faster speed. Maximising headroom may be
achieved by reducing the Vdsat of the transistor, by reducing its overdrive
voltage, Vgst (Vgs-Vth), this means say, increasing the ratio of W/L.
However, reducing Vgst, makes matching worse, so compromises have to be
made. Better matching means larger W x L, however, this means a slower
circuit, which could mean instability in a feedback loop. etc...etc... all
to satisfy specifications of power consumption, noise, die size,
etc...etc...
Now, all of this has to be done with process variations, say Vt varying by
200mv, gm of mosfet varing 20%, and over temperatures, say -40 deg to 85deg,
over all supply voltages. Typically models are made that reflect the
extremes of the process, which I explain in more detail here:
http://www.anasoft.co.uk/worstcase.htm
Typically, 100,000s of simulations are run to verify a chip before tapeout.
So, no, I do not have "bias". My view is based on the facts.
If a simulator does not directly support worst case analyses, its dead in
the water as far as IC design in concerned. Period.
Second, is usability of accessing key data that supports the above design
issues. IC design requires spending hours per day, every day, running
continually modified simulations. Pissing about for a minute to access each
plot *is* a major problem, for serious, professional designers.
For example, in checking that Vds (drain voltage) is greater than Vdsat
(when device crushes) over *all* process corners, and over the operating DC
ranges, one needs to be able to do this *easily*.
http://www.anasoft.co.uk/screenshots.htm
Scroll down to the second screen shot.
This shows a signal list tab to the left where you can ctrl-click and easily
display a combination of any signal. For example, plotting Vgs and Vdsat.
SuperSpice lists in that signal list all major device parameters such as
Vgst, gm, gds, etc... You don't have to hunt about to get the data that you
really need to plot.
Even small details can have a *major* effect on usability when your
simulating 40 hours per week. For example, SS displays the actual x, y trace
data of the graph without cursors, because the mouse cursor *locks* onto the
trace, and only displays only the *valid* y with x data. LTSpice just
displays apparent x,y data of whether the mouse is on the screen, which has
nothing to do with the real trace data. Using LT manual cursers is a major
pain.
So, sure, if your not an IC design pro, the LT GUI, may well be adequate for
your needs.