Pinging 74HC4046 Users

[Jim Thompson]

Finally zeroing in on modeling the 74HC4046 after finding a
unpublished AppNote that gave more details on the innards. This is
what a fixed frequency looks like, simulation-wise...

http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf

Comments? Scalings? (This is based on AppNote and Datasheets
claiming trip at VDD/2).

First release will be VCO only and will be in LTspice format. Once
you approve that, the PFD is virtually all logic.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[Nico Coesel]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com>
wrote:

>Finally zeroing in on modeling the 74HC4046 after finding a
>unpublished AppNote that gave more details on the innards. This is
>what a fixed frequency looks like, simulation-wise...
>
>http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
>Comments? Scalings? (This is based on AppNote and Datasheets
>claiming trip at VDD/2).
>
>First release will be VCO only and will be in LTspice format. Once
>you approve that, the PFD is virtually all logic.

Funny. I put a HC7046 into a design recently. Unfortunately there are
no design tools for calculating the loop filter components. So how
about modeling the HC7046? It is much more interesting because of the
lock detect output which can be used as a reset.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

[Phil Hobbs]

On 10/15/2012 9:16 PM, Nico Coesel wrote:
> Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com>
> wrote:
>
>> Finally zeroing in on modeling the 74HC4046 after finding a
>> unpublished AppNote that gave more details on the innards. This is
>> what a fixed frequency looks like, simulation-wise...
>>
>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>>
>> Comments? Scalings? (This is based on AppNote and Datasheets
>> claiming trip at VDD/2).
>>
>> First release will be VCO only and will be in LTspice format. Once
>> you approve that, the PFD is virtually all logic.
>
> Funny. I put a HC7046 into a design recently. Unfortunately there are
> no design tools for calculating the loop filter components. So how
> about modeling the HC7046? It is much more interesting because of the
> lock detect output which can be used as a reset.
>

I investigated all the HC versions (HC4046 from several vendors, HC7046,
HC9046) about a year back, iirc, and their oscillators are all junk
compared with the ancient metal-gate 4046. They're horribly nonlinear,
all in different ways, which makes it really hard to build a good PLL.
What's worse, their oscillators quit when their control voltages are
within a volt or so of ground (the actual threshold for misbehaviour
varies from device to device).

The 7046 is enough more expensive that I'd be much happier spending the
dough on a better oscillator, and using the back end of a normal HC4046
from a good vendor.


Cheers

Phil Hobs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net

[Jim Thompson]

On Tue, 16 Oct 2012 01:16:34 GMT, ni...@puntnl.niks (Nico Coesel)
wrote:

>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com>
>wrote:
>
>>Finally zeroing in on modeling the 74HC4046 after finding a
>>unpublished AppNote that gave more details on the innards. This is
>>what a fixed frequency looks like, simulation-wise...
>>
>>http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>>
>>Comments? Scalings? (This is based on AppNote and Datasheets
>>claiming trip at VDD/2).
>>
>>First release will be VCO only and will be in LTspice format. Once
>>you approve that, the PFD is virtually all logic.
>
>Funny. I put a HC7046 into a design recently. Unfortunately there are
>no design tools for calculating the loop filter components. So how
>about modeling the HC7046? It is much more interesting because of the
>lock detect output which can be used as a reset.

Funny. I have a HC7046 schematic right here in front of me.

Personally I think lock detectors are a farce. But I can certainly
add it in.

As for "design tools for calculating the loop filter components", come
on Nico, that's math, you don't need a "tool" :-)

See...

http://www.analog-innovations.com/SED/PhaseLockedLoopAnalysis.pdf

for a primer. Adjust analysis for edge-detecting PFD "gain".

[Jim Thompson]

Phil, What sort of non-linearity are you seeing? All I can think of
is perhaps using non-cascoded current mirrors, or just using a gross
un-boosted follower. Is it just a bow in the control curve, or are
you seeing bow in the capacitor charging voltage?

[Jim Thompson]

On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

It occurs to me that the variable current input quits at about 1*VTH.
So you were trying to get to zero frequency ?:-)

Add some offset current and it won't quit oscillating.

[Jim Thompson]

Further recollections... I've used OpAmps to force the control
linearity. Been a long time, maybe 30 years since I had a VCM need.

You could, of course, resurrect one of my MC4024's from the mid '60's
:-)

[George Herold]

On Oct 15, 7:59 pm, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-

Web-Site.com> wrote:
> Finally zeroing in on modeling the 74HC4046 after finding a
> unpublished AppNote that gave more details on the innards.  This is
> what a fixed frequency looks like, simulation-wise...
>
> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
> Comments?  Scalings?  (This is based on AppNote and Datasheets
> claiming trip at VDD/2).
>
> First release will be VCO only and will be in LTspice format.  Once
> you approve that, the PFD is virtually all logic.
>
>                                         ...Jim Thompson
> --
> | James E.Thompson, CTO                            |    mens     |
> | Analog Innovations, Inc.                         |     et      |
> | Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
> | Phoenix, Arizona  85048    Skype: Contacts Only  |             |
> | Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |

> | E-mail Icon athttp://www.analog-innovations.com|    1962     |

>
> I love to cook with wine.     Sometimes I even put it in the food.

test reply,

(Google won't let me post??)

George

[George Herold]

On Oct 15, 7:59 pm, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
Web-Site.com> wrote:

> Finally zeroing in on modeling the 74HC4046 after finding a
> unpublished AppNote that gave more details on the innards.  This is
> what a fixed frequency looks like, simulation-wise...
>
> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
> Comments?  Scalings?  (This is based on AppNote and Datasheets
> claiming trip at VDD/2).
>
> First release will be VCO only and will be in LTspice format.  Once
> you approve that, the PFD is virtually all logic.
>
>                                         ...Jim Thompson
> --
> | James E.Thompson, CTO                            |    mens     |
> | Analog Innovations, Inc.                         |     et      |
> | Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
> | Phoenix, Arizona  85048    Skype: Contacts Only  |             |
> | Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |

> | E-mail Icon athttp://www.analog-innovations.com|    1962     |

>
> I love to cook with wine.     Sometimes I even put it in the food.

Hi Jim, Phil. Here’s a plot for a 74HC4046

http://bayimg.com/kAEhEaAec

And for different ‘charging’ resistors.

http://bayimg.com/kAehmaaEC

The lines were just drawn by eye.

As Phil says the oscillations stop if the control voltage falls below
~1Volt.
(I never used the metal can version so don’t know what I’m missing.)

George H.

(trying onece more then)

[Jim Thompson]

On Tue, 16 Oct 2012 06:11:46 -0700 (PDT), George Herold
<ghe...@teachspin.com> wrote:

>On Oct 15, 7:59 pm, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
>Web-Site.com> wrote:
>> Finally zeroing in on modeling the 74HC4046 after finding a
>> unpublished AppNote that gave more details on the innards.  This is
>> what a fixed frequency looks like, simulation-wise...
>>
>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>>
>> Comments?  Scalings?  (This is based on AppNote and Datasheets
>> claiming trip at VDD/2).
>>
>> First release will be VCO only and will be in LTspice format.  Once
>> you approve that, the PFD is virtually all logic.
>>
>>                                         ...Jim Thompson

[snip]

>
>Hi Jim, Phil. Here’s a plot for a 74HC4046
>
>http://bayimg.com/kAEhEaAec
>
>And for different ‘charging’ resistors.
>
>http://bayimg.com/kAehmaaEC
>
>The lines were just drawn by eye.

Thanks for the plots. Quite puzzling, I'd expect drooping at the high
end of the F vs V plot due to gate delays.

>
>As Phil says the oscillations stop if the control voltage falls below
>~1Volt.

I think Phil didn't use an "offset" resistor

>(I never used the metal can version so don’t know what I’m missing.)
>
>George H.
>
>(trying onece more then)

Both attempts posted :-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

On 10/15/2012 07:59 PM, Jim Thompson wrote:
> Finally zeroing in on modeling the 74HC4046 after finding a
> unpublished AppNote that gave more details on the innards. This is
> what a fixed frequency looks like, simulation-wise...
>
> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
> Comments? Scalings? (This is based on AppNote and Datasheets
> claiming trip at VDD/2).
>
> First release will be VCO only and will be in LTspice format. Once
> you approve that, the PFD is virtually all logic.
>
> ...Jim Thompson

Different manufacturers give you a wide variety of ridiculously
nonlinear tuning curves for the VCO--the tuning sensitivity varies like
3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5) depending on
the device.

Which did you pick? ;)

(The metal gate 4046-style oscillators all stink on ice--HC4046, HC7046,
HC9046, all makers, all horrible. PD2 is nice if you stay out of the
dead zone.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

[Phil Hobbs]

The metal gate version works over about 1000:1 range, and is very
respectably linear--a few percent IIRC, which is much better than good
enough for inside a PLL. It's really quite pretty in a small way.

The HC parts' nonlinearity is all over the map depending on the vendor,
and that messes up the loop dynamics really badly. Spicing the HC4046
oscillator will definitely be "a trap for young players", as Dave Jones
says.

With the loop gain varying 3:1 with control voltage, and the centre
frequency being a very poorly controlled function of the RC, you have
to make HC4046 loops ridiculously overdamped in the normal case to avoid
loop instability. If you're using lead-lag compensation, you have to
put the zero a factor of at least 5 below the nominal unity gain cross,
whereas with a well-behaved VCO, you can put it right at the unity gain
cross and have 45 degrees' phase margin.

I'd far rather use an OTA integrator/Schmitt trigger oscillator or
something like that, with the 4046 PDII.

The HC4046 has its uses, but not nearly as many as if it were really a
faster CD4046.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

[Tim Wescott]

On Tue, 16 Oct 2012 06:11:46 -0700, George Herold wrote:

> On Oct 15, 7:59 pm, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
> Web-Site.com> wrote:

<<< snip >>>

> (I never used the metal can version so don’t know what I’m missing.)

Phil said metal _gate_ version, i.e. a plain ol' 4046.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

[Tim Wescott]

Oh, I should know -- OTA Integrator?

I wish someone would take the 3-state phase detector from the 4046 and
put it into a 6-pin SOT and call it TinyLogic or whatever. It would save
ever so much board space.

[Jim Thompson]

On Tue, 16 Oct 2012 11:25:52 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>On 10/15/2012 07:59 PM, Jim Thompson wrote:
>> Finally zeroing in on modeling the 74HC4046 after finding a
>> unpublished AppNote that gave more details on the innards. This is
>> what a fixed frequency looks like, simulation-wise...
>>
>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>>
>> Comments? Scalings? (This is based on AppNote and Datasheets
>> claiming trip at VDD/2).
>>
>> First release will be VCO only and will be in LTspice format. Once
>> you approve that, the PFD is virtually all logic.
>>
>> ...Jim Thompson
>
>Different manufacturers give you a wide variety of ridiculously
>nonlinear tuning curves for the VCO--the tuning sensitivity varies like
>3:1,

I don't think most users fret over the incremental slope. The
"follower" variation is trivial to fix by adding an OpAmp. Sinking
one end of the capacitor into the substrate diode every half cycle is
something you have to live with if you like 4046's. I'm doing this
for fun (and requests from this group)... I wouldn't use one myself.
Get my MC4024 if you want better linearity. I think there's also a
PECL copy, but I don't remember the part number off the top of my
head. Or use a V-to-F chip.

>and the oscillator quits below about 0.7-1.1V (@VDD=5) depending on
>the device.

That's noted on the data sheet. Why does that give you such
heartburn? Do you really need zero frequency?

>
>Which did you pick? ;)

I have the most complete data on the TI 'HC4046, but I was aiming sort
of average ;-) since I'm building it from behavioral blocks.

I would guess that you're one of the few people in the world that
would need a flat-ass accurate fit to one particular version.

>
>(The metal gate 4046-style oscillators all stink on ice--HC4046, HC7046,
>HC9046, all makers, all horrible. PD2 is nice if you stay out of the
>dead zone.)
>
>Cheers
>
>Phil Hobbs

What do you really need? An accurate V-to-F?

[Jim Thompson]

W/O the charge pump, it's just a dual-D plus a quad 2-in-NAND.

[George Herold]

Ahh thanks Tim, the CD4046? I guess I should order some.

OTA = transconductance amplifier? (not sure what O is.)

George H.

[Tim Wescott]

That's a lot more board space than a SOT-23.

[Jim Thompson]

On Tue, 16 Oct 2012 11:37:30 -0500, Tim Wescott

If you can round up some customers who would pay for it, I'll design
and fab it.

Unfortunately today's average customer wants the whole world on that
one chip, NOT just a building block.

[Phil Hobbs]

Operational transconductance amplifier, e.g. an LM13700--basically a
bunch of current mirrors, controlled by a diff pair so that you can set
the tail current of the pair and the output is a current source equal to
delta I_C, which pulls almost to the rails. You hang a cap on the
output, buffer it with the built-in Darlington, and feed that into a
Schmitt trigger, which can be made from the other half of the LM13700 in
a pinch. The Schmitt switches the diff pair of the integrator stage, so
you get a reasonably decent triangle wave with a slope proportional to
the current you program the OTA integrator with. Works well at low
speed, over a wide range, and the component count is lowish.

>
> I wish someone would take the 3-state phase detector from the 4046 and
> put it into a 6-pin SOT and call it TinyLogic or whatever. It would save
> ever so much board space.

Agreed. But it would cost a bunch more, because the 4046 is the jellybean.

[Phil Hobbs]

The loop gain is proportional to K_VCO * K_phi, so if the tuning
sensitivity varies all over the map like that, so does the frequency
compensation of the loop. That's what makes the HC4046 and its brethren
so sucky.

[Jim Thompson]

On Tue, 16 Oct 2012 14:02:39 -0400, Phil Hobbs

I've not even played with one, except to measure some DC. The data
sheets would seem to indicate that the non-linearity occurs at the
tuning extremes. Just bound your control voltage if you're getting
lock-in issues <:-|

I don't know why the "designers" of the 4046 didn't do a better job of
copying the PECL core of my MC4024 (~1965). All current mode, no
diode clamping, etc.

[Nico Coesel]

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

>On 10/15/2012 07:59 PM, Jim Thompson wrote:
>> Finally zeroing in on modeling the 74HC4046 after finding a
>> unpublished AppNote that gave more details on the innards. This is
>> what a fixed frequency looks like, simulation-wise...
>>
>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>>
>> Comments? Scalings? (This is based on AppNote and Datasheets
>> claiming trip at VDD/2).
>>
>> First release will be VCO only and will be in LTspice format. Once
>> you approve that, the PFD is virtually all logic.
>>
>> ...Jim Thompson
>
>Different manufacturers give you a wide variety of ridiculously
>nonlinear tuning curves for the VCO--the tuning sensitivity varies like
>3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5) depending on
>the device.

Major deja-vu here :-) I used NXP's MS-DOS tool to cook up some values
but they where way off. Fortunately the circuit I tried the HC7046 in
is a one-off and not something that needs to go into production. I
have used PLLs before but never had so much trouble getting the
circuit going.

[Phil Hobbs]

Just what I need, another opportunity for a little turd-polishing. ;)

The HC4046 isn't impossible to use, it's just sucky for no good reason.
Since the frequency vs RC spec is so loose, keeping away from the
edges is hard even in a narrowband application. You just have to use
really tame loop compensation (which is fine for some things).

>
> I don't know why the "designers" of the 4046 didn't do a better job of
> copying the PECL core of my MC4024 (~1965). All current mode, no
> diode clamping, etc.

Or even the metal gate CD4046.

[tm]

"Phil Hobbs" <pcdhSpamM...@electrooptical.net> wrote in message
news:hpCdnao1ebP9XODN...@supernews.com...

You are supposed to pick up the turd by its clean end.

tm

[Phil Hobbs]

*satori*

[John Larkin]

On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescott
<t...@seemywebsite.please> wrote:

We build something like the charge-pump detector into FPGAs. We use an
external dual schottky diode for the pump-up and pump-down blips, to
avoid the deadband that tri-state charge pumps tend to create. We can
also delta-sigma those outputs to control our VXCO open-loop.

The little function generator chips make nice wide-range, low
frequency VCOs. Exar, Maxim?




--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

[Bill Sloman]

On Oct 17, 1:12 pm, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescott
>
>
>
> <t...@seemywebsite.please> wrote:
> >On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote:
>
> >> On 10/15/2012 09:40 PM, Jim Thompson wrote:
> >>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs

> >>> <pcdhSpamMeSensel...@electrooptical.net>  wrote:

>
> >>>> On 10/15/2012 9:16 PM, Nico Coesel wrote:

> >>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com>

And there used to be a fairly wide range of chips available that were
designed to be very linear VCOs, intended for use as voltage-to-
frequency A/D converters. Analog Devices still seems to be in the
business

http://www.analog.com/en/analog-to-digital-converters/voltage-to-frequency-converters/products/index.html

Phil Hobbs probably should be using the AD650 - though I can't
recommend it on the basis of personal expereience

--
Bill Sloman, Sydney

[Phil Hobbs]

Fifteen bucks for a 1-MHz V-F converter? Not me, especially not inside
a PLL where 1% linearity is way better than good enough.

I'd happily use a metal-gate 4046 at frequencies where they work--all
you need is a resistor to ground from the PD2 output to pull it off the
dead zone.

Above a megahertz or so, a current-programmed triangle wave oscillator
is good, or else a linearized LC VCO. You can get linearities of better
than 10% in varactor-tuned VCOs by putting in a couple of off-stage
resonances.

[Phil Hobbs]

Those aren't too bad looking, but check out the NXP HC7046 datasheet, p.
24 of http://tinyurl.com/c3xgcgq , or the TI one, P. 14 of
http://tinyurl.com/cghq2yb .

Even the much-ballyhooed HC9046 has the same sorts of worries, see P.24
of http://tinyurl.com/chlkgwv . Many of the typical curves are probably
acceptably linear for most PLL uses, but I for one do not get a warm
fuzzy feeling about the unit-to-unit repeatability, based on those curves.

And check out the actual HC4046--first in a Chinese knockoff,
http://tinyurl.com/buvdkby P. 490,
then the TI version, P. 14 of http://tinyurl.com/ckz4ezv ,
and then in the ON semi versions, P. 11 of http://tinyurl.com/cyymxsl .

Compare that with the HEF4046 (NXP metal gate version)--check out the
VCO linearity error plot on P. 15 of http://tinyurl.com/cl3c7vv . The
TI CD4046B claims 0.7% linearity from 2.5V to 7.5V with a 10V supply,
http://tinyurl.com/cpd3skg .

The HC versions are all over the map.

[Jim Thompson]

Turns out that the principal difference between old CD4046 and new
74HC versions is that the current mirrors in the new versions have
GAIN: 6x-8x depending on voltage, i.e. channel-length modulation.

Apparently their mis-directed aim was higher operating frequency. The
result is extraordinarily bad linearity :-(

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

That's very interesting. So they didn't just use bigger FETs for the
output devices of the mirrors? How did they do it?

Cheers

Phil "Bipolar" Hobbs

[Jim Thompson]

On Wed, 17 Oct 2012 15:33:40 -0400, Phil Hobbs

Most likely bigger FET's... but I'm guessing they used raw device-size
scaling, no cascoding (which minimizes channel-length modulation).

I don't have any device library information :-(

The sad part of all this is how easy it would be to design a much
better VCM... not a difficult task at all.

Phil, What is your application? If you need linearity, why not just
roll your own, given the high-speed comparators that are now available
off-the-shelf.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

I'm not using any PLLs at the moment--you asked about the modelling
problem, and the badness of the HC4046 oscillator is one of my pet
peeves from many years back. Sort of like you and Democrats. ;)

I've often done as you suggest--in fact over the years my main use of
HC4046es has been as acquisition aids for my real phase detectors, which
are generally diode bridges because their noise is so low. Mini
Circuits MPD-1s are good medicine.

Just now I'm fighting bit rot in an electromagnetic simulator that
worked fine up till yesterday, and debugging a little board full of
pHEMTs and 0402s.

Cheers

Phil Hobbs

[Jim Thompson]

On Tue, 16 Oct 2012 16:19:44 -0400, Phil Hobbs

Try this...

http://www.analog-innovations.com/SED/Oscillator_AnotherArchitecture.pdf

Note the frequency, ~46MHz, and the current consumption ;-)

It is immaculately linear in frequency versus control current.

Now I'm yanking your chain just a wee bit, this is on a 0.18um
process, but I'll try it on a 5V process and see how it behaves.

But would anyone buy it?

[Jim Thompson]

On Wed, 17 Oct 2012 17:51:09 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>On 10/17/2012 03:57 PM, Jim Thompson wrote:

[snip]

>>
>> Phil, What is your application? If you need linearity, why not just
>> roll your own, given the high-speed comparators that are now available
>> off-the-shelf.
>>
>> ...Jim Thompson
>
>I'm not using any PLLs at the moment--you asked about the modelling
>problem, and the badness of the HC4046 oscillator is one of my pet
>peeves from many years back. Sort of like you and Democrats. ;)
>
>I've often done as you suggest--in fact over the years my main use of
>HC4046es has been as acquisition aids for my real phase detectors, which
>are generally diode bridges because their noise is so low. Mini
>Circuits MPD-1s are good medicine.
>
>Just now I'm fighting bit rot in an electromagnetic simulator that
>worked fine up till yesterday, and debugging a little board full of
>pHEMTs and 0402s.
>
>Cheers
>
>Phil Hobbs

Is it bit rot or root rot ?:-)

Don't you love "worked fine up till yesterday" situations?

One of my worst pranks was on a young engineer (EE, at
OmniComp/GenRad)... he's fretting over a breadboard that "was working
yesterday". He goes to lunch and I sit down at the bench with my
OptiVisors...

http://www.analog-innovations.com/SED/OptiVisorMonster.jpg

and spot a solder bridge. I solder suck it up, and the breadboard
works.

When young engineer returns from lunch he's bewildered and pacing
around, then testing, then pacing, then testing...

To this day I've never told him... and it's been 27 years ;-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

As long as it was less than a buck or thereabouts, probably so. Of
course the much-maligned Younger Generation might not understand. ;)

Cheers

Phil Hobbs

[Phil Hobbs]

Jim Thompson wrote:
>
> On Wed, 17 Oct 2012 17:51:09 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> >On 10/17/2012 03:57 PM, Jim Thompson wrote:
> [snip]
> >>
> >> Phil, What is your application? If you need linearity, why not just
> >> roll your own, given the high-speed comparators that are now available
> >> off-the-shelf.
> >>
> >> ...Jim Thompson
> >
> >I'm not using any PLLs at the moment--you asked about the modelling
> >problem, and the badness of the HC4046 oscillator is one of my pet
> >peeves from many years back. Sort of like you and Democrats. ;)
> >
> >I've often done as you suggest--in fact over the years my main use of
> >HC4046es has been as acquisition aids for my real phase detectors, which
> >are generally diode bridges because their noise is so low. Mini
> >Circuits MPD-1s are good medicine.
> >
> >Just now I'm fighting bit rot in an electromagnetic simulator that
> >worked fine up till yesterday, and debugging a little board full of
> >pHEMTs and 0402s.
> >
> >Cheers
> >
> >Phil Hobbs
>
> Is it bit rot or root rot ?:-)
>
> Don't you love "worked fine up till yesterday" situations?

Not really. This one's a genuine mystery at the moment--same
executable, same input files, last week it ran fine, today it produces
hundreds of megabytes of NaN's. Like I said, it's obviously bit rot.

>
> One of my worst pranks was on a young engineer (EE, at
> OmniComp/GenRad)... he's fretting over a breadboard that "was working
> yesterday". He goes to lunch and I sit down at the bench with my
> OptiVisors...
>
> http://www.analog-innovations.com/SED/OptiVisorMonster.jpg
>
> and spot a solder bridge. I solder suck it up, and the breadboard
> works.
>
> When young engineer returns from lunch he's bewildered and pacing
> around, then testing, then pacing, then testing...

I'd be very happy if my case of bit rot spontaneously fixed itself like
that. I did find that the 0402-ish board had a major goof--somebody
stuffed NPNs where PNPs should have been.

I wonder if there is a useful class of circuits where you could replace
PNPs with NPNs without reversing the power supplies, and have it still
work.

>
> To this day I've never told him... and it's been 27 years ;-)

He's probably forgotten all about it.

Cheers

Phil Hobbs

[Bill Sloman]

On Oct 18, 2:56 am, Phil Hobbs

<pcdhSpamMeSensel...@electrooptical.net> wrote:
> On 10/16/2012 11:33 PM, Bill Sloman wrote:
> > On Oct 17, 1:12 pm, John Larkin
> > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescot

> >> <t...@seemywebsite.please> wrote:
> >>> On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote:
> >>>> On 10/15/2012 09:40 PM, Jim Thompson wrote:
> >>>>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs
> >>>>> <pcdhSpamMeSensel...@electrooptical.net> wrote:
> >>>>>> On 10/15/2012 9:16 PM, Nico Coesel wrote:
> >>>>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com>
> >>>>>>> wrote:

<snip>

> >>>>> It occurs to me that the variable current input quits at about 1*VTH.
> >>>>> So you were trying to get to zero frequency ?:-)
>
> >>>>> Add some offset current and it won't quit oscillating.
>

> >>>> The metal gate version works over about 1000:1 range, and is very
> >>>> respectably linear--a few percent IIRC, which is much better than good
> >>>> enough for inside a PLL. It's really quite pretty in a small way.
>
> >>>> The HC parts' nonlinearity is all over the map depending on the vendor,
> >>>> and that messes up the loop dynamics really badly. Spicing the HC4046
> >>>> oscillator will definitely be "a trap for young players", as Dave Jones
> >>>> says.
>
> >>>> With the loop gain varying 3:1 with control voltage, and the centre
> >>>> frequency being a very poorly controlled function of the RC, you have
> >>>> to make HC4046 loops ridiculously overdamped in the normal case to avoid
> >>>> loop instability. If you're using lead-lag compensation, you have to
> >>>> put the zero a factor of at least 5 below the nominal unity gain cross,
> >>>> whereas with a well-behaved VCO, you can put it right at the unity gain
> >>>> cross and have 45 degrees' phase margin.
>
> >>>> I'd far rather use an OTA integrator/Schmitt trigger oscillator or
> >>>> something like that, with the 4046 PDII.
>
> >>>> The HC4046 has its uses, but not nearly as many as if it were really a
> >>>> faster CD4046.
>

> >>> Oh, I should know -- OTA Integrator?
>
> >>> I wish someone would take the 3-state phase detector from the 4046 and
> >>> put it into a 6-pin SOT and call it TinyLogic or whatever. It would save
> >>> ever so much board space.
>
> >> We build something like the charge-pump detector into FPGAs. We use an
> >> external dual schottky diode for the pump-up and pump-down blips, to
> >> avoid the deadband that tri-state charge pumps tend to create. We can
> >> also delta-sigma those outputs to control our VXCO open-loop.
>
> >> The little function generator chips make nice wide-range, low
> >> frequency VCOs. Exar, Maxim?
>
> > And there used to be a fairly wide range of chips available that were
> > designed to be very linear VCOs, intended for use as voltage-to-
> > frequency A/D converters. Analog Devices still seems to be in the
> > business
>

> >http://www.analog.com/en/analog-to-digital-converters/voltage-to-freq...

>
> > Phil Hobbs probably should be using the AD650 - though I can't
> > recommend it on the basis of personal expereience
>
> Fifteen bucks for a 1-MHz V-F converter? Not me, especially not inside
> a PLL where 1% linearity is way better than good enough.

The point was that these are legacy parts, and correspondingly
expensive. The LM331 which offers even better linearity, but only goes
to 100kHz, turns out to be still available to, but at $6 each in small
quantities. I was rather hoping to provoke a response from somebody
who is still using that kind of part.

> I'd happily use a metal-gate 4046 at frequencies where they work--all
> you need is a resistor to ground from the PD2 output to pull it off the
> dead zone.
>
> Above a megahertz or so, a current-programmed triangle wave oscillator
> is good,

Sure. A 1GHz gbw op amp could take you quite a way above 1MHz.

>or else a linearized LC VCO. You can get linearities of better
> than 10% in varactor-tuned VCOs by putting in a couple of off-stage
> resonances.

Messy. I'd be thinking of a digitally controlled Direct Digital
Synthesis chip, which would be a lot tidier and would probably have a
lower jitter (if you low-pass filtered the synthesised sine wave
properly). For a seriously low jitter option, a DDS-like system
including an MC100E195 might be interesting - if complicated. Coping
with the temperature dependence of the delay through the MC100E195
might require Peltier junction or a self-calibrating scheme if you
really wanted to exploit the full capacity of the MC100E195.

--
Bill Sloman, Sydney

[Allan Herriman]

I would have bought it up to about seven years ago. That was the last
time I used a '46 (actually a '9046 with its better phase detector).
I left the oscillator disabled.

These days, for the sorts of things I design, I'm more likely to replace
the entire application with something like this:
http://www.silabs.com/products/clocksoscillators/clocks/Pages/Any-RateJitterAttenuatingClockMultipliers.aspx

Regards,
Allan

[George Herold]

On Oct 17, 3:08 pm, Phil Hobbs

> 24 ofhttp://tinyurl.com/c3xgcgq, or  the TI one, P. 14 ofhttp://tinyurl.com/cghq2yb.

>
> Even the much-ballyhooed HC9046 has the same sorts of worries, see P.24

> ofhttp://tinyurl.com/chlkgwv. Many of the typical curves are probably

> acceptably linear for most PLL uses, but I for one do not get a warm
> fuzzy feeling about the unit-to-unit repeatability, based on those curves.
>

> And check out the actual HC4046--first in a Chinese knockoff,http://tinyurl.com/buvdkbyP. 490,

> then the TI version, P. 14 ofhttp://tinyurl.com/ckz4ezv,
> and then in the ON semi versions, P. 11 ofhttp://tinyurl.com/cyymxsl.
>
> Compare that with the HEF4046 (NXP metal gate version)--check out the

> VCO linearity error plot on P. 15 ofhttp://tinyurl.com/cl3c7vv.  The

> TI CD4046B claims 0.7% linearity from 2.5V to 7.5V with a 10V supply,http://tinyurl.com/cpd3skg.
>
> The HC versions are all over the map.
>
> Cheers
>
> Phil Hobbs
>
> --
> Dr Philip C D Hobbs
> Principal Consultant
> ElectroOptical Innovations LLC
> Optics, Electro-optics, Photonics, Analog Electronics
>
> 160 North State Road #203
> Briarcliff Manor NY 10510
>

> hobbs at electrooptical dot nethttp://electrooptical.net- Hide quoted text -
>
> - Show quoted text -

Thanks for all the links Phil, I was just checking on which 'flavor'
my data is from.

So the data I took was for TI's 4046... and I now notice that someone
in production purchased the more expensive NXP flavor.... grumble, I
should go back and re-measure.
(Why do people always have to 'piss a bit in the pot' and change
things?)

George H.

[Tom Del Rosso]

Phil Hobbs wrote:

> On 10/15/2012 07:59 PM, Jim Thompson wrote:
> > Finally zeroing in on modeling the 74HC4046 after finding a
> > unpublished AppNote that gave more details on the innards. This is
> > what a fixed frequency looks like, simulation-wise...
> >
> > http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
> >
> > Comments? Scalings? (This is based on AppNote and Datasheets
> > claiming trip at VDD/2).
> >
> > First release will be VCO only and will be in LTspice format. Once
> > you approve that, the PFD is virtually all logic.
> >
> > ...Jim Thompson
>

> Different manufacturers give you a wide variety of ridiculously
> nonlinear tuning curves for the VCO--the tuning sensitivity varies

> like 3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5)
> depending on the device.
>

> Which did you pick? ;)
>

> (The metal gate 4046-style oscillators all stink on ice--HC4046,
> HC7046, HC9046, all makers, all horrible. PD2 is nice if you stay
> out of the dead zone.)

I always wondered what the "phase pulses" were good for. If you don't need
them, my 8-gate wonder* would do, and I don't think it has a dead zone.


*
SET -----+------------------------|
| |NAND>--+
+-------| +--| |
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| | |
|NAND>-----+ |
+-------| +--| Q
| |NAND>--+-------
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+----
+-------| +--|
|NAND>--+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| | |
|NAND>-----+--+ |
+-------| +--| |
| |NAND>--+
RESET -----+------------------------|


--

Reply in group, but if emailing add one more
zero, and remove the last word.

[Jim Thompson]

Taking note that I'm not a logic designer, I'm not sure your version
covers all states. It took Ron Treadway NINE gates back in the
mid-60's in the MC4044...

http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |

[Phil Hobbs]

Digital PLLs don't have the performance of analogue ones, and are far,
far more complicated and power hungry. My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.

You can get inductors in 2% tolerances, and the varactors of course are
variable (and also good to +-5% to 8%), so you don't need tweaks to get
a very respectable linearity improvement. That means that you can be
more aggressive on the loop compensation, and the improved performance
is worth a lot.

[Phil Hobbs]

Wow, $35? I can buy a lot of good analogue stuff for that!

[Phil Hobbs]

The phase pulse output is for lock detection. PD2's output is valid in
any condition, and when using PD2, PD1 will have a 50% duty cycle when
the loop is locked and also when one of the input signals is missing.

I normally just put a window comparator on the PD2 output and use that,
since the filtered output pulls to the rail when it's out of lock.

[John Larkin]

We have considered using a phase detector and a DDS, 100% digital PLL,
inside an FPGA to be able to do i/q demodulation of digitized sinewave
signals. It sounded like fun, but we never had a firm application (ie,
paying customer) to justify doing it.

In one case, it would have been AC line stuff, 50 or 60 or 400 Hz,
fairly narrowband (except aircraft 400 Hz is all over the place.) In
another, it would be synchro/LVDT, pretty much audio kind of range.

The digital PLL takes no parts... it's just a heap of VHDL.



--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

[Phil Hobbs]

If you already have an FPGA, sure, dump it in with all the other crap. ;)

A good diode phase detector such as an MPD-1 makes it a pleasure to
build first-class PLLs. Lots of output, zilch noise, low and stable
offset voltage, easy to drive from logic if you need to. Good medicine.

[Gerhard Hoffmann]

As far as I remember that's the very first time I disagree with you, but
for this subject I do. A customer of mine builds world class analog
DLLs & PLLs for special navigation and timing systems, but when every ps
counts, analog is really running out of steam. Just try to buy a
state-of-the-art S&H. You get it if you buy a 16 bit /200 MHz ADC, too.

There is no such thing as "low and stable offset voltage". There is
offset voltage, and that dictates unpleasant architecture decisions
because the appearant channel delay varies depending on what
state of a QPDM signal you happen to lock to. Or so.

We are about to digitize in L-Band, the downconverter / polyphase
filter will perhaps be 8-way. That means 8 DDS-es, 8 sin/cos tables,
8 complex mixers etc, dissipating lots of power, but that
power will not shift the phase/delay of some analog low pass.

;-) have a good night, Gerhard

[Jeroen]

I have this particle beam trajectory measurement system where lots
of fully digital PLLs are used to follow bunches of protons around
a particle accelerator. It spits out the bunch trajectories at an
aggregate rate of up to 280M bunch positions per second. All FPGAs.
A British firm built it for me. Operators love it. I'm in the
process of making a second system for another accelerator.

Jeroen Belleman

[Bill Sloman]

On Oct 19, 4:00 am, Phil Hobbs

> Digital PLLs don't have the performance of analogue ones,

Probably not generally true.

> and are far, far more complicated

Probably true, but our business is burying the complication so nobody
else has to worry about it.

> and power hungry.

I'm not sure about that as a general statement. I've alway been take
with the low power consumption of the Philips/NXP now Xilinx
CoolRunner CMOS parts - when you didn't tray and run them too fast -
which is why I've got a stick of 15 of them in my cupboard here,
waiting for a project to exploit them

> My usual use for PLLs is
> demodulation rather than frequency synthesis, so DDSes are pretty much
> beside the point.

Why?

> You can get inductors in 2% tolerances, and the varactors of course are
> variable (and also good to +-5% to 8%), so you don't need tweaks to get
> a very respectable linearity improvement.  That means that you can be
> more aggressive on the loop compensation, and the improved performance
> is worth a lot.

But there's a great deal of manual labour tweaking each example to get
it's particular linearity respectable. Physicists have graduate
students to do that sort of labour. Engineers designing for production
can't afford them.

--
Bill Sloman, Sydney

[Bill Sloman]

> > hobbs at electrooptical dot nethttp://electrooptical.net-Hide quoted text -

>
> > - Show quoted text -
>
> Thanks for all the links Phil,  I was just checking on which 'flavor'
> my data is from.
>
> So the data I took was for TI's 4046... and I now notice that someone
> in production purchased the more expensive NXP flavor.... grumble, I
> should go back and re-measure.
> (Why do people always have to 'piss a bit in the pot' and change
> things?)

Buyers get bribed by sales people. Junior engineers get snowed by
sales people - it's the latest design so it must be better - and so
forth. Sometimes the more modern parts are simply cheaper, and still
good enough - soemtimes better on every parameter except the one that
matters.

I used to field a lot of that kind of query from purchasing when I was
at Cambridge Instruments - I tried to answer them fast so that they
wouldn't have any excuse for leaving enegineering out of the loop.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 19, 4:06 am, Phil Hobbs

<pcdhSpamMeSensel...@electrooptical.net> wrote:
> On 10/18/2012 07:06 AM, Allan Herriman wrote:
>
>
>
> > On Wed, 17 Oct 2012 15:57:57 -0700, Jim Thompson wrote:
>
> >> On Tue, 16 Oct 2012 16:19:44 -0400, Phil Hobbs

> >> <pcdhSpamMeSensel...@electrooptical.net>  wrote:

>
> >>> On 10/16/2012 02:30 PM, Jim Thompson wrote:
> >>>> On Tue, 16 Oct 2012 14:02:39 -0400, Phil Hobbs
> >>>> <pcdhSpamMeSensel...@electrooptical.net>   wrote:
>
> >>>>> On 10/16/2012 11:56 AM, Jim Thompson wrote:
> >>>>>> On Tue, 16 Oct 2012 11:25:52 -0400, Phil Hobbs

> >>>>>> <pcdhSpamMeSensel...@electrooptical.net>    wrote:

> >http://www.silabs.com/products/clocksoscillators/clocks/Pages/Any-Rat...

>
> > Regards,
> > Allan
>
> Wow, $35?  I can buy a lot of good analogue stuff for that!

Then spend $35 worth of labour tweeking it to get the linearity right.

--
Bill Sloman, Sydney

[Tom Del Rosso]

Jim Thompson wrote:
>
> Taking note that I'm not a logic designer, I'm not sure your version
> covers all states.

It passed your sim with slightly different frequencies at each input to
create a walking phase shift.

You did need to match the gates. If they were simmed as discrete 7400's
then you had to take the 4 on the left from one package.

> It took Ron Treadway NINE gates back in the
> mid-60's in the MC4044...
>
> http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

I know. That's why I was surprised it worked with 8 as quoted:

==========quote==========
Newsgroups:
alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc
Sent: Monday, August 27, 2001 10:26 PM
Subject: Re: Help an Analog Guy with a Digital Problem

|> The internal feedback disabled the pulse too soon. The resulting
|> pulse width at the final latch was about 1/2 of what it is with
|> feedback from the output (~2.5nS vs 5nS).
|
|Ok. So was your testing of the last circuit sucessful under full load?
|

You bet...you're now in a product...E-Mail for details.
=========================

[Phil Hobbs]

Bill Sloman wrote:

> On Oct 19, 4:00 am, Phil Hobbs
> <pcdhSpamMeSensel...@electrooptical.net> wrote:
>

<snip>

>
> > My usual use for PLLs is
> > demodulation rather than frequency synthesis, so DDSes are pretty much
> > beside the point.
>
> Why?

Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done. Analogue loops rock. Doing it digitally makes as
much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.

>
>
> > You can get inductors in 2% tolerances, and the varactors of course are
> > variable (and also good to +-5% to 8%), so you don't need tweaks to get
> > a very respectable linearity improvement. That means that you can be
> > more aggressive on the loop compensation, and the improved performance
> > is worth a lot.
>
> But there's a great deal of manual labour tweaking each example to get
> it's particular linearity respectable. Physicists have graduate
> students to do that sort of labour. Engineers designing for production
> can't afford them.

Not true--read what I wrote above. Inexpensive close-tolerance inductors do just
fine.

How are you liking being back in OZ? Run into Phil A. yet?

Cheers

Phil Hobbs

[Jim Thompson]

Thanks, Tom! I'll have to try that. Does it have deadband?

[Jan Panteltje]

On a sunny day (Fri, 19 Oct 2012 08:59:28 -0400) it happened Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote in
<50814EB0...@electrooptical.net>:

>
>
>Bill Sloman wrote:
>
>> On Oct 19, 4:00 am, Phil Hobbs
>> <pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>
><snip>
>
>>
>> > My usual use for PLLs is
>> > demodulation rather than frequency synthesis, so DDSes are pretty much
>> > beside the point.
>>
>> Why?
>
>Because driving them in a demodulator loop is a completely needless hassle, and won't
>do as good a job when you're done. Analogue loops rock. Doing it digitally makes as
>much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.

mm
:-)
See my posting in s.e.d today with subject:
GPS frequency counter + PLL PIC based

[Bill Sloman]

On Oct 19, 11:59 pm, Phil Hobbs
<pcdhSpamMeSensel...@electrooptical.net> wrote:
> BillSlomanwrote:

> > On Oct 19, 4:00 am, Phil Hobbs
> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>
> <snip>
>
> > > My usual use for PLLs is
> > > demodulation rather than frequency synthesis, so DDSes are pretty much
> > > beside the point.
>
> > Why?
>
> Because driving them in a demodulator loop is a completely needless hassle, and won't
> do as good a job when you're done.

Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.

>Analogue loops rock.  Doing it digitally makes as
> much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.

There are occasion when an ADC plus digital signal processing plus a
DAC do make sense - as soon as you want a non-linear or - worse - a
non-monotonic relationship between input and output. For phase-locked
loops this happens quite often - as Floyd M Gardener pointed out, the
sort of phase-sensitive detector that gives you the best lock doesn't
necessarily get you into lock as fast as you'd like.

The DDS approach comes into its own when you want several sine wave
sources at once - for detecting at twice the frequency or both in-
phase and in quadrature. The analogue techniques for doing this are no
less messy and generally give you a poorer quality sine wave.

> > > You can get inductors in 2% tolerances, and the varactors of course are
> > > variable (and also good to +-5% to 8%), so you don't need tweaks to get
> > > a very respectable linearity improvement.  That means that you can be
> > > more aggressive on the loop compensation, and the improved performance
> > > is worth a lot.
>
> > But there's a great deal of manual labour tweaking each example to get
> > it's particular linearity respectable. Physicists have graduate
> > students to do that sort of labour. Engineers designing for production
> > can't afford them.
>
> Not true--read what I wrote above.  Inexpensive close-tolerance inductors do just
> fine.

Inexpensive close tolerance varactors don't seem to be as readily
available. And the tuning range available is rarely impressive.

Varactors have a roughly hyperbolic capacitance to voltage
relationship, so getting the tuning loop critically damped isn't going
to be all that easy.

> How are you liking being back in OZ?  Run into Phil A. yet?

Phil Allison does live in Sydney, but I don't expect to run into him -
I did suggest (here) that we get together over a coffee a few years
ago but he didn't like the idea.

Oz has been fine so far, but we're not yet entirely out of jet-lag.
We've been keeping a low profile. I did apply for two jobs yesterday,
but that was more to get my name on the books than in any expectation
that I'd get anything. My wife wants to buy a car today, which is
going to take a while.

--
Bill Sloman, Nijmegen

[John Larkin]

On Fri, 19 Oct 2012 15:02:51 -0700 (PDT), Bill Sloman
<bill....@ieee.org> wrote:

>On Oct 19, 11:59 pm, Phil Hobbs
><pcdhSpamMeSensel...@electrooptical.net> wrote:
>> BillSlomanwrote:
>> > On Oct 19, 4:00 am, Phil Hobbs
>> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>> <snip>
>>
>> > > My usual use for PLLs is
>> > > demodulation rather than frequency synthesis, so DDSes are pretty much
>> > > beside the point.
>>
>> > Why?
>>
>> Because driving them in a demodulator loop is a completely needless hassle, and won't
>> do as good a job when you're done.
>
>Why do you think that? The DDS syntheisised sine wave is likely to
>have a lower jitter than you'd get from most VCOs, and you've got a
>whole lot better idea of the frequency you are synthesising.

DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.

The real nuisance in a DDS is the damned lowpass filter.

VCOs can be a lot better, and VCXOs hugely better.

[Jamie]

Slugman is like the yellow line on the road, he's always in the
middle, can't take either side but yet, his lines seem to break left or
right at
every turning post.

He just can't maintain solid facts or lines.

Jamie

[Tom Del Rosso]

That exchange was you, me, you. You tested it and according to the email it
went into an RFID Tag Chip that reports temperature and pressure of its
environment via a 2.4GHz RF Link.

Deadband like a frequency where it doesn't work? Wouldn't there just be an
upper limit that depends on the logic speed? I can't teach you anything
about that. You'll have to teach me.

Here is the diagram with markings to show the sequence of transitions. The
=0 and =1 indicate constant states. The "x" after a number means no
further changes are caused by that transition. If you build it with NOR's
it is negative-edge triggered.


below: Q(initially) = 0 RESET = 0


/0
SET -----+------------------------|
| |NAND>--+ \1
+-------| \5 +--| | /6x

|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |

+--| /4 | |
|NAND>-----+ |
\3 +-------| +--| Q
| |NAND>--+------- /2

+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q

| |NAND>-----+---- \3
/2 +-------| +--|
|NAND>--+ \3x |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 0 RESET = 1


/0
SET -----+------------------------|
| |NAND>--+ \1
+-------| \5 +--| | /6x

|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |

+--| /4 | |
|NAND>-----+ |
\3 +-------| +--| Q
| |NAND>--+------- /2

+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q

| |NAND>-----+---- \3
/2 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 0


/0
SET -----+------------------------|
| |NAND>--+ \1
+-------| \1 +--| | /2x

|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |

+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1

+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q

| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =0 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 1


/0
SET -----+------------------------|
| |NAND>--+ \1
+-------| \1 +--| | /2x

|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |

+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1

+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q

| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|

[Bill Sloman]

On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com>
wrote:

> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
>

> <bill.slo...@ieee.org> wrote:
> >On Oct 19, 11:59 pm, Phil Hobbs
> ><pcdhSpamMeSensel...@electrooptical.net> wrote:
> >> BillSlomanwrote:
> >> > On Oct 19, 4:00 am, Phil Hobbs
> >> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>
> >> <snip>
>
> >> > > My usual use for PLLs is
> >> > > demodulation rather than frequency synthesis, so DDSes are pretty much
> >> > > beside the point.
>
> >> > Why?
>
> >> Because driving them in a demodulator loop is a completely needless hassle, and won't
> >> do as good a job when you're done.
>
> >Why do you think that? The DDS syntheisised sine wave is likely to
> >have a lower jitter than you'd get from most VCOs, and you've got a
> >whole lot better idea of the frequency you are synthesising.
>
> DDSs suck for jitter. Unfiltered, looking at the phase accumulator
> MSB, they have a full clock of p-p jitter.

Obviously. but what sort of idiot would use one that way? Of course,
if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.

http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html#Direct_Digital_Synthesis

When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.

> DAC'd and filtered, into a
> comparator, it's more complex, but much below the LPF cutoff, you're
> basically quantized to the DAC resolution. Jitter like 1 part in
> 20,000 is common for a 16-bit system.

Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.

The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.

> The real nuisance in a DDS is the damned lowpass filter.

You should have paid closer attention during the relevant lectures

> VCOs can be a lot better,

Only if you find low-pass filters intimidating

> and VCXOs hugely better.

VCXO do - however - tend to be rather restricted in the frequencies
they can generate.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 20, 10:59 am, Jamie

That's Jamie for you. John Larkin makes a fool of himself and Jamie
chimes in to tell us that he too is intellectually limited - as if we
didn't already know.

--
Bill Sloman, Sydney

[John Larkin]

On Fri, 19 Oct 2012 21:01:19 -0700 (PDT), Bill Sloman
<bill....@ieee.org> wrote:

>On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com>
>wrote:
>> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
>>
>> <bill.slo...@ieee.org> wrote:
>> >On Oct 19, 11:59 pm, Phil Hobbs
>> ><pcdhSpamMeSensel...@electrooptical.net> wrote:
>> >> BillSlomanwrote:
>> >> > On Oct 19, 4:00 am, Phil Hobbs
>> >> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>> >> <snip>
>>
>> >> > > My usual use for PLLs is
>> >> > > demodulation rather than frequency synthesis, so DDSes are pretty much
>> >> > > beside the point.
>>
>> >> > Why?
>>
>> >> Because driving them in a demodulator loop is a completely needless hassle, and won't
>> >> do as good a job when you're done.
>>
>> >Why do you think that? The DDS syntheisised sine wave is likely to
>> >have a lower jitter than you'd get from most VCOs, and you've got a
>> >whole lot better idea of the frequency you are synthesising.
>>
>> DDSs suck for jitter. Unfiltered, looking at the phase accumulator
>> MSB, they have a full clock of p-p jitter.
>
>Obviously. but what sort of idiot would use one that way?

Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.

Of course,
>if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
>tolerable.
>
>http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html#Direct_Digital_Synthesis
>
> When I mentioned DDS's earlier in this thread I did mention that you
>ought to filter the output, but I'd figured that people like you and
>Phil Hobbs wouldn't need to be reminded.

We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.

But reminded? By you? I design electronics, and you don't.

>
>> DAC'd and filtered, into a
>> comparator, it's more complex, but much below the LPF cutoff, you're
>> basically quantized to the DAC resolution. Jitter like 1 part in
>> 20,000 is common for a 16-bit system.
>
>Actually, as long as the DAC refresh time is shorter than your low
>pass filter 3dB point, you should do appreciably better than the DAC
>resolution.
>
>The "noise" on a pure staircase waveform is essentially a sawtooth
>wave at the DAC refresh rate, and that ought to be a lot faster than
>the frequency you are interested in, and correspondingly easy to
>filter out. Four or six poles of low pass filter isn't going to cost
>anything like as much as the DDS chip.

The filter takes a lot more area, and does often cost more.

At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus. The
plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.

I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.

>
>> The real nuisance in a DDS is the damned lowpass filter.
>
>You should have paid closer attention during the relevant lectures
>

What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.

How many DDS synthesizers have you designed in the last 10 years? I've
done a dozen or so. Hell, have you ever designed a DDS into something?

http://www.highlandtechnology.com/categories/waveform_generators.shtml




--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom timing and laser controllers

Photonics and fiberoptic TTL data links

VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

[Bill Sloman]

On Oct 20, 3:58 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman

> >if your DDS has a 500MHz internal clock, 2nsec of jitter might be
> >tolerable.
>
> >http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...

>
> > When I mentioned DDS's earlier in this thread I did mention that you
> >ought  to filter the output, but I'd figured that people like you and
> >Phil Hobbs wouldn't need to be reminded.
>
> We don't use standard DDS chips very often. We do our own DDS logic in
> an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
> off-chip.
>
> But reminded? By you? I design electronics, and you don't.

I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.

> >> DAC'd and filtered, into a
> >> comparator, it's more complex, but much below the LPF cutoff, you're
> >> basically quantized to the DAC resolution. Jitter like 1 part in
> >> 20,000 is common for a 16-bit system.
>
> >Actually, as long as the DAC refresh time is shorter than your low
> >pass filter 3dB point, you should do appreciably better than the DAC
> >resolution.
>
> >The "noise" on a pure staircase waveform is essentially a sawtooth
> >wave at the DAC refresh rate, and that ought to be a lot faster than
> >the frequency you are interested in, and correspondingly easy to
> >filter out. Four or six poles of low pass filter isn't going to cost
> >anything like as much as the DDS chip.
>
> The filter takes a lot more area, and does often cost more.

If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.

> At low frequencies, the filter output settles between phase
> accumulator code transitions, so the waveform has plateaus.

Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.

> The plateaus trip the comparator at fuzzy levels, so you get a lot of
> jitter.

It's not the plateau that trips the comparator, but the noise on the
plateau. A little hysteresis around the comparator might help, but I
shouldn't have to point this out to someone with your extravagantly
practiced expertise.

> As I said, period jitter of about 1/20000 RMS is typical for a
> 16 bit system. One trick is to keep the DDS frequency high, so the
> filter stays in its sweet spot, and divide down after the comparator.
>
> I don't understand why ADI makes so many DDS chips, but doesn't make
> an integrated lowpass filter.

The DDS chips would be built with a logic process, while the filter
could be expected to be analog. A delay line that could be used to set
up a FIR filter could be interesting, but it would use up a lot of
pins.

> >> The real nuisance in a DDS is the damned lowpass filter.
>
> >You should have paid closer attention during the relevant lectures
>
> What an ass you are. I got my EE degree before DDS was invented, and
> you are even older than I am.

I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.

> How many DDS synthesizers have you designed in the last 10 years?

None. I've been out of work aka retired for the last ten years, as you
well know

> I've done a dozen or so. Hell, have you ever designed a DDS into something?

Nothing that got built. I still managed to get my head around the idea
that you ought to filter what comes out of the DAC, which doesn't seem
to have lodged all that firmly with you.

<snipped more advertising>

--
Bill Sloman, Sydney

[Jamie]

Actually, it's quite the opposite. Good show.

Jamie

[Jamie]

I can say one thing about slugman, it does not usually impersonate that
often, he's doing very well at being himself, the ASS.

Jamie

[Bill Sloman]

On Oct 20, 11:58 pm, Jamie

<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> John Larkin wrote:

> > On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman

> >>http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...

Jamie may be slow, but he's persistent. Pity about the direction.

--
Bill Sloman, Sydney

[John Larkin]

"Ought to" means that you are following hearsay. We use filters when
it makes sense.

It's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.

Your story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.

>
>> >> DAC'd and filtered, into a
>> >> comparator, it's more complex, but much below the LPF cutoff, you're
>> >> basically quantized to the DAC resolution. Jitter like 1 part in
>> >> 20,000 is common for a 16-bit system.
>>
>> >Actually, as long as the DAC refresh time is shorter than your low
>> >pass filter 3dB point, you should do appreciably better than the DAC
>> >resolution.
>>
>> >The "noise" on a pure staircase waveform is essentially a sawtooth
>> >wave at the DAC refresh rate, and that ought to be a lot faster than
>> >the frequency you are interested in, and correspondingly easy to
>> >filter out. Four or six poles of low pass filter isn't going to cost
>> >anything like as much as the DDS chip.
>>
>> The filter takes a lot more area, and does often cost more.
>
>If you've built the logic part of the DDS chip into a corner of an
>FPGA this could well be true. No DAc and no filter sounds like taking
>economy a little too far.
>
>> At low frequencies, the filter output settles between phase
>> accumulator code transitions, so the waveform has plateaus.
>
>Only if your low pass filter cuts off at too high a frequency. This
>does depend on the frequency range you want to cover, and if you were
>going nuts you might look at ways of moving the 3dB point of the low
>pass filter around to cover a really wide frequency range.

Please design a suitable tunable, adaptive filter and post it here.
Cutoff from, say, 45 KHz to 45 MHz, glitch-free tuning. 7 poles would
be adequate.

>
>> The plateaus trip the comparator at fuzzy levels, so you get a lot of
>> jitter.
>
>It's not the plateau that trips the comparator, but the noise on the
>plateau.

Or its residual slope.

A little hysteresis around the comparator might help, but I
>shouldn't have to point this out to someone with your extravagantly
>practiced expertise.

Idiot. Hysteresis won't help the jitter at all.

What does help a bit is digital interpolation, between lookup table
entries, at the full clock rate. We do that in several of our
products. It is especually useful in products that have multiple DDSs
on chip and allow cross-synthesizer moddulations, like our V346. Any
DDS can AM/FM/PM any other, in compound paths. All the modulations are
on-chip, and only the final outputs have DACs and filters.

>
>> As I said, period jitter of about 1/20000 RMS is typical for a
>> 16 bit system. One trick is to keep the DDS frequency high, so the
>> filter stays in its sweet spot, and divide down after the comparator.
>>
>> I don't understand why ADI makes so many DDS chips, but doesn't make
>> an integrated lowpass filter.
>
>The DDS chips would be built with a logic process, while the filter
>could be expected to be analog.

Their full company name is Analog Devices.

A delay line that could be used to set
>up a FIR filter could be interesting, but it would use up a lot of
>pins.
>
>> >> The real nuisance in a DDS is the damned lowpass filter.
>>
>> >You should have paid closer attention during the relevant lectures
>>
>> What an ass you are. I got my EE degree before DDS was invented, and
>> you are even older than I am.
>
>I never got an EE degree, and learned the stuff when I needed it - and
>read up on it from time to time when I needed more.
>Low pass filters aren't either complicated or difficult. Why you feel
>the need to describe them as "damned" escapes me.

It escapes you because you don't actually design DDSs or their
filters.

>
>> How many DDS synthesizers have you designed in the last 10 years?
>
>None. I've been out of work aka retired for the last ten years, as you
>well know
>
>> I've done a dozen or so. Hell, have you ever designed a DDS into something?
>
>Nothing that got built.

That seems to be your history, designing stuff that doesn't get built.

Get an ADI DDS eval board and learn something.

[Michael A. Terrell]

http://www.ebay.com/itm/280840956721

[John Larkin]

Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
too.

One can usually get an eval board for free, from an ADI rep. But you'd
have to sound competant and friendly, which would both be difficult
for Sloman.

[Jamie]

There is no amount of bull shit you can spread here that would change my
view of you using this place as a dumping ground.

Polluting is illegal in most places around the world.

Jamie

[Michael A. Terrell]

Now, all he has to do is collect enough empty beer cans to pay for
it.

[Bill Sloman]

On Oct 21, 2:53 am, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman

"Hearsay" is this context, is body of electronic knowledge that
motivated the development of the DDS approach. An accumulator
generates a sequence of digital phase values for the sine wave being
synthesised, a look-up table turns this into a sequency of digital
amplitudes, and a DAC turns this into a sequence of analog voltages
(or currents), which ias a staircase approximation to the desired
waveform. The Fourier transform of this waveform includes the desired
fundamental and the undesired high frequency artifacts representing
the steps in the staircase, which you can filter out to any desired
degree with a suitable low pass filter.

All hearsay, until you build the hardware, but peculiarly reliable
hearsay.

> It's bad enough that you make statements that are uninformed or wrong,
> but you have to phrase them as personal insults.

You do find personal insults where most people would merely find
colourful language.

> Your story about applying for work at ASML summarizes the situation:
> your are way to obnoxious for your own good.

I upset the personal department by going behind their backs to talk to
an engineer that I'd been interviewed by earlier. Personnel
departments aren't good at evaluating engineers. Good ones know it and
don't get too upset about being by-passed. Bad ones know it too but
hate being reminded that they aren't as clever as they like to think.
At ASML it looks as if the guy in charge was more interested in
defending his right to act as a gatekeeper than in getting the right
people through the gate.

What - precisely - is the application? The obvious solution would be
clock-tuned FIR filter, where the filter shaped was determined by a
bunch of resistors (or mabybe capacitors - I've not designed a
capacitor based version, but I've a vague idea that it might be
practical).

That sort of requirement usually means that somebody has screwed up
their system design, and you'd be better off thinking out the system
again.

> >> The plateaus trip the comparator at fuzzy levels, so you get a lot of
> >> jitter.
>
> >It's not the plateau that trips the comparator, but the noise on the
> >plateau.
>
> Or its residual slope.

Some devices do have a specified minimum slew rate for reliable
operation; essentially this reflect the spectral distribution of the
internal nosie sources (generally PSRR in practice).

>  A little hysteresis around the comparator might help, but I
> >shouldn't have to point this out to someone with your extravagantly
> >practiced expertise.
>
> Idiot. Hysteresis won't help the jitter at all.

If the comparator flips repeatedly as the waveform goes through 0V (or
whatever threshold you've chosen) you'll have a nasty output.
Hysterisis will prevent that, and the high frequency noise that the
comparator will inject into the system as it flips repeatedly

If the internal noise around the comparator means that it flips once,
but at an uncertain time determined by the amplitude of the noise
divided by the slope or the ramp, you will have jitter, but that's
just the second law of thermodynamics.

> What does help a bit is digital interpolation, between lookup table
> entries, at the full clock rate. We do that in several of our
> products. It is especually useful in products that have multiple DDSs
> on chip and allow cross-synthesizer moddulations, like our V346. Any
> DDS can AM/FM/PM any other, in compound paths. All the modulations are
> on-chip, and only the final outputs have DACs and filters.

Digitally interpolating what, where? I presume you are using multiple
DDS's to synthesise a modulated sine wave - which is to say that you
are multipling the amplitudes in the digital domain

> >> As I said, period jitter of about 1/20000 RMS is typical for a
> >> 16 bit system. One trick is to keep the DDS frequency high, so the
> >> filter stays in its sweet spot, and divide down after the comparator.
>
> >> I don't understand why ADI makes so many DDS chips, but doesn't make
> >> an integrated lowpass filter.
>
> >The DDS chips would be built with a logic process, while the filter
> >could be expected to be analog.
>
> Their full company name is Analog Devices.

The term "process" refers to the sequence of operations used to
convert a the surface of a silicon wafer into a integrated circuit.
Some processes are optimised to produce digital logic, others to
produce analog devices, and some can be used to produce mixed signal
devices.

http://www.analog.com/en/press-release/06_20_12_ADI_and_TSMC_Collaborate_on_New_Analog/press.html

Back when I was working on the Cambridge Instruments Electron Beam
Testers for looking at the surfaces of bare chips while they were
working, the customers would talk to us about that kind of stuff, but
only in broad terms.

>
> > A delay line that could be used to set
> >up a FIR filter could be interesting, but it would use up a lot of
> >pins.
>
> >> >> The real nuisance in a DDS is the damned lowpass filter.
>
> >> >You should have paid closer attention during the relevant lectures
>
> >> What an ass you are. I got my EE degree before DDS was invented, and
> >> you are even older than I am.
>
> >I never got an EE degree, and learned the stuff when I needed it - and
> >read up on it from time to time when I needed more.
> >Low pass filters aren't either complicated or difficult. Why you feel
> >the need to describe them as "damned" escapes me.
>
> It escapes you because you don't actually design DDSs or their
> filters.

I've designed quite enough filters to appreciate where it gets
interesting.

> >> How many DDS synthesizers have you designed in the last 10 years?
>
> >None. I've been out of work aka retired for the last ten years, as you
> >well know
>
> >> I've done a dozen or so. Hell, have you ever designed a DDS into something?
>
> >Nothing that got built.
>
> That seems to be your history, designing stuff that doesn't get built.

It's not the whole of my history by any means. The electron beam
tester got built, and worked, but never went into production. Quite a
bit of the less ambitious stuff did go all the way. You seem to
concentrate on doing lots of little, less ambitious designs, and have
more stuff that makes it into production.

> Get an ADI DDS eval board and learn something.

If I had a potential customer for the knowledge that I might acquire,
I'd do it like a shot. At the moment I'm more interested in looking at
the Sydney job ads - I found two that I could reasonably respond to on
Friday, and sent my CV off to the relevant agencies. I expect to get
brushed off - after the Netherlands my expectations aren't high - but
it does get my name into the database.

Settling in in Sydney is distinctly time consuming. We wandered around
the Sydney Motor Show last night and my wife bought a car, which means
more bureaucratic procedures to be dealt with.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 21, 4:31 am, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sat, 20 Oct 2012 13:11:08 -0400, "Michael A. Terrell"
> <mike.terr...@earthlink.net> wrote:
> >John Larkin wrote:

> >> On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman

> >> <bill.slo...@ieee.org> wrote:
> >> >On Oct 20, 3:58 pm, John Larkin
> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com>
> >> >> >wrote:
> >> >> >> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
> >> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >> >On Oct 19, 11:59 pm, Phil Hobbs
> >> >> >> ><pcdhSpamMeSensel...@electrooptical.net> wrote:
> >> >> >> >> BillSlomanwrote:
> >> >> >> >> > On Oct 19, 4:00 am, Phil Hobbs
> >> >> >> >> > <pcdhSpamMeSensel...@electrooptical.net> wrote:

<snip>

> >> Get an ADI DDS eval board and learn something.
>
> >http://www.ebay.com/itm/280840956721
>
> Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
> too.
>
> One can usually get an eval board for free, from an ADI rep. But you'd

> have to sound competent and friendly, which would both be difficult
> for Sloman.

They seemed friendly enough at the last Analog Devices seminar I
attended - which looks as if it was in Eindhoven in September last
year. I had more clout when I worked for Cambridge Instruments, and we
once got a site visit from Barry Gilbert - I'd hoped to be able to
sell him on the electron beam tester, but the RF parts he was pushing
were a bit quick for the hardware we'd put together then. I'd had some
ideas about coping with faster integrated circuits, but the priority
at that time was on perfecting what we had.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Oct 21, 7:08 am, "Michael A. Terrell" <mike.terr...@earthlink.net>

wrote:
> John Larkin wrote:
>
> > On Sat, 20 Oct 2012 13:11:08 -0400, "Michael A. Terrell"
> > <mike.terr...@earthlink.net> wrote:
>
> > >John Larkin wrote:
>

> > >> On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman

> > >> <bill.slo...@ieee.org> wrote:
>
> > >> >On Oct 20, 3:58 pm, John Larkin
> > >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> > >> >> On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
> > >> >> <bill.slo...@ieee.org> wrote:
> > >> >> >On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com>
> > >> >> >wrote:
> > >> >> >> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
> > >> >> >> <bill.slo...@ieee.org> wrote:
> > >> >> >> >On Oct 19, 11:59 pm, Phil Hobbs
> > >> >> >> ><pcdhSpamMeSensel...@electrooptical.net> wrote:
> > >> >> >> >> BillSlomanwrote:
> > >> >> >> >> > On Oct 19, 4:00 am, Phil Hobbs
> > >> >> >> >> > <pcdhSpamMeSensel...@electrooptical.net> wrote:

<snip>

> > >> Get an ADI DDS eval board and learn something.
>
> > >http://www.ebay.com/itm/280840956721
>
> > Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
> > too.
>
> > One can usually get an eval board for free, from an ADI rep. But you'd
> > have to sound competant and friendly, which would both be difficult
> > for Sloman.
>
>    Now, all he has to do is collect enough empty beer cans to pay for
> it.

Mike Terrell's can't imagine that I've got more money than he has. If
I need that kind of stuff I buy it from Farnell. Finding some place to
store it is more of a constraint.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 21, 5:56 am, Jamie
<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> BillSlomanwrote:

> There is no amount of bull shit you can spread here that would change my
> view of you using this place as a dumping ground.
>
>    Polluting is illegal in most places around the world.

Jamie can't tell shit from shinola., and has no inhibitions about
advertising his inadequecies. Sad.

--
Bill Sloman, Sydney

[John Larkin]

Sounds to me that he did his job very well.

[Bill Sloman]

On Oct 21, 10:27 am, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sat, 20 Oct 2012 15:49:56 -0700 (PDT),BillSloman
> <bill.slo...@gmail.com> wrote:
> >On Oct 21, 2:53 am, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman
> >> <bill.slo...@ieee.org> wrote:
> >> >On Oct 20, 3:58 pm, John Larkin
> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com>
> >> >> >wrote:
> >> >> >> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
> >> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >> >On Oct 19, 11:59 pm, Phil Hobbs
> >> >> >> ><pcdhSpamMeSensel...@electrooptical.net> wrote:
> >> >> >> >> BillSlomanwrote:
> >> >> >> >> > On Oct 19, 4:00 am, Phil Hobbs
> >> >> >> >> > <pcdhSpamMeSensel...@electrooptical.net> wrote:

<snip>

> >> It's bad enough that you make statements that are uninformed or wrong,
> >> but you have to phrase them as personal insults.
>
> >You do find personal insults where most people would merely find
> >colourful language.
>
> >> Your story about applying for work at ASML summarizes the situation:
> >> your are way to obnoxious for your own good.
>
> >I upset the personal department by going behind their backs to talk to
> >an engineer that I'd been interviewed by earlier. Personnel
> >departments aren't good at evaluating engineers. Good ones know it and
> >don't get too upset about being by-passed. Bad ones know it too but
> >hate being reminded that they aren't as clever as they like to think.
> >At ASML it looks as if the guy in charge was more interested in
> >defending his right to act as a gatekeeper than in getting the right
> >people through the gate.
>
> Sounds to me that he did his job very well.

It could be that Highland Technology Inc. has the same kind of
problem.

--
Bill Sloman, Sydney

[John Larkin]

Not hiring you is not a "problem", it's a joy.

[Michael A. Terrell]

Round the whole wide world...

[Bill Sloman]

On Oct 21, 3:58 pm, "Michael A. Terrell" <mike.terr...@earthlink.net>
wrote:
> John Larkin wrote:
>
> > On Sat, 20 Oct 2012 21:01:46 -0700 (PDT),BillSloman

A flattering misconception. Sci.electronics.design is unusually active
as user gropus go, but it's scarcely the whole world.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 21, 3:05 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sat, 20 Oct 2012 21:01:46 -0700 (PDT),BillSloman

Precisely. You are sacrificing potential long terms benenfits - very
potential in this case, granting your limited capacity to exploit
skills that might exceed your own - in favour of short term
gratification.

--
Bill Sloman, Sydney

[legg]

On Wed, 17 Oct 2012 16:20:09 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

<snip>
>Don't you love "worked fine up till yesterday" situations?
>
>One of my worst pranks was on a young engineer (EE, at
>OmniComp/GenRad)... he's fretting over a breadboard that "was working
>yesterday". He goes to lunch and I sit down at the bench with my
>OptiVisors...
>
> http://www.analog-innovations.com/SED/OptiVisorMonster.jpg
>
>and spot a solder bridge. I solder suck it up, and the breadboard
>works.
>
>When young engineer returns from lunch he's bewildered and pacing
>around, then testing, then pacing, then testing...
>
>To this day I've never told him... and it's been 27 years ;-)
>
> ...Jim Thompson

If I'd found you fiddling with someone else's work, undocumented,
there would have been fireworks. I know you think it's just a joke,
but it ain't.

RL

[Jim Thompson]

Cool it, Chester! I was the BOSS!

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[John Larkin]

On Sun, 21 Oct 2012 13:02:10 -0500, legg <le...@nospam.magma.ca> wrote:

He has a serious mean streak. And he has a much better memory for his
"pranks" that he has for, say, physics or thermo.

Personally, I detest sneaking practical jokers and gloating get-even
creeps. Cowards, both.

[Bill Sloman]

On Oct 22, 4:05 am, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
Web-Site.com> wrote:

> On Sun, 21 Oct 2012 13:02:10 -0500, legg <l...@nospam.magma.ca> wrote:
> >On Wed, 17 Oct 2012 16:20:09 -0700, Jim Thompson
> ><To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> wrote:
>
> ><snip>
> >>Don't you love "worked fine up till yesterday" situations?
>
> >>One of my worst pranks was on a young engineer (EE, at
> >>OmniComp/GenRad)... he's fretting over a breadboard that "was working
> >>yesterday".  He goes to lunch and I sit down at the bench with my
> >>OptiVisors...
>
> >>  http://www.analog-innovations.com/SED/OptiVisorMonster.jpg
>
> >>and spot a solder bridge.  I solder suck it up, and the breadboard
> >>works.
>
> >>When young engineer returns from lunch he's bewildered and pacing
> >>around, then testing, then pacing, then testing...
>
> >>To this day I've never told him... and it's been 27 years ;-)
>
> >>                                        ...Jim Thompson
>
> >If I'd found you fiddling with someone else's work, undocumented,
> >there would have been fireworks. I know you think it's just a joke,
> >but it ain't.
>
> >RL
>
> Cool it, Chester!  I was the BOSS!

One of my happier memories of working at EMI Central Research is of
having been intransigent enough that C.A.G. LeMay rejected me as his
project engineer for a particularly ill-conceived project.

One of his nastier habits was to settle down with the hardware after
work and fiddle with it, without documenting what he was doing. The
guy who got stuck with job I managed to evade had to get his engineers
together every morning and go through the hardware to find out what
C.A.G. LeMay had done and either correct it or document it. They
didn't always find everything.

It didn't matter in the long run - it was always a very silly idea -
but it did waste a lot of time.

--
Bill Sloman, Sydeney

[John Larkin]

Not hiring you has enduring benefits.

Seriously, you'd be poison here, or to most productive engineering
groups. You seem to have no genuine curiosity about electronics, no
creativity or humor (they go together), and you have the people skills
of a wolverine on a bad day.


--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

[Bill Sloman]

On Oct 22, 9:03 am, John Larkin <jlar...@highlandtechnology.com>
wrote:

> On Sun, 21 Oct 2012 03:45:18 -0700 (PDT), Bill Sloman
>
>
>

Strange idea. I've been a member of a couple of productive engineering
groups, and I've remained in contact with the one at EMI Central
Research (1976-79) ever since. I'm even linked to some of them on
LinkedIn.

>You seem to have no genuine curiosity about electronics,

A bizarre misconception. Even you should have enoguh sense to deduce
that this ins't true just from my posting patterns here - I don't
spend all my time (or even a substantial part of it) correcting your
misconceptions, though you are probably too emotionally involved to
credit this.

> no creativity or humor (they go together),

The patents do suggest that I do have some capacity for creative
thinking, and if you don't get my jokes your own sense of humour may
be the one at fault.

It's a while since I posted a joke that I really liked - like the one
in the thread "Op amp for division" back on April 11 1997 when I
claimed that

"It is with a certain measure of schadenfreude that we in Nijmegen
note
that Harvard's semi-automatous expert help system "Winfield Hill"
based
on Paul Horowitz's electronics textbook "The Art of Electronics" has
failed its extended Turing test."

but I do post intentionally comic stuff from time to time.

> and you have the people skills of a wolverine on a bad day.

A claim that would surprise a large number of people that I know.
Nobody has ever accused me of being good at flattery, which would seem
to be the only people skill that you actually value, but there's a
long gap between being direct and acting like a wolverine.

You would seem to be a perfect example of the kind of personnel
department which has absolute faith in their less-than-reliable
judgement.

--
Bill Sloman, Nijmegen

[John Larkin]

Little of which saw production. Engineering that doesn't result in
products is a waste of time and money.

and I've remained in contact with the one at EMI Central
>Research (1976-79) ever since. I'm even linked to some of them on
>LinkedIn.

LinkedIn is not productive.

>
>>You seem to have no genuine curiosity about electronics,
>
>A bizarre misconception. Even you should have enoguh sense to deduce
>that this ins't true just from my posting patterns here - I don't
>spend all my time (or even a substantial part of it) correcting your
>misconceptions, though you are probably too emotionally involved to
>credit this.

When I suggest things you might explore, you claim to be bored, or
demand to be paid to investigate.

>
>> no creativity or humor (they go together),
>
>The patents do suggest that I do have some capacity for creative
>thinking, and if you don't get my jokes your own sense of humour may
>be the one at fault.
>
>It's a while since I posted a joke that I really liked - like the one
>in the thread "Op amp for division" back on April 11 1997 when I
>claimed that
>
>"It is with a certain measure of schadenfreude that we in Nijmegen
>note
>that Harvard's semi-automatous expert help system "Winfield Hill"
>based
>on Paul Horowitz's electronics textbook "The Art of Electronics" has
>failed its extended Turing test."

That's the funniest you've been in 15 years?

>
>but I do post intentionally comic stuff from time to time.
>
>> and you have the people skills of a wolverine on a bad day.
>
>A claim that would surprise a large number of people that I know.
>Nobody has ever accused me of being good at flattery,

Or at getting people to hire you.

which would seem
>to be the only people skill that you actually value, but there's a
>long gap between being direct and acting like a wolverine.
>
>You would seem to be a perfect example of the kind of personnel
>department which has absolute faith in their less-than-reliable
>judgement.

I'm not a personnel department. My company doesn't even have one. And
I've hired lots of duds that looked pretty good at first. The trick is
to get rid of them if they turn out to be duds. Most of the good hires
here have been by informal contacts or by accident, not the
advertise-resume-interview routine, which usually doesn't work well. I
met my best engineer here on s.e.d. Our embedded programmer guy was
the lab partner of someone we knew who was in school. My business
manager is a lady I used to work on ships with, maintaining automation
systems, when I first came to California. My IT guy is the son of a
friend of my wife.

Luckily, California is a work-at-will state. We can lay off anyone at
any time for any reason, as they can quit any time they feel like it.
So if we don't have a mutually beneficial relationship, it ends.

[Tom Del Rosso]

Jim Thompson wrote:
>
> Thanks, Tom! I'll have to try that. Does it have deadband?

I didn't know what deadband refered to. Now I do, so the answer is I don't
know. I take it Treadway's 9-gate wonder did not? How can you ever know
without considering the output driver and filter characteristics?

My circuit is not 3-state, but at the time you asked for just an
edge-triggered set-reset flip flop. Since it's never hi-Z even when locked
I don't understand how it can have deadband. More jitter maybe since it
over-corrects, but not deadband. I hope you can clarify that for me.


--

Reply in group, but if emailing add one more
zero, and remove the last word.

[Phil Hobbs]

On 10/21/2012 9:32 PM, Tom Del Rosso wrote:
> Jim Thompson wrote:
>>
>> Thanks, Tom! I'll have to try that. Does it have deadband?
>
> I didn't know what deadband refered to. Now I do, so the answer is I don't
> know. I take it Treadway's 9-gate wonder did not? How can you ever know
> without considering the output driver and filter characteristics?
>
> My circuit is not 3-state, but at the time you asked for just an
> edge-triggered set-reset flip flop. Since it's never hi-Z even when locked
> I don't understand how it can have deadband. More jitter maybe since it
> over-corrects, but not deadband. I hope you can clarify that for me.
>
>

The deadband occurs where the phase difference is small enough that the
PD2 output pulse width is less than t_PHL + t_PLH. The output pulse
becomes a runt, and the phase detector gain K_phi drops to zero at zero
phase difference.

The competing approach, used e.g. by Motorola back in the day, uses two
separate outputs and subtracts them in analogue. That still has
nonlinearity, but (a) K_phi only drops by a factor of 2 when one of the
two pulses disappears, and, even more important, (b) the loop isn't
trying to make the PD sit right on the flat spot, the way it is in the 4046.

Unlike the HC4046's VCO, PD2 is easy to fix--you just put a resistor to
ground to pull it slightly off the flat spot. A few nanoseconds' worth
is enough.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net

[Bill Sloman]

On Oct 22, 10:41 am, John Larkin <jlar...@highlandtechnology.com>
wrote:

Perhaps. But I didn't get to chose which projects got funded - your
criticism is of U.K. engineering management, which wasn't all that
good, rather than of my competence as an engineer.

>  >and I've remained in contact with the one at EMI Central
> >Research (1976-79) ever since. I'm even linked to some of them on
> >LinkedIn.
>
> LinkedIn is not productive.

Sure. Whoever said it was? Apart from From LinkedIn, who want to make
money out of it ...

> >>You seem to have no genuine curiosity about electronics,
>
> >A bizarre misconception. Even you should have enoguh sense to deduce
> >that this ins't true just from my posting patterns here - I don't
> >spend all my time (or even a substantial part of it) correcting your
> >misconceptions, though you are probably too emotionally involved to
> >credit this.
>
> When I suggest things you might explore, you claim to be bored, or
> demand to be paid to investigate.

I'm going to do stuff for you for free? I may be curious, but I'm not
gullible.

> >> no creativity or humor (they go together),
>
> >The patents do suggest that I do have some capacity for creative
> >thinking, and if you don't get my jokes your own sense of humour may
> >be the one at fault.
>
> >It's a while since I posted a joke that I really liked - like the one
> >in the thread "Op amp for division" back on April 11 1997 when I
> >claimed that
>
> >"It is with a certain measure of schadenfreude that we in Nijmegen
> >note that Harvard's  semi-automatous expert help system "Winfield Hill"
> >based on Paul Horowitz's electronics textbook "The Art of Electronics" has
> >failed its extended Turing test."
>
> That's the funniest you've been in 15 years?

That's the one that sticks in my mind - perhaps because Winfield Hill
did find it funny. I'm not going to do a web search for additional
examples - that would be taking you much too seriously.

>
> >but I do post intentionally comic stuff from time to time.
>
> >> and you have the people skills of a wolverine on a bad day.
>
> >A claim that would surprise a large number of people that I know.
> >Nobody has ever accused me of being good at flattery,
>
> Or at getting people to hire you.

I did pretty well from 1969 to 1991. After I'd turned 49 there were
actual gaps between jobs - I'd become experienced and relatively
expensive. People skills generally improve with age, so you've got to
be hypothesising that I metamorphosed into a wolverine in my late
forties, which is implausible, even for you. In fact at that point I'd
become the social glue that held the Cambrdige Instruments electron
beam tester project together, which was unexpected, and used up half a
day a week that I'd have preferred to devote to circuit design and
debugging.

>
> >  which would seem
> >to be the only people skill that you actually value, but there's a
> >long gap between being direct and acting like a wolverine.
>
> >You would seem to be a perfect example of the kind of personnel
> >department which has absolute faith in their less-than-reliable
> >judgement.
>
> I'm not a personnel department. My company doesn't even have one.

But you do the selection and hiring, so you are the Highland
Electronics personnel department, as well as filling a number of other
functions. A jack of all trades, though you seem to have mastered
electronics, if not perhaps to the level of becoming a living national
treasure.

> And I've hired lots of duds that looked pretty good at first. The trick is
> to get rid of them if they turn out to be duds. Most of the good hires
> here have been by informal contacts or by accident, not the
> advertise-resume-interview routine, which usually doesn't work well.

You left out the "take up references" and/or talk to previous
employers part of the advertise-resume-inteview procedure. In the last
decade of my time in the UK I used to get a few phone calls a year
asking about people who had mentioned working with me to prospective
employers.

> I
> met my best engineer here on s.e.d. Our embedded programmer guy was
> the lab partner of someone we knew who was in school. My business
> manager is a lady I used to work on ships with, maintaining automation
> systems, when I first came to California. My IT guy is the son of a
> friend of my wife.

Which is to say you really haven't mastered the advertise/read resume/
interview routine which allows you to access a rather bigger pool of
candidates.

> Luckily, California is a work-at-will state. We can lay off anyone at
> any time for any reason, as they can quit any time they feel like it.
> So if we don't have a mutually beneficial relationship, it ends.

So your limited skills in personnel selection aren't actually lethal.

--
Bill Sloman, Sydney

[Bill Sloman]

On Oct 22, 12:40 pm, Phil Hobbs

<pcdhSpamMeSensel...@electrooptical.net> wrote:
> On 10/21/2012 9:32 PM, Tom Del Rosso wrote:> Jim Thompson wrote:
>
> >> Thanks, Tom!  I'll have to try that.  Does it have deadband?
>
> > I didn't know what deadband refered to.  Now I do, so the answer is I don't
> > know.  I take it Treadway's 9-gate wonder did not?  How can you ever know
> > without considering the output driver and filter characteristics?
>
> > My circuit is not 3-state, but at the time you asked for just an
> > edge-triggered set-reset flip flop.  Since it's never hi-Z even when locked
> > I don't understand how it can have deadband.  More jitter maybe since it
> > over-corrects, but not deadband.  I hope you can clarify that for me.
>
> The deadband occurs where the phase difference is small enough that the
> PD2 output pulse width is less than t_PHL + t_PLH.  The output pulse
> becomes a runt, and the phase detector gain K_phi drops to zero at zero
> phase difference.
>
> The competing approach, used e.g. by Motorola back in the day, uses two
> separate outputs and subtracts them in analogue.  That still has
> nonlinearity, but (a) K_phi only drops by a factor of 2 when one of the
> two pulses disappears, and, even more important, (b) the loop isn't
> trying to make the PD sit right on the flat spot, the way it is in the 4046.
>
> Unlike the HC4046's VCO, PD2 is easy to fix--you just put a resistor to
> ground to pull it slightly off the flat spot.  A few nanoseconds' worth
> is enough.

The NXP 9046 uses a different solution again - current sources rather
than logic levels

http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf


The VCO is still nasty, but PC2 is well-behaved.

--
Bill Sloman, Sydney

[Phil Hobbs]

Yup, it's better, but it just saves you a single resistor and costs at
least a buck more. The 4046 PD2's flat spot is a minor wart if you know
about it, but it can be a real puzzler otherwise--superficially the loop
looks well-behaved, but it hunts back and forth by a few nanoseconds.

[John Larkin]

1. I didn't suggest that you do things that I need. I suggested that
you do things that might help *you* find useful something to do, maybe
even find work.

2. If you want someone to hire you, as a consultant or as an employer,
it's really good if you convince them that you are willing to work in
their interest. Learning their application and science, or offering a
freebie to start, is very good business. Sounding greedy and arrogant
and bored isn't.

Hey, it's your life; live it your way.

[Bill Sloman]

On Oct 23, 6:25 am, John Larkin <jlar...@highlandtechnology.com>
wrote:

> On Sun, 21 Oct 2012 19:01:15 -0700 (PDT), Bill Sloman
>
>
>

So you claim.

> I suggested that you do things that might help *you* find useful something
> to do, maybe even find work.

Very altruistic of you. Your grasp of the demands of the Dutch (and
now the Australia) job market for engineers may be better than mine,
since all I know about that subject is what I read in the local job
ads, but none of your suggestions has looked all that useful to me.

> 2. If you want someone to hire you, as a consultant or as an employer,
> it's really good if you convince them that you are willing to work in
> their interest. Learning their application and science, or offering a
> freebie to start, is very good business.

For them. Less so for me. I might do it if I knew a fair bit about the
people involved, and had good reason to think them honest, but I've
got better things to do with my time than jumping through hoops in the
vague hope of beong considered for a particular job. Not all that much
better, perhaps, but still better than that.

>Sounding greedy and arrogant and bored isn't.

Any more that sounding vain, petulant, and self-obsessed makes one
look attractive as an employer.

Wanting to get paid for doing a specific task isn't exactly greedy -
nobody values stuff they get for nothing, and people who don't have to
pay for work tend to be frivolous about expanding the scope of the
task. I'm certainly bored by a lot of the discussion that goes on here
- a lot of it is old errors being recycled by people who can't get
their heads around the fact that they might be wrong - and pointing
this out does make me sound arrogant. It's problem that all competent
people have to live with. I'd have thought that you might have run
into it from time to time, if you real-world competence came anywhere
near your self-image.

> Hey, it's your life; live it your way.

Such a generous concession.

--
Bill Sloman, Sydney