1ns max jitter oscillator, cheap - for fast 4 diode sampler

[klaus.k...@gmail.com]

Hi

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)

So I need a pretty good oscillator, with low jitter

I have never needed a good oscillator before, so on this topic I am totally at square one

First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.

In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)

But jitter is not listed as a search parameter. So where to start? (with low price in mind)

Cheers

Klaus

[bill....@ieee.org]

This isn't a low price solution, but etched crystals were commercially available to up to about 600MHz, and the jitter on their output was less than a picosecond.

Some twenty years ago I was planning on buying in a crystal oscillator that ran at 500MHz with ECL outputs, for about 100 euro.

Today's parts are more widely available and appear to go up to 2.1GHz

https://uk.farnell.com/abracon/ax5pbf1-500-0000c/oscillator-500mhz-lvpecl-5mm-x/dp/2986239

http://www.farnell.com/datasheets/2713167.pdf

They seem to have gotten cheaper too.

Still not cheap.

--
Bill Sloman, Sydney

[Phil Hobbs]

A standard XO is nowhere near as bad as 1 ns. That would be half a
radian worth at 100 MHz.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[John Larkin]

On Tue, 7 May 2019 07:14:33 -0700 (PDT), klaus.k...@gmail.com
wrote:

Do you want a continuous running oscillator, namely a crystal
oscillator? That works if the measured event and the sampler timebase
can run off the same clock. Even cheap XOs have picosecond or
sub-picosecond jitter measured over short time spans. Longer spans are
trashed by low frequency phase noise, numbers in the nanoseconds per
second for cheap XOs, picoseconds per second for good OCXOs.

Most XOs now have a jitter spec on their data sheet. Some spec
femtosecond period jitter.

Sampling oscilloscopes typically need async triggered timebase
oscillators, which are more difficult. Jitters like 1 part in 50,000
(jitter 20 PPM RMS times timed delay) are more common for a triggered
LC, like on an 11801. 1 part per million is possible; I'm doing that
now.

A triggered oscillator can be phase locked to a good XO while
preserving the trigger alignment.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Cursitor Doom]

On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

> Hi
>
> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.




--
This message may be freely reproduced without limit or charge only via
the Usenet protocol. Reproduction in whole or part through other
protocols, whether for profit or not, is conditional upon a charge of
GBP10.00 per reproduction. Publication in this manner via non-Usenet
protocols constitutes acceptance of this condition.

[Gerhard Hoffmann]

Am 07.05.19 um 19:20 schrieb Cursitor Doom:

> I know I'll appear a dinosaur by saying this, but you really can't beat a
> good old fashioned Wien Bridge oscillator when it comes to spectral
> purity and low phase noise. They certainly beat the crap out of any
> digital synthesis technique IMV.
>
>

ROTFL.

A Q like a wet sand bag.

[Tom Gardner]

On 07/05/19 18:20, Cursitor Doom wrote:
> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>
>> Hi
>>
>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>
> I know I'll appear a dinosaur by saying this, but you really can't beat a
> good old fashioned Wien Bridge oscillator when it comes to spectral
> purity and low phase noise. They certainly beat the crap out of any
> digital synthesis technique IMV.

No, but that statement is about as sensible as almost
all your statements.

[Winfield Hill]

Tom Gardner wrote...

Yes, I would have gone for a crystal, or at least a
high-Q LC oscillator.


--
Thanks,
- Win

[bitrex]

On 5/7/19 1:20 PM, Cursitor Doom wrote:
> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>
>> Hi
>>
>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>
> I know I'll appear a dinosaur by saying this, but you really can't beat a
> good old fashioned Wien Bridge oscillator when it comes to spectral
> purity and low phase noise. They certainly beat the crap out of any
> digital synthesis technique IMV.
>
>
>
>

In a rare moment of partial agreement with my arch-nemesis "Cursitor
Doom" an injecton-locked Wien bridge oscillator can provide a
near-perfect combination of very low phase noise and very low wideband
noise floor and distortion. And certainly meets the low-price requirement.

[bitrex]

He's right about the spectral purity and the phase noise can be cleaned
up by injection-locking it.

[klaus.k...@gmail.com]

On Tuesday, 7 May 2019 17:18:48 UTC+2, John Larkin wrote:
> On Tue, 7 May 2019 07:14:33 -0700 (PDT), klaus.k...@gmail.com
> wrote:
>
> >Hi
> >
> >I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
> >
> >So I need a pretty good oscillator, with low jitter
> >
> >I have never needed a good oscillator before, so on this topic I am totally at square one
> >
> >First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.
> >
> >In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)
> >
> >But jitter is not listed as a search parameter. So where to start? (with low price in mind)
> >
> >Cheers
> >
> >Klaus
>
> Do you want a continuous running oscillator, namely a crystal
> oscillator? That works if the measured event and the sampler timebase
> can run off the same clock. Even cheap XOs have picosecond or
> sub-picosecond jitter measured over short time spans. Longer spans are
> trashed by low frequency phase noise, numbers in the nanoseconds per
> second for cheap XOs, picoseconds per second for good OCXOs.
>

That is a very good point, great catch.

I will be using it in a TDR, so short pulse, and build up waveform for reflected pulse. Since I need up to 200m lenth, the maximum time from the emitted pulse to reflected is 3us. So if the jitter is slowly changing over time, it may be a lot less in only that time span.

I do not know the properties of crystal jitter. Would that be sinusoidal shaped?

> Most XOs now have a jitter spec on their data sheet. Some spec
> femtosecond period jitter.
>

I looked at Digikey. The cheapest XO (about 0.5 USD) has 3ps jitter:

https://www.sitime.com/datasheet/SiT8008

A lot better than what I need.

When looking at oscillators, the cheapest (0.4 USD) also has only 3ps:

https://www.sitime.com/datasheet/SiT2001

For crystals, I see no spec of jitter:

https://abracon.com/Resonators/abls.pdf

But, I guess that is because that makes no sense if the inverter used for the crystal is defined. For microcontrollers I never see a spec for the jitter, maybe it is horrendous

I have seen jitter defined for the PLL. For example for a ST controller:

https://www.st.com/resource/en/datasheet/stm32g071cb.pdf

Page 76, defines 40ps jitter. Cannot see if that is from RC or crystal clock. But is most likely crystal clock. So it seems, I can use a cheap crystal for the microontroller and get a sufficient low jitter figure

> Sampling oscilloscopes typically need async triggered timebase
> oscillators, which are more difficult. Jitters like 1 part in 50,000
> (jitter 20 PPM RMS times timed delay) are more common for a triggered
> LC, like on an 11801. 1 part per million is possible; I'm doing that
> now.
>
> A triggered oscillator can be phase locked to a good XO while
> preserving the trigger alignment.
>
>

Thanks for the very good info

Regards

Klaus

[klaus.k...@gmail.com]

On Tuesday, 7 May 2019 19:20:49 UTC+2, Cursitor Doom wrote:
> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>
> > Hi
> >
> > I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>
> I know I'll appear a dinosaur by saying this, but you really can't beat a
> good old fashioned Wien Bridge oscillator when it comes to spectral
> purity and low phase noise. They certainly beat the crap out of any
> digital synthesis technique IMV.
>
>

So I could use a Wien Bridge oscillator, or a cheap colpits?

Then use the cheap crystal osc in the microcontroller to compensate the measurements (measure the colpits frequency and correct the numbers)

Cheers

Klaus

[klaus.k...@gmail.com]

How do you clean up the oscillator by injection? Got an example?

Cheers

Klaus

[George Herold]

Hmm, Well I know little of phase noise, but if it's at all related to
harmonic distortion... Then I will say I've built a little Wien bridge
oscillator (audio) with light bulb AGC (ala Jim Williams, ala Bill Hewlett)
And it's slick. The 2nd harmonic is hard to see without fancy kit and
the 3rd harmonic is ~70 dB down. Which is better than my Rigol DDS
Sig Gen. (about -70 dB 2nd and -60 on 3rd)

I'm not sure my objection has anything to do with ns phase noise.

George H.

[George Herold]

Yeah me too. Curious minds want to know.
In my very limited experience, the spectral purity depended on
how 'strong' the AGC was.

George H.
>
> Cheers
>
> Klaus

[George Herold]

This maybe.
https://www.analog.com/en/technical-articles/injection-lock-a-wien-bridge-oscillator.html

GH

[George Herold]

OK last thing. I stuck my Wien bridge on the good SRS 720 spectrum analyzer and the 3rd was ~90 db down. (my above 70 dB number was measuring on a 'scope, not so good.)

GH
FFT.)

[Jeroen Belleman]

While Wien bridge oscillators may have low distortion and therefore
good spectral purity, they certainly aren't low noise. I mean, even
the frequency-selective part is lossy, dissipative and therefore
noisy.

Jitter is the uncertainty in the timing of some level crossing.
This uncertainty depends on the noise level and on the rate of
change of the signal around that level crossing. To get low jitter,
you want the noise to be as low as possible and you want to cross
the decision level as fast as possible.

So you want a low-loss resonator, a low noise feedback amplifier,
high oscillation amplitude and high frequency. That pretty much
rules out a Wien bridge oscillator, or any RC oscillator for
that matter.

For timing a fast sampler, jitter performance doesn't need to
be stellar. It shouldn't be too hard to get jitter in the few
tens of picoseconds ballpark, even with an RC oscillator.

Jeroen Belleman

[klaus.k...@gmail.com]

That's the next thing. I need to find a scope that is good enough to measure the jitter. One of my work colleagues has one.

At home I have a TDS744A, which has 80ps jitter. So I can use that for rough measurements

[klaus.k...@gmail.com]

So for RC osc, I would need:

Good filtering on the waveform
Fast comparator with steady trigger treshold
Good PSSR
Circuit isolated from noise sources

Cheers

Klaus

[John Larkin]

On Tue, 7 May 2019 12:42:22 -0700 (PDT), klaus.k...@gmail.com
wrote:

>On Tuesday, 7 May 2019 17:18:48 UTC+2, John Larkin wrote:
>> On Tue, 7 May 2019 07:14:33 -0700 (PDT), klaus.k...@gmail.com
>> wrote:
>>
>> >Hi
>> >
>> >I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>> >
>> >So I need a pretty good oscillator, with low jitter
>> >
>> >I have never needed a good oscillator before, so on this topic I am totally at square one
>> >
>> >First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.
>> >
>> >In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)
>> >
>> >But jitter is not listed as a search parameter. So where to start? (with low price in mind)
>> >
>> >Cheers
>> >
>> >Klaus
>>
>> Do you want a continuous running oscillator, namely a crystal
>> oscillator? That works if the measured event and the sampler timebase
>> can run off the same clock. Even cheap XOs have picosecond or
>> sub-picosecond jitter measured over short time spans. Longer spans are
>> trashed by low frequency phase noise, numbers in the nanoseconds per
>> second for cheap XOs, picoseconds per second for good OCXOs.
>>
>That is a very good point, great catch.
>
>I will be using it in a TDR, so short pulse, and build up waveform for reflected pulse. Since I need up to 200m lenth, the maximum time from the emitted pulse to reflected is 3us. So if the jitter is slowly changing over time, it may be a lot less in only that time span.
>

The simplest timebase is a linear RC ramp and a comparator and a DAC,
no clock at all. RMS jitter of 1 part in 20,000 isn't difficult,
1:50000 is challenging. So 3 us/20000 would be 150 ps RMS jitter,
which is probably OK. The echo from 200m of coax will be very soft,
and you can average to reduce displayed jitter. Cheat a little.

You can switch the ramp capacitor or charging current to have a couple
of different delay ranges, and get less jitter on the short range.

A TDR can use the same clock for the launch pulse as for counting
coarse timebase delay, so an XO for coarse counts and a vernier ramp
for fine delays could hugely reduce sampling jitter. Like say, a 50
MHz clock followed by a 20 ns analog ramp.

>I do not know the properties of crystal jitter. Would that be sinusoidal shaped?
>
>> Most XOs now have a jitter spec on their data sheet. Some spec
>> femtosecond period jitter.
>>
>
>I looked at Digikey. The cheapest XO (about 0.5 USD) has 3ps jitter:
>
>https://www.sitime.com/datasheet/SiT8008
>
>A lot better than what I need.
>
>When looking at oscillators, the cheapest (0.4 USD) also has only 3ps:
>
>https://www.sitime.com/datasheet/SiT2001
>
>For crystals, I see no spec of jitter:
>
>https://abracon.com/Resonators/abls.pdf

Oscillators are so cheap, there's no point in buying bare crystals and
trying to make them oscillate.

>
>But, I guess that is because that makes no sense if the inverter used for the crystal is defined. For microcontrollers I never see a spec for the jitter, maybe it is horrendous
>
>I have seen jitter defined for the PLL. For example for a ST controller:
>
>https://www.st.com/resource/en/datasheet/stm32g071cb.pdf
>
>Page 76, defines 40ps jitter. Cannot see if that is from RC or crystal clock. But is most likely crystal clock. So it seems, I can use a cheap crystal for the microontroller and get a sufficient low jitter figure
>
>> Sampling oscilloscopes typically need async triggered timebase
>> oscillators, which are more difficult. Jitters like 1 part in 50,000
>> (jitter 20 PPM RMS times timed delay) are more common for a triggered
>> LC, like on an 11801. 1 part per million is possible; I'm doing that
>> now.
>>
>> A triggered oscillator can be phase locked to a good XO while
>> preserving the trigger alignment.
>>
>>
>Thanks for the very good info
>
>Regards
>
>Klaus

--

John Larkin Highland Technology, Inc

picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[John Larkin]

A sampler time base needs to stay phase coherent to a trigger.
Injection locking whacks randomly the phase. We care about time, not
frequency.

It is possible to build an instant-start LC oscillator, and phase-lock
it to a low phase noise XO, and preserve the original trigger timing
with picosecond precision, but I can't tell how.

But Klaus can do a totally synchronous system, for TDR, so doesn't
need a triggered oscillator. Could do a simple all analog ramp for the
timebase.

[John Larkin]

If Klaus needs an oscillator at all, he needs many MHz. A $3 quartz
crystal oscillator would have picosecond jitter. A Wein bridge
wouldn't be practical at that frequency and would have ghastly phase
noise.

[John Larkin]

On Tue, 7 May 2019 12:45:47 -0700 (PDT), klaus.k...@gmail.com
wrote:

>On Tuesday, 7 May 2019 19:20:49 UTC+2, Cursitor Doom wrote:
>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>
>> > Hi
>> >
>> > I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>>
>> I know I'll appear a dinosaur by saying this, but you really can't beat a
>> good old fashioned Wien Bridge oscillator when it comes to spectral
>> purity and low phase noise. They certainly beat the crap out of any
>> digital synthesis technique IMV.
>>
>>
>
>So I could use a Wien Bridge oscillator, or a cheap colpits?

No, NO! Buy a cheap cmos crystal oscillator with a suitable jitter
spec.

[klaus.k...@gmail.com]

I was actually going the digital way

Clean clock to drive the microcontroller that generates the TDR pulse with a HR timer

The microcontroller has picosecond timing

https://www.st.com/resource/en/datasheet/stm32f334k6.pdf

Page 80, 217ps

I will let that HR timer trigger the 4 diode sampler, then use slow aquisition to sample and store for later analysis


But, your way may be cheaper

Cheers

Klaus

[klaus.k...@gmail.com]

That would then be a little sensitive to the DAC noise, which would cause jitter directly. But that DAC signal can be heavily filtered

I would need a linear ramp then. But in other threads you have shown more or less how that can be done

>
> You can switch the ramp capacitor or charging current to have a couple
> of different delay ranges, and get less jitter on the short range.
>
> A TDR can use the same clock for the launch pulse as for counting
> coarse timebase delay, so an XO for coarse counts and a vernier ramp
> for fine delays could hugely reduce sampling jitter. Like say, a 50
> MHz clock followed by a 20 ns analog ramp.
>
>

That is sort of how they are doing the ps timebase. They use a standard timer (16 bit or whatever), max clock of 144MHz (7ns resolution). Then they add a delay line, to generate the 217ps smaller intervals

Cheers

Klaus

[whit3rd]

On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

> > I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)

[and want a low-jitter oscillator]

> I know I'll appear a dinosaur by saying this, but you really can't beat a
> good old fashioned Wien Bridge oscillator when it comes to spectral
> purity and low phase noise. They certainly beat the crap out of any
> digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> It is possible to build an instant-start LC oscillator, and phase-lock
> it to a low phase noise XO, and preserve the original trigger timing
> with picosecond precision, but I can't tell how.

"preserve the original trigger timing" <- compared to what?

[bitrex]

On 5/7/19 5:01 PM, John Larkin wrote:
> On Tue, 7 May 2019 15:37:52 -0400, bitrex <us...@example.net> wrote:
>
>> On 5/7/19 1:20 PM, Cursitor Doom wrote:
>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>>
>>>> Hi
>>>>
>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>>>
>>> I know I'll appear a dinosaur by saying this, but you really can't beat a
>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>> purity and low phase noise. They certainly beat the crap out of any
>>> digital synthesis technique IMV.
>>>
>>>
>>>
>>>
>>
>> In a rare moment of partial agreement with my arch-nemesis "Cursitor
>> Doom" an injecton-locked Wien bridge oscillator can provide a
>> near-perfect combination of very low phase noise and very low wideband
>> noise floor and distortion. And certainly meets the low-price requirement.
>
> If Klaus needs an oscillator at all, he needs many MHz. A $3 quartz
> crystal oscillator would have picosecond jitter. A Wein bridge
> wouldn't be practical at that frequency and would have ghastly phase
> noise.
>
>

Sometimes folks assume we're all intimately familiar with the
requirements of the projects they're working on ("I'm working on my...")
sadly I'm not, sure would make my life easier if that crystal ball were
up and running. Not even sure if requirement is sine or square.

Analog Devices likes the injection-locked Wien bridge for low phase
noise, low distortion sines but at say, 10kHz. Down there the
performance of that lash-up does look amazing.

[klaus.k...@gmail.com]

There's another thread about a 1ns sampling stage which details that I am working on a ns sample hold, that will be used for a cheap TDR function

https://groups.google.com/forum/#!topic/sci.electronics.design/Rzeziuv-4q8

Cheers

Klaus

[John Larkin]

Like this:

https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0

That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.

[Gerhard Hoffmann]

Am 07.05.19 um 21:37 schrieb bitrex:

Alone the fact that you can easily injection lock a Wien bridge
oscillator is a sure sign that its frequency stability is not
of prime quality. And the absence of harmonics has nothing to do
with phase noise, as long as their amplitude is not that large
that it causes high order sideband mixdown to baseband. (noise present
around harmonics). You can have a square wave with excellent phase
noise.

Injection locking also does not solve any problem. If your injection
source is so good, why not use it directly, without all of this ado?

And if you look at the Leeson equation that defines the phase noise
of an oscillator, there is a division term of (2 * Q**2), so Q is one
of the most important parameters. In practical oscillators that can be
even stronger than **2, depending on offset. The Leeson formula is
somewhat simplified. Rohde, Rubiola and others have improved on that.

Remember that the phase slope of the loop gain is effective Q.
dphase/dfreq of a Wien bridge is, oh, ask LTspice. The wet sand bag.
Good is different. Oscillation frequency is where phase goes through 0,
so Q = dphase / dfreq at this frequency is that what counts.

Jitter is phase noise integrated over all frequencies of interest.
That works in the other direction, too, but there are more degrees
of freedom, i.e the noise distribution close to / far from the carrier.

And for telecom applications, the frequencies of interest do not
include anything below 12 KHz. That's how most stuff is specc'ed
because it gives better numbers. 1/f noise is ugly.

You probably cannot afford that luxury of neglecting 1/f because you
need absolute flight time, but if your laser link has GHz subcarriers,
then that's OK.

There is a German web site with a calculator: phase noise -- jitter
but here it's well after midnight, so I won't search it now.
Maybe tomorrow.

As I wrote more than once here: timenuts group at febo.com,
and www.rubiola.org

The HP 54750A scope contains a time stretcher (dual slope: charge fast,
discharge slowly). It has been described in HP Journal.
It is even 2-stage to get more traces per second.
I must admit that I love that scope. And everybody should have the
HP journals in their vault.

This dual slope procedure is not uncommon. I have done something similar
to compare a hydrogen maser and a cesium. 5 ps resolution with
somewhat worse accuracy have been reached at many places. That's
about what a Stanford 620 time interval counter delivers. Good instrument.

cheers, Gerhard


...and its a Wien bridge, not Wein. Also, it's not Seimens.
The creator of the bridge was Wien by name; he has his name
probably from the the town called Vienna abroad. Also the sausages are
not Weiners but Wieners, even if from Oscar Mayer; but methinks in
Vienna they call them Frankfurter.

I wished I was an Oscar Meyer Weiner, because if I was an Oscar Meyer
weiner, everybody would love me.

[Gunther Heiko Hagen]

On Wed, 08 May 2019 01:30:48 +0200, Gerhard Hoffmann wrote:

> ...and its a Wien bridge, not Wein. Also, it's not Seimens.
> The creator of the bridge was Wien by name; he has his name probably
> from the the town called Vienna abroad. Also the sausages are not
> Weiners but Wieners, even if from Oscar Mayer; but methinks in Vienna
> they call them Frankfurter.

You're showing your misunderstanding of Wurst is only eclipsed by your
misunderstanding of electronics.

> I wished I was an Oscar Meyer Weiner, because if I was an Oscar Meyer
> weiner, everybody would love me.

Dream on.

[bitrex]

On 5/7/19 4:57 PM, John Larkin wrote:
> On Tue, 7 May 2019 15:39:04 -0400, bitrex <us...@example.net> wrote:
>
>> On 5/7/19 3:08 PM, Tom Gardner wrote:
>>> On 07/05/19 18:20, Cursitor Doom wrote:
>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>>>
>>>>> Hi
>>>>>
>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>>>>
>>>> I know I'll appear a dinosaur by saying this, but you really can't beat a
>>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>>> purity and low phase noise. They certainly beat the crap out of any
>>>> digital synthesis technique IMV.
>>>
>>> No, but that statement is about as sensible as almost
>>> all your statements.
>>
>> He's right about the spectral purity and the phase noise can be cleaned
>> up by injection-locking it.
>
> A sampler time base needs to stay phase coherent to a trigger.
> Injection locking whacks randomly the phase. We care about time, not
> frequency.
>
> It is possible to build an instant-start LC oscillator, and phase-lock
> it to a low phase noise XO, and preserve the original trigger timing
> with picosecond precision, but I can't tell how.
>
> But Klaus can do a totally synchronous system, for TDR, so doesn't
> need a triggered oscillator. Could do a simple all analog ramp for the
> timebase.
>
>

It was entirely unclear to me whether OP was looking for a timebase
oscillator or a test oscillator for the sampler! to measure the
performance of the sampler with a signal. I guess the part about RC
oscillator threw me - why would you use an RC oscillator for a sampling
timebase.....?????

In any case there's nothing intrinsically high phase noise about the
Wien bridge topology or injection locking. it all depends on the
implementation....

[bitrex]

There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact. Do they usually put inductors in ICs?

[Clifford Heath]

On 8/5/19 10:21 am, bitrex wrote:
> there's nothing intrinsically high phase noise about the
> Wien bridge topology or injection locking. it all depends on the
> implementation....

Injection of phase adjustments doesn't cause phase noise?
Tell us another joke, please...

[bitrex]

Are you hoping for -infinity dBc? No indeed you can't have that sorry

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <n...@spam.com> wrote:

>>John Larkin <jjlarkin@highland_snip_technology.com> wrote:

>>> It is possible to build an instant-start LC oscillator, and phase-lock
>>> it to a low phase noise XO, and preserve the original trigger timing
>>> with picosecond precision, but I can't tell how.

>>"preserve the original trigger timing" <- compared to what?

> Like this:

> https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0

> That oscillator starts instantly when an external trigger comes in,
> but it's phase locked to a crystal oscillator. The XO is at some
> random phase at trigger time. Injection locking would walk the
> triggered oscillator into phase with the XO, which we don't want.

So you count cycles until you reach the desired time, then start a fast ramp
to set the vernier delay. How you measure the vernier delay time?

[John Larkin]

On Tue, 7 May 2019 14:07:00 -0700 (PDT), klaus.k...@gmail.com

I'd be skeptical of the jitter. Resolution is cheap. A lot is going on
in a uP chip.

>
>I will let that HR timer trigger the 4 diode sampler, then use slow aquisition to sample and store for later analysis
>
>
>But, your way may be cheaper

Here's a cheap semi-linear ramp delay:

https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0

Making two ranges would't be hard. Switch the cap or the charging
current.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Clifford Heath]

Duh. But start with high Q (low phase noise, low resistance->Johnson
noise, LC not RC) and you need smaller kicks to injection lock. Varicap
tuning to reduce the frequency deviation would also allow smaller
injections - you could still use a phase detector to PLL the tuning.

[Steve Wilson]

John Larkin <jjla...@highlandtechnology.com> wrote:

> Here's a cheap semi-linear ramp delay:
>
> https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
>

Why not use a current source|

[Clifford Heath]

On 8/5/19 12:38 pm, John Larkin wrote:
> Here's a cheap semi-linear ramp delay:
> https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
> Making two ranges would't be hard. Switch the cap or the charging
> current.

Or just lower the charge voltage and linearise the exponential charge
curve in software. Longer delay -> less dV/dt -> less accurate.

[John Larkin]

In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.

We use a Keysight time interval counter to cal the ramps.

It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[John Larkin]

Resistors are cheap and very wideband. Fast precision current sources
are a real pain. The curvature is small, and a 2nd or 3rd order
polynomial onto the DAC data calibrates things nicely.

[bitrex]

I don't get where this idea come from that the Wien bridge topology is
intrinsically low Q. Is it because the open-loop RC network is?

The amplifier in the circuit is not just a power buffer to overcome loss
like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which
terminal the frequency-selective network is connected to, y'all.

[Bill Sloman]

On Wednesday, May 8, 2019 at 1:43:22 PM UTC+10, John Larkin wrote:
> On Wed, 08 May 2019 03:28:25 GMT, Steve Wilson <n...@spam.com> wrote:
>
> >John Larkin <jjla...@highlandtechnology.com> wrote:
> >
> >> Here's a cheap semi-linear ramp delay:
> >>
> >> https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
> >>
> >
> >Why not use a current source|
>
> Resistors are cheap and very wideband. Fast precision current sources
> are a real pain.

Precision might be, but running through a calibration procedure (which might take a millisecond, most of it devoted to engaging a microprocessor and turning it off again afterwards) every minute would let you get away with something cheap and practical.

> The curvature is small, and a 2nd or 3rd order
> polynomial onto the DAC data calibrates things nicely.

That's one approach. If you want to exploit the full precision of the DAC, a linear ramp makes best use of it.

--
Bill Sloman, Sydney

[whit3rd]

On Tuesday, May 7, 2019 at 4:07:03 PM UTC-7, John Larkin wrote:
> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <n...@spam.com> wrote:
>
> >John Larkin <jjlarkin@highland_snip_technology.com> wrote:
> >
> >> It is possible to build an instant-start LC oscillator, and phase-lock
> >> it to a low phase noise XO, and preserve the original trigger timing
> >> with picosecond precision, but I can't tell how.

> Like this:
>
> https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0
>
> That oscillator starts instantly when an external trigger comes in,
> but it's phase locked to a crystal oscillator. The XO is at some
> random phase at trigger time. Injection locking would walk the
> triggered oscillator into phase with the XO, which we don't want.

The asynchronous slick way to do that (we've discussed it in the past)
is with a sine/cosine quadrature master oscillator (which can be quartz-locked)
and track/hold amps that go into HOLD at the trigger time, with multiplier/summer circuitry.

sin(w*t -phi) = sin(w*t) cos(phi) - cos(w*t) sin(phi)
after you engage the HOLD, and
sin(w*t - w*t) = 0 = sin(w * t) cos(w * t) - cos(w * t) sin (w * t)
before (with the track/hold amplifiers tracking the sine and cosine
of the master clock).

Just like the picture, output goes from flat zero to full sinewave in an instant.

Gilbert cells and transformer adders can do the job at a wide range of frequencies.

[Steve Wilson]

That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?

[Clifford Heath]

Wien relies on the cancellation of two RC phase-shift networks.
Both the R's are noisy, so how can the result *not* be noisy?

In a good LC, the resistance is far less than 1% of the reactances.

[Bill Sloman]

Start a ramp at the trigger instant. Let it ramp up until the next clock edge but one, stop it, and digitise the static voltage that the ramp settled at.

Waiting for at least one clock interval gets past the mess as the ramp gets under way.

Back in 1990 we did it with an 800MHz clock and divided up the 1.25nsec clock into 10psec intervals.

It took about 40nsec for the digitised interval to come available, and we had to recalibrate the ramp generator every few minutes - one DAC set the ramp starting voltage, and another the ramp slope - but that took less than a millisecond.

The system had a pair of timing boards which could also generate edges timed to 10psec between clock edges which made self-calibration tolerably straight-forward.

--
Bill Sloman, Sydney

[Chris Jones]

On 08/05/2019 10:40, bitrex wrote:
> On 5/7/19 5:16 PM, whit3rd wrote:
>> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>
>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>> [and want a low-jitter oscillator]
>>
>>> I know I'll appear a dinosaur by saying this, but you really can't
>>> beat a
>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>> purity and low phase noise. They certainly beat the crap out of any
>>> digital synthesis technique IMV.
>>
>> The best timing performance requires significant stored energy,
>> if only for Heisenberg uncertainty principles.   That means LC beats RC
>> circuitry (the resistors don't store energy, they just waste it).   A
>> rock
>> has the full momentum of the standing wave acoustics, so a crystal is
>> better
>> than LC.   Short of maser/resonant cavity  references, the
>> possibilities are good
>> for plain old wires as delay lines (distributed L, C) also.
>>
>> World-class timing uses superconducting cavities, if that matters.
>>
>
> There's nothing intrinsic about the poor, besmirched Wien bridge
> oscillator topology that makes it intrinsically low Q,

Um do you know what Q is?

> intrinsically
> high phase noise, or any of these scurrilous accusations against it! And
> the topology is already used in ICs to generate accurate sampling
> clocks, as a matter-of-fact.

Which ones? I haven't seen it used on a chip.

> Do they usually put inductors in ICsThey don't usually put inductors in chips if it is not necessary,
because they are big, which means the chips use more area on the wafer
and cost more money to make. They do use inductors on chips,
begrudgingly, when they want a low phase-noise oscillator, because LC
oscillators have better phase noise than RC oscillators, and because
people will pay enough more money for this good phase noise performance
that it justifies the increased cost of the silicon that is occupied by
the big inductor. I have designed the local oscillator of a cellphone
radio chip, and yes it used an LC oscillator, like all of our
competitors also did.

It is difficult to convince people about things like phase noise,
because most people lack the equipment to measure it easily, and because
LTSpice won't simulate it. You need something a bit more spendy, like
SpectreRF.

I also find it impossible to convince people that their mixer won't work
better with a low-distortion sine wave LO signal than it would with a
nice sharp square wave LO. Again, hard to simulate the noise performance
properly with anything cheap, and the people who know how to measure it
are not the ones who need convincing.

[George Herold]

Thanks for that Gerhard... we love you anyway. :^)

George H. (who can never remember how to spell Wien.)

[George Herold]

On Tuesday, May 7, 2019 at 8:40:40 PM UTC-4, bitrex wrote:
> On 5/7/19 5:16 PM, whit3rd wrote:
> > On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
> >> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
> >
> >>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
> > [and want a low-jitter oscillator]
> >
> >> I know I'll appear a dinosaur by saying this, but you really can't beat a
> >> good old fashioned Wien Bridge oscillator when it comes to spectral
> >> purity and low phase noise. They certainly beat the crap out of any
> >> digital synthesis technique IMV.
> >
> > The best timing performance requires significant stored energy,
> > if only for Heisenberg uncertainty principles. That means LC beats RC
> > circuitry (the resistors don't store energy, they just waste it). A rock
> > has the full momentum of the standing wave acoustics, so a crystal is better
> > than LC. Short of maser/resonant cavity references, the possibilities are good
> > for plain old wires as delay lines (distributed L, C) also.
> >
> > World-class timing uses superconducting cavities, if that matters.
> >
>
> There's nothing intrinsic about the poor, besmirched Wien bridge
> oscillator topology that makes it intrinsically low Q,

Huh? There's no energy storage.. I haven't tried this, but if you turn
off the power, I'd guess the oscillations die away right away.
Low Q.
(I've used Wien bridge oscillators with diode AGC and they turn on
and off right away.)

George H.

[George Herold]

On Wednesday, May 8, 2019 at 12:12:51 AM UTC-4, bitrex wrote:
> On 5/7/19 11:00 PM, Clifford Heath wrote:
> > On 8/5/19 11:22 am, bitrex wrote:
> >> On 5/7/19 8:56 PM, Clifford Heath wrote:
> >>> On 8/5/19 10:21 am, bitrex wrote:
> >>>> there's nothing intrinsically high phase noise about the Wien bridge
> >>>> topology or injection locking. it all depends on the implementation....
> >>>
> >>> Injection of phase adjustments doesn't cause phase noise?
> >>> Tell us another joke, please...
> >>
> >> Are you hoping for -infinity dBc? No indeed you can't have that sorry
> >
> > Duh. But start with high Q (low phase noise, low resistance->Johnson
> > noise, LC not RC) and you need smaller kicks to injection lock. Varicap
> > tuning to reduce the frequency deviation would also allow smaller
> > injections - you could still use a phase detector to PLL the tuning.
>
> I don't get where this idea come from that the Wien bridge topology is
> intrinsically low Q. Is it because the open-loop RC network is?

Right, Q is a measure of energy storage. How much energy leaks out
of the oscillation amplitude during each cycle.

George H.

[Steve Wilson]

Steve Wilson <n...@spam.com> wrote:

>>>> That oscillator starts instantly when an external trigger comes in,
>>>> but it's phase locked to a crystal oscillator. The XO is at some
>>>> random phase at trigger time. Injection locking would walk the
>>>> triggered oscillator into phase with the XO, which we don't want.

>>>So you count cycles until you reach the desired time, then start a fast
>>>ramp to set the vernier delay. How you measure the vernier delay time?

>> In our products, we compute a polynomial at factory cal time to
>> linearize the dac codes going into the ramp comparator. The poly terms
>> go into a cal table. That's why we can use an RC instead of a current
>> source.

>> We use a Keysight time interval counter to cal the ramps.

>> It takes a bit of care to avoid "stitching errors", little hickies
>> every time we add one digital count and jump the ramp back down.

> That's not what I meant. When you start the LC oscillator, there is a
> random phase between the trigger and the XO. How do you measure that?

That question is probably going to come too close to the area you don't
want to talk about. How about a different approach.

Instead of trying to lock a pll to an oscillator at random phase, we could
measure to time between an asychronous trigger and an XO clock:

1. start a fast ramp at the trigger
2. find the delay to the second clock pulse from the XO
3. store this in a sample/hold or adc
4. count to the target delay minus 1 clock
5. start a fast ramp to the same delay time as the original

You now have the target delay locked to the XO but shifted in time

6. add the desired vernier delay to fill in between clock periods

There is the nasty problem of the trigger hitting exactly on a clock
transition, but that will occur with any asynchronous system. I am now
examining patents from Tektronix, LeCroy, HP/Agilent/Keysight to find out
how they handle the problem.

[John Larkin]

It's a weird digital PLL. A fast ADC is clocked based on the XO and
digitizes the triggered oscillator waveform. A mess of math in an FPGA
figures out the phase difference, does some PID control stuff, and
drives a DAC and a varicap to trim the LC oscillator. Lots of fun
signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.

HP did something similar ca 1970, but used a vernier heterodyne trick.
That takes longer to measure the difference and close the loop, and
jitter piles up until then.

There's a discussion of various digital delay generator architectures
in Wikipedia. I had to write it to get them to footnote my company
name; they insisted on a contribution of content.

[Bill Sloman]

That's why we waited for the third clock edge, or the second clock edge after the first clock edge that was actually after the trigger pulse had been detected and registered.

Nothing nasty about it, but it is one more delay (but nowhere near as long as the ramp sampling process)

That's what we did back in 1990. anyway, and it did work, even if the machine never went into production.

--
Bill Sloman, Sydney

[John Larkin]

Which ICs?

[bitrex]

Keep in mind that OP asked for "low cost" as well so it doesn't sound to
me like he was asking for a low phase noise 2GHz sampling clock - I'm no
expert or nothin' but I don't think anything about a system like that
would fit my own definition of "low cost."

While it may not be an appropriate solution for this particular project
my point was that CD made the Wien bridge suggestion and people jumped
down his throat like it was the dumbest idea in the world; my
counter-point was, not so fast, the Wien topology actually can be pretty
good with respect to phase noise. And at single or tens of MHz it
actually is used for low-jitter sampling clocks, to avoid using
impracticably large inductors or off-chip crystals.

In essence my contention is that while it might indeed be an
inappropriate choice for this particular project it isn't for the
reasons that were given.

[bitrex]

A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

<https://core.ac.uk/download/pdf/34451869.pdf>

<https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en>

A patent by Infinenon:

<https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf>

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

[John Larkin]

Do any actual chips do this?

We're using the LMX2571 frequency synthesizer chip, which has
phenomenal jitter performance. Like other new-generation synth chips,
it has multiple VCO cores inside, LC oscillators probably. The math is
mind-boggling.

[George Herold]

Can you see phase noise with a DSO by triggering on the oscillator and then
looking at the signal a long time later. And seeing how stable it is
wrt time.?

George H.

[bitrex]

Definitively? I cannot say for sure it's not like olden times where you
got a schematic with the data-sheet; IC mfgrs don't tell u SHIT without
an NDA not even the CPU core voltages of the new shit like in my post a
few moments ago.

I can only assume that if they patented it there's a decent chance it
will be or is being used for something. Not a guarantee sometimes they
just sit on them but it seems like a lot of work to pay a team for as
just a jerk-off exercise.

[Steve Wilson]

John Larkin <jjla...@highlandtechnology.com> wrote:

>>That's not what I meant. When you start the LC oscillator, there is a
>>random phase between the trigger and the XO. How do you measure that?
>
> It's a weird digital PLL. A fast ADC is clocked based on the XO and
> digitizes the triggered oscillator waveform. A mess of math in an FPGA
> figures out the phase difference, does some PID control stuff, and
> drives a DAC and a varicap to trim the LC oscillator. Lots of fun
> signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.

Excellent. Thanks

[John Larkin]

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

--

John Larkin Highland Technology, Inc

picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <n...@spam.com> wrote:
>>Excellent. Thanks

> The Pepper thing, where an analog ramp is suspended for some number of
> XO clocks, is magnificent. EG&G used to sell a DDG based on that.
> Theirs was a very bad implementation of a great idea, and the
> interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <n...@spam.com> wrote:

>>Excellent. Thanks

> The Pepper thing, where an analog ramp is suspended for some number of
> XO clocks, is magnificent. EG&G used to sell a DDG based on that.
> Theirs was a very bad implementation of a great idea, and the
> interrupted ramp thing has drift problems for long delays.

Any more info? All I get is Dr. pepper and pepper spray

[John Larkin]

It's referenced in the Wiki article, patent US4968907A. The patent is
hard to read, but basically he built a constant-current, linear analog
ramp delay generator to cover some modest time span, and suspended the
current for some integer number of XO clocks to add time. The async
suspensions add time but don't add clock jitter. Brilliant.

I had an understanding to license the patent, but decided to do the
triggered oscillator thing instead. It's better for long delays.

[klaus.k...@gmail.com]

Well, couldn't you add a PLL to boost the frequency to what is needed (in my case 144MHz). If the PLL phase noise if good enough that is

Cheers

Klaus

[klaus.k...@gmail.com]

On Wednesday, 8 May 2019 21:41:59 UTC+2, John Larkin wrote:
> On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <n...@spam.com> wrote:
>
> >John Larkin <jjlarkin@highland_snip_technology.com> wrote:
> >
> >> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <n...@spam.com> wrote:
> >>>Excellent. Thanks
> >
> >> The Pepper thing, where an analog ramp is suspended for some number of
> >> XO clocks, is magnificent. EG&G used to sell a DDG based on that.
> >> Theirs was a very bad implementation of a great idea, and the
> >> interrupted ramp thing has drift problems for long delays.
> >
> >Any more information? All I get is Dr. Pepper and pepper spray.
>
> It's referenced in the Wiki article, patent US4968907A.

I wasn't able to find the Wiki. Searched it for your name, but nothing popped up.

Cheers

Klaus

[bitrex]

Sounds like rapidly entering the territory of "not cheap." :-( but
higher-performance Wien bridges are a thing and might be interesting to
experiment with

[bitrex]

The literature seems to indicate they can't easily hit the phase-noise
performance of LC or crystal, but can beat ring oscillators or RC
relaxation oscillators.

There are finally only so many fundamental oscillator topologies and
variations on a theme; the Wien bridge I think is a gyrator-type where
positive feedback is used to boost a low-Q resonator network into
simulating a high-Q one.

[klaus.k...@gmail.com]

On Tuesday, 7 May 2019 22:50:59 UTC+2, John Larkin wrote:
> On Tue, 7 May 2019 12:42:22 -0700 (PDT), klaus.k...@gmail.com
> wrote:
>
> >On Tuesday, 7 May 2019 17:18:48 UTC+2, John Larkin wrote:
> >> On Tue, 7 May 2019 07:14:33 -0700 (PDT), klaus.k...@gmail.com
> >> wrote:
> >>
> >> >Hi

> >> >
> >> >I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
> >> >

> >> >So I need a pretty good oscillator, with low jitter
> >> >
> >> >I have never needed a good oscillator before, so on this topic I am totally at square one
> >> >
> >> >First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.
> >> >
> >> >In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)
> >> >
> >> >But jitter is not listed as a search parameter. So where to start? (with low price in mind)
> >> >
> >> >Cheers
> >> >
> >> >Klaus
> >>
> >> Do you want a continuous running oscillator, namely a crystal
> >> oscillator? That works if the measured event and the sampler timebase
> >> can run off the same clock. Even cheap XOs have picosecond or
> >> sub-picosecond jitter measured over short time spans. Longer spans are
> >> trashed by low frequency phase noise, numbers in the nanoseconds per
> >> second for cheap XOs, picoseconds per second for good OCXOs.
> >>
> >That is a very good point, great catch.
> >
> >I will be using it in a TDR, so short pulse, and build up waveform for reflected pulse. Since I need up to 200m lenth, the maximum time from the emitted pulse to reflected is 3us. So if the jitter is slowly changing over time, it may be a lot less in only that time span.
> >
>
> The simplest timebase is a linear RC ramp and a comparator and a DAC,
> no clock at all. RMS jitter of 1 part in 20,000 isn't difficult,
> 1:50000 is challenging. So 3 us/20000 would be 150 ps RMS jitter,
> which is probably OK. The echo from 200m of coax will be very soft,
> and you can average to reduce displayed jitter. Cheat a little.

In this case I need a fast comparator, sub ns response time. They cost over 2 USD which is a lot more expensive than a picosecond timing PWM microcontroller

Cheers

Klaus

[klaus.k...@gmail.com]

The PLL is the one onchip, inside the microcontroller

[George Herold]

This maybe,
https://en.wikipedia.org/wiki/Digital_delay_generator

GH

[Steve Wilson]

klaus.k...@gmail.com wrote:

> In this case I need a fast comparator, sub ns response time. They cost
> over 2 USD which is a lot more expensive than a picosecond timing PWM
> microcontroller

Where do you get one? any model numbers?

> Cheers

> Klaus

[klaus.k...@gmail.com]

https://www.st.com/resource/en/datasheet/stm32f334k6.pdf

[Gerhard Hoffmann]

Am 08.05.19 um 17:27 schrieb bitrex:

> On 5/8/19 11:15 AM, John Larkin wrote:
>> On Tue, 7 May 2019 20:40:35 -0400, bitrex <us...@example.net> wrote:
>>

>>> There's nothing intrinsic about the poor, besmirched Wien bridge
>>> oscillator topology that makes it intrinsically low Q, intrinsically
>>> high phase noise, or any of these scurrilous accusations against it! And
>>> the topology is already used in ICs to generate accurate sampling
>>> clocks, as a matter-of-fact.
>>
>> Which ICs?
>>
>
> A good number of papers in the literature about design of on-chip low
> phase noise Wien bridge clock oscillators:
>
> <https://core.ac.uk/download/pdf/34451869.pdf>

....

OK. The only one with hard numbers.

-73.7 dBc/Hz at 10 KHz offset from 5.something MHz carrier.

the cheapest 5 MHz XO I could find at Digikey in about 20 seconds:

-145 dBc / Hz at 10 KHz offset, or about 70 dB better.
This precision part costs 61.5 cents.

<
https://www.digikey.de/product-detail/de/ecs-inc/ECS-3225S33-050-EN-TR/ECS-3225S33-050-EN-TR-ND/6578872
>

< https://www.ecsxtal.com/store/pdf/ECS-3225S.pdf >

And into that 3.2 * 2.5 mm footprint they won't get much of a quality
crystal.

A 5MHz quality crystal would have a Q of > one million.
(or abt 100K @ 100 MHz; Q*f is abt. constant for comparable material.)



And the newfangled figure of merit: 172 dB for the Wien bridge oscillator.

For the current crop of Hittite, AD and TI synthesizers with on-chip
resonator I remember > 230 dB.

Forcing Wien bridges into the context of "accurate sampling clocks"
seems quite far-fetched.

> For clocks in the 100s of kHz to several MHz range the topology seems to
> have a lot of nice properties, since unless you want to use off-chip Ls
> or crystals your options are rather limited.

What offchip Ls or crystals do you need for that 61.5 ct. thing?


regards,
Gerhard

[Steve Wilson]

Thanks. And this thing sells for how much?

Do you have any information on the ultra fast comparators, such as risetime,
offset, delay time? There is nothing in the datasheet.

[klaus.k...@gmail.com]

On Wednesday, 8 May 2019 23:42:05 UTC+2, Steve Wilson wrote:
> klaus.k...@gmail.com wrote:
>
> > On Wednesday, 8 May 2019 22:37:36 UTC+2, Steve Wilson wrote:
> >> klaus.k...@gmail.com wrote:
> >>
> >> > In this case I need a fast comparator, sub ns response time. They cost
> >> > over 2 USD which is a lot more expensive than a picosecond timing PWM
> >> > microcontroller
> >>
> >> Where do you get one? any model numbers?
> >>
> > https://www.st.com/resource/en/datasheet/stm32f334k6.pdf
>
>
> Thanks. And this thing sells for how much?
>

Significantly below 2 USD (I cannot disclose the RFQ I have)

> Do you have any information on the ultra fast comparators, such as risetime,
> offset, delay time? There is nothing in the datasheet.

Comparator specs is on pgae 99

30ns, 5mV

Risetime is just an digital IO (5ns)

Cheers

Klaus

[Steve Wilson]

Thanks. I was searching for "ultra fast comparator" which is the term in
the title. I had no idea they would change the term.

> Cheers
>
> Klaus

[Clifford Heath]

Found it on my second search. Use this in Google (the quotes are important):

"pepper" "digital delay generator"

Clifford heath.

[Clifford Heath]

On 8/5/19 11:08 pm, George Herold wrote:
> On Tuesday, May 7, 2019 at 7:30:53 PM UTC-4, Gerhard Hoffmann wrote:
>> Am 07.05.19 um 21:37 schrieb bitrex:

>>> On 5/7/19 1:20 PM, Cursitor Doom wrote:
>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>>>

>>>>> Hi

>>>>>
>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>>>>

>>>> I know I'll appear a dinosaur by saying this, but you really can't beat a
>>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>>> purity and low phase noise. They certainly beat the crap out of any
>>>> digital synthesis technique IMV.
>>>>
>>>>
>>>>
>>>>
>>>

>>> In a rare moment of partial agreement with my arch-nemesis "Cursitor
>>> Doom" an injecton-locked Wien bridge oscillator can provide a
>>> near-perfect combination of very low phase noise and very low wideband
>>> noise floor and distortion. And certainly meets the low-price requirement.
>>
>> Alone the fact that you can easily injection lock a Wien bridge
>> oscillator is a sure sign that its frequency stability is not
>> of prime quality. And the absence of harmonics has nothing to do
>> with phase noise, as long as their amplitude is not that large
>> that it causes high order sideband mixdown to baseband. (noise present
>> around harmonics). You can have a square wave with excellent phase
>> noise.
>>
>> Injection locking also does not solve any problem. If your injection
>> source is so good, why not use it directly, without all of this ado?
>>
>> And if you look at the Leeson equation that defines the phase noise
>> of an oscillator, there is a division term of (2 * Q**2), so Q is one
>> of the most important parameters. In practical oscillators that can be
>> even stronger than **2, depending on offset. The Leeson formula is
>> somewhat simplified. Rohde, Rubiola and others have improved on that.
>>
>> Remember that the phase slope of the loop gain is effective Q.
>> dphase/dfreq of a Wien bridge is, oh, ask LTspice. The wet sand bag.
>> Good is different. Oscillation frequency is where phase goes through 0,
>> so Q = dphase / dfreq at this frequency is that what counts.
>>
>> Jitter is phase noise integrated over all frequencies of interest.
>> That works in the other direction, too, but there are more degrees
>> of freedom, i.e the noise distribution close to / far from the carrier.
>>
>> And for telecom applications, the frequencies of interest do not
>> include anything below 12 KHz. That's how most stuff is specc'ed
>> because it gives better numbers. 1/f noise is ugly.
>>
>> You probably cannot afford that luxury of neglecting 1/f because you
>> need absolute flight time, but if your laser link has GHz subcarriers,
>> then that's OK.
>>
>> There is a German web site with a calculator: phase noise -- jitter
>> but here it's well after midnight, so I won't search it now.
>> Maybe tomorrow.
>>
>> As I wrote more than once here: timenuts group at febo.com,
>> and www.rubiola.org
>>
>> The HP 54750A scope contains a time stretcher (dual slope: charge fast,
>> discharge slowly). It has been described in HP Journal.
>> It is even 2-stage to get more traces per second.
>> I must admit that I love that scope. And everybody should have the
>> HP journals in their vault.
>>
>> This dual slope procedure is not uncommon. I have done something similar
>> to compare a hydrogen maser and a cesium. 5 ps resolution with
>> somewhat worse accuracy have been reached at many places. That's
>> about what a Stanford 620 time interval counter delivers. Good instrument.
>>
>> cheers, Gerhard
>>
>>
>> ...and its a Wien bridge, not Wein. Also, it's not Seimens.
>> The creator of the bridge was Wien by name; he has his name
>> probably from the the town called Vienna abroad. Also the sausages are
>> not Weiners but Wieners, even if from Oscar Mayer; but methinks in
>> Vienna they call them Frankfurter.
>>
>> I wished I was an Oscar Meyer Weiner, because if I was an Oscar Meyer
>> weiner, everybody would love me.
>
> Thanks for that Gerhard... we love you anyway. :^)
>
> George H. (who can never remember how to spell Wien.)

I heard about a couple who drove all the way around Vienna twice on the
ring road looking for the exit to Vienna. They saw "Wien" signs on every
exit but thought that just mean "Exit". :)

BTW The rule of thumb in German for "ie" vs "ei": pronunciation follows
the *second* letter. "Ei" meaning "egg" is pronounced "I".

Clifford Heath.

[Clifford Heath]

On 9/5/19 6:10 am, bitrex wrote:
> ... but

> higher-performance Wien bridges are a thing and might be interesting to
> experiment with

The thing Wien bridges are good at is low-distortion audio sine waves.
All you need is clean AGC with a good time constant and you get very
nice sines.

[Chris Jones]

On 09/05/2019 01:16, bitrex wrote:
> On 5/8/19 8:10 AM, Chris Jones wrote:

>> On 08/05/2019 10:40, bitrex wrote:
>>> On 5/7/19 5:16 PM, whit3rd wrote:

>>>> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
>>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>>>
>>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)

>>>> [and want a low-jitter oscillator]
>>>>

>>>>> I know I'll appear a dinosaur by saying this, but you really can't
>>>>> beat a
>>>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>>>> purity and low phase noise. They certainly beat the crap out of any
>>>>> digital synthesis technique IMV.
>>>>

>>>> The best timing performance requires significant stored energy,
>>>> if only for Heisenberg uncertainty principles.   That means LC beats RC
>>>> circuitry (the resistors don't store energy, they just waste it).
>>>> A rock
>>>> has the full momentum of the standing wave acoustics, so a crystal
>>>> is better
>>>> than LC.   Short of maser/resonant cavity  references, the
>>>> possibilities are good
>>>> for plain old wires as delay lines (distributed L, C) also.
>>>>
>>>> World-class timing uses superconducting cavities, if that matters.
>>>>
>>>

>>> There's nothing intrinsic about the poor, besmirched Wien bridge
>>> oscillator topology that makes it intrinsically low Q,

>> Um do you know what Q is?

>>   > intrinsically
>>> high phase noise, or any of these scurrilous accusations against it!
>>> And the topology is already used in ICs to generate accurate sampling
>>> clocks, as a matter-of-fact.

>> Which ones? I haven't seen it used on a chip.
>>
>>> Do they usually put inductors in ICsThey don't usually put inductors
>>> in chips if it is not necessary,
>> because they are big, which means the chips use more area on the wafer
>> and cost more money to make. They do use inductors on chips,
>> begrudgingly, when they want a low phase-noise oscillator, because LC
>> oscillators have better phase noise than RC oscillators, and because
>> people will pay enough more money for this good phase noise
>> performance that it justifies the increased cost of the silicon that
>> is occupied by the big inductor. I have designed the local oscillator
>> of a cellphone radio chip, and yes it used an LC oscillator, like all
>> of our competitors also did.
>>
>> It is difficult to convince people about things like phase noise,
>> because most people lack the equipment to measure it easily, and
>> because LTSpice won't simulate it. You need something a bit more
>> spendy, like SpectreRF.
>>

>> I also find it impossible to convince people that their mixer won't
>> work better with a low-distortion sine wave LO signal than it would
>> with a nice sharp square wave LO. Again, hard to simulate the noise
>> performance properly with anything cheap, and the people who know how
>> to measure it are not the ones who need convincing.
>

> Keep in mind that OP asked for "low cost" as well so it doesn't sound to
> me like he was asking for a low phase noise 2GHz sampling clock - I'm no
> expert or nothin' but I don't think anything about a system like that
> would fit my own definition of "low cost."
Heh, cellphone chips are very much optimised for low cost. If you make a
billion of something, you will spend a lot of engineering effort and
other NRE, even just to shave 0.1 cents off that thing.

[Chris Jones]

You can see it like that, if there is so much of it that it is quite
bad, at offset frequencies related to the "long time later".

You can also see it directly with a spectrum analyser (provided that has
a much cleaner LO than what you are measuring). Sometimes it helps to
notch out the carrier (if you are only interested in noise at high
offsets). Note that with this method you will also see AM noise, which
might be useful or might be a distraction, as for example in a mixer LO
signal, the AM noise may be largely rejected by the mixer. **

You can buy a special instrument calles something like a "signal source
analyzer" from keysight, that does it.

There are a lot of cheaper methods which are tricky to do properly, e.g.
phase lock two oscillators together in quadrature and mix one with the
other, then you know the combined noise of the two oscillators. If one
of the oscillators is known to be very good, that is enough:
http://www.wenzel.com/documents/measuringphasenoise.htm
http://www.wenzel.com/documents/phasenoisemeasurement.htm
Otherwise, if you do that with all possible pairs from a set of 3
oscillators you can still get out the absolute phase noise.

Or you can mix an oscillator with itself, but with a long delay line in
one path. It's a long time since I have done it so I can't remember all
of the ways.

You might as well read all the notes on the Wenzel site, it has far
better information than what I can remember.

** There are a lot of ADI DDS chips that lack a pin to bypass the DAC
reference and these are said to have poor AM noise. Here is a page
showing some methods of investigating this as well as measuring phase noise:
https://martein.home.xs4all.nl/pa3ake/hmode/dds_ad9910_amnoise.html

[bitrex]

Yeah but you can use gajillions (technical term) of transistors all you
have to do is just draw them!

the cost rapidly increases when you not an IC designer and have to
kludge something together from off-the-shelf parts that don't really fit
the bill.

[bitrex]

On 5/8/19 5:03 PM, Gerhard Hoffmann wrote:

>> For clocks in the 100s of kHz to several MHz range the topology seems
>> to have a lot of nice properties, since unless you want to use
>> off-chip Ls or crystals your options are rather limited.
>
> What offchip Ls or crystals do you need for that 61.5 ct. thing?

The context of that sentence was for the use-case of IC design a la the
Infineon patent.

> regards,
> Gerhard

[bitrex]

My impression of the thrust of the papers I posted was that in
certain-use cases where you need tunability so a fixed-frequency crystal
osc is out, and don't want the added complexity of an LC VCO and/or PLL
frequency synthesizer, that the humble Wien actually isn't that bad for
generating a timebase. Not as good as the crystal or VCO, but better
than anything else.

[John Miles, KE5FX]

On Wednesday, May 8, 2019 at 7:38:01 AM UTC-7, John Larkin wrote:
> It's a weird digital PLL. A fast ADC is clocked based on the XO and
> digitizes the triggered oscillator waveform. A mess of math in an FPGA
> figures out the phase difference, does some PID control stuff, and
> drives a DAC and a varicap to trim the LC oscillator. Lots of fun
> signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.
>

I wonder what kind of precision you could get by simply hitting the
varactor with the trigger signal (or rather an amplitude-stabilized version
of it, such as the output of a fast comparator) and watching how the phase
difference changes over time. If the oscillators started out phase-locked
to each other before the trigger event came in, then their phase difference
would be an indication of how long ago the trigger happened.

There have been various hacks along those lines such as sending the trigger
through a SAW filter and measuring the phase of its ringdown waveform with
an ADC, but the one I'm thinking of was patented fairly recently.

-- john, KE5FX

[John Larkin]

On Wed, 8 May 2019 13:18:51 -0700 (PDT), klaus.k...@gmail.com

LVDS receivers make great fast RRIO comparators. We pay 55 cents for
SN65LVDS2DBVR.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Gerhard Hoffmann]

Am 09.05.19 um 04:50 schrieb John Miles, KE5FX:

> There have been various hacks along those lines such as sending the trigger
> through a SAW filter and measuring the phase of its ringdown waveform with
> an ADC, but the one I'm thinking of was patented fairly recently.
>
> -- john, KE5FX

Would that be Prof. Prochatzka from Prague?

73, Gerhard

[John Miles, KE5FX]

> Would that be Prof. Prochatzka from Prague?
>
> 73, Gerhard

Sounds familiar. I remember some Polish- or Czech-sounding names from their
poster session a few years back.

-- john, KE5FX

[John Larkin]

You could make a picosecond (or femtosecond) accurate time-interval
counter that way. Bang a resonator at an incoming trigger edge and
digitize the ringing waveform with an ADC, for a bunch of samples.
Curve fit to figure out the exact time that the ring started. ADC
noise and its clock jitter get averaged out.

Acoustic things like SAWs take forever to damp out, ring like a bell,
so can't be used at decently high rep rates. You can kill an LC or a
delay line dead in two cycles.

In my case, I want a fast clock that starts instantly at trigger time
and is trigger synchronous but crystal accurate. That's the goofy PLL.

[klaus.k...@gmail.com]

Yes, that is cheap (a bit slower than my requirements)

But how do you use it as a comparator, since it has large tolerances on the receiver thresholds (100mV)?

Regards

Klaus

[amal banerjee]

On Tuesday, May 7, 2019 at 7:44:39 PM UTC+5:30, klaus.k...@gmail.com wrote:
> Hi
>
> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>
> So I need a pretty good oscillator, with low jitter
>
> I have never needed a good oscillator before, so on this topic I am totally at square one
>
> First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.
>
> In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)
>
> But jitter is not listed as a search parameter. So where to start? (with low price in mind)
>
> Cheers
>
> Klaus

Have you considered a common emitter negative resistance oscillator using some RF|microwave transistor - HFA3134, BFR92A etc?

[Gerhard Hoffmann]

Am 09.05.19 um 05:10 schrieb John Miles, KE5FX:

https://www.researchgate.net/publication/231007282_Time_measurement_device_with_four_femtosecond_stability
>

But this was published in Sept. 2010, so that could not
be the background of a fresh patent.

I've met Prof. P. some years ago in his lab in Prague.
Seems like he knows what he's talking about. We had
an interface between his SPAD and my time stretcher
for measuring photon flight time.

cheers, Gerhard

[Gerhard Hoffmann]

Am 09.05.19 um 12:16 schrieb klaus.k...@gmail.com:

>> LVDS receivers make great fast RRIO comparators. We pay 55 cents for
>> SN65LVDS2DBVR.
>>
> Yes, that is cheap (a bit slower than my requirements)
>
> But how do you use it as a comparator, since it has large tolerances on the receiver thresholds (100mV)?

I had good results with AD8561 in that dual slope thing.
But beware of the bias current. It took a FET buffer or
it would have interfered with the slow discharge of the dual slope cap.


regards, Gerhard

[Phil Hobbs]

On 5/7/19 4:57 PM, John Larkin wrote:
> On Tue, 7 May 2019 15:39:04 -0400, bitrex <us...@example.net> wrote:
>
>> On 5/7/19 3:08 PM, Tom Gardner wrote:
>>> On 07/05/19 18:20, Cursitor Doom wrote:

>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
>>>>
>>>>> Hi
>>>>>
>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
>>>>

>>>> I know I'll appear a dinosaur by saying this, but you really can't beat a
>>>> good old fashioned Wien Bridge oscillator when it comes to spectral
>>>> purity and low phase noise. They certainly beat the crap out of any
>>>> digital synthesis technique IMV.
>>>

>>> No, but that statement is about as sensible as almost
>>> all your statements.
>>
>> He's right about the spectral purity and the phase noise can be cleaned
>> up by injection-locking it.
>
> A sampler time base needs to stay phase coherent to a trigger.
> Injection locking whacks randomly the phase. We care about time, not
> frequency.

Sinusoidal injection locking of sinusoidal oscillators is a lot gentler
than square wave injection.

>
> It is possible to build an instant-start LC oscillator, and phase-lock
> it to a low phase noise XO, and preserve the original trigger timing
> with picosecond precision, but I can't tell how.
>
> But Klaus can do a totally synchronous system, for TDR, so doesn't
> need a triggered oscillator. Could do a simple all analog ramp for the
> timebase.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[John Larkin]

On Thu, 9 May 2019 03:16:29 -0700 (PDT), klaus.k...@gmail.com

If you're doing a timing ramp, DC offset becomes time offset, and you
can cal that out. 1 ps RMS jitter and 1 ps delay resolution are
feasible with a reasonably fast ramp. The FIN1101, LVDS in and out, is
even better.

Somebody sells basically the same part, but they call it a comparator
and want $4 for it.