QFN32 vs. TQFP32
linnix
the old board, we have to use QFN64 due to the size. For the new
board, we might be able to use either QFN32 or TQFP32. QFN does not
offer much area savings, since we cannot route signals under the
ground pad. Can we run a via/trace on the channel between the ground
pad and outside pads? Any opinions?
John Larkin
If it passes your design rules, sure.
How many layers will you have?
John
linnix
2 layers, 60mmx10mm PCB. it's difficult to route all the signals on
the outside. For the QFN64 (5mmx5mm), we currently route some signals
on the channel (0.4mm) and the four corners. Vias would be very small
and more expensive. There are very little clearances between traces
and the ground pad. Soldermask is the only thing keeping them apart.
qrk
<m...@linnix.info-for.us> wrote:
Do the arithmetic. You'll have a gap between the outer pads and the
center pad of 20 to 25 mils. That means a via pad size of 15 to 10
mils if you use 5/5 rules.
If you have the space, easier to use a TQFP. You'll probably find the
TQFP saves space since you can pop vias under the part. Plus, much
easier to rework TQFPs.
Looking at my designs, looks like I avoid using QFN parts, choosing
BGA over QFN.
--
Mark
Nico Coesel
I usually have a ground and power plane underneath TQFP packages so I
try to avoid putting traces underneath a TQFP package.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
linnix
> linnix <m...@linnix.info-for.us> wrote:
> >We are redesigning a board with a 32 pins chip from a 64 pins. For
> >the old board, we have to use QFN64 due to the size. For the new
> >board, we might be able to use either QFN32 or TQFP32. QFN does not
> >offer much area savings, since we cannot route signals under the
> >ground pad. Can we run a via/trace on the channel between the ground
> >pad and outside pads? Any opinions?
>
> I usually have a ground and power plane underneath TQFP packages so I
> try to avoid putting traces underneath a TQFP package.
>
Well, 7mm (9mm peak to peak) TQFP does not leave much room on a 10mm
width board.
QFN has a big ground pad under the chip. We don''t really need the
thermo dissipation, and it limits traces and via under it. We had
about 10% burn through (during assembly) with traces under the ground
pad.
John Larkin
<m...@linnix.info-for.us> wrote:
>On Nov 29, 10:44�am, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> On Sun, 29 Nov 2009 09:38:29 -0800 (PST), linnix
>>
>> <m...@linnix.info-for.us> wrote:
>> >We are redesigning a board with a 32 pins chip from a 64 pins. �For
>> >the old board, we have to use QFN64 due to the size. �For the new
>> >board, we might be able to use either QFN32 or TQFP32. �QFN does not
>> >offer much area savings, since we cannot route signals under the
>> >ground pad. �Can we run a via/trace on the channel between the ground
>> >pad and outside pads? �Any opinions?
>>
>> If it passes your design rules, sure.
>>
>> How many layers will you have?
>>
>> John
>
>2 layers, 60mmx10mm PCB. it's difficult to route all the signals on
>the outside. For the QFN64 (5mmx5mm), we currently route some signals
>on the channel (0.4mm) and the four corners. Vias would be very small
>and more expensive. There are very little clearances between traces
>and the ground pad. Soldermask is the only thing keeping them apart.
Yikes, that sort of thing is hard to do on a 2-layer board.
John
-jg
> We had
> about 10% burn through (during assembly) with traces under the ground
> pad.
? What does that mean ?
Did you try to route traces under the PAD, and rely on the solder mask
to protect you ?!
If you read the fine print on many QFN packages,
they DO require that the inner PAD is soldered, I think there have
been issues with the very small outer pads giving way under the cyclic
stress
-jg
linnix
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sun, 29 Nov 2009 10:59:42 -0800 (PST), linnix
>
>
>
> <m...@linnix.info-for.us> wrote:
> >On Nov 29, 10:44 am, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Sun, 29 Nov 2009 09:38:29 -0800 (PST), linnix
>
> >> <m...@linnix.info-for.us> wrote:
> >> >We are redesigning a board with a 32 pins chip from a 64 pins. For
> >> >the old board, we have to use QFN64 due to the size. For the new
> >> >board, we might be able to use either QFN32 or TQFP32. QFN does not
> >> >offer much area savings, since we cannot route signals under the
> >> >ground pad. Can we run a via/trace on the channel between the ground
> >> >pad and outside pads? Any opinions?
>
> >> If it passes your design rules, sure.
>
> >> How many layers will you have?
>
> >> John
>
> >2 layers, 60mmx10mm PCB.
> it's difficult to route all the signals on
> >the outside. For the QFN64 (5mmx5mm), we currently route some signals
> >on the channel (0.4mm) and the four corners. Vias would be very small
> >and more expensive. There are very little clearances between traces
> >and the ground pad. Soldermask is the only thing keeping them apart.
Sorry, it's more like 90mmx15mm.
TQFP64 is 14mm
QFN64 is 10mm
TQFP32 is 7mm
QFN32 is 5mm
>
> Yikes, that sort of thing is hard to do on a 2-layer board.
Actually, it's doable on 2 layers. But without vias on the inside, we
are forced to do everything on top. And we want to keep cost low, so
0.3mm traces minimum.
>
> John
linnix
> On Nov 30, 10:06 am, linnix <m...@linnix.info-for.us> wrote:
>
> > We had
> > about 10% burn through (during assembly) with traces under the ground
> > pad.
>
> ? What does that mean ?
> Did you try to route traces under the PAD, and rely on the solder mask
> to protect you ?!
Yes, I did. I confess.
>
> If you read the fine print on many QFN packages,
> they DO require that the inner PAD is soldered, I think there have
> been issues with the very small outer pads giving way under the cyclic
> stress
I put in a smaller PCB pad and traces around it. This is just to get
by until we can change the design.
>
> -jg
linnix
> On Sun, 29 Nov 2009 09:38:29 -0800 (PST), linnix
>
> <m...@linnix.info-for.us> wrote:
> >We are redesigning a board with a 32 pins chip from a 64 pins. For
> >the old board, we have to use QFN64 due to the size. For the new
> >board, we might be able to use either QFN32 or TQFP32. QFN does not
> >offer much area savings, since we cannot route signals under the
> >ground pad. Can we run a via/trace on the channel between the ground
> >pad and outside pads? Any opinions?
>
> Do the arithmetic. You'll have a gap between the outer pads and the
> center pad of 20 to 25 mils. That means a via pad size of 15 to 10
> mils if you use 5/5 rules.
>
> If you have the space, easier to use a TQFP. You'll probably find the
> TQFP saves space since you can pop vias under the part. Plus, much
> easier to rework TQFPs.
Not possible with TQFP64, possible with TQFP32. But for TQFP32, we
need another chip to multiplex I/Os.
>
> Looking at my designs, looks like I avoid using QFN parts, choosing
> BGA over QFN.
No BGA available.
>
> --
> Mark
-jg
> On Nov 29, 1:27 pm, -jg <jim.granvi...@gmail.com> wrote:
>
> > On Nov 30, 10:06 am, linnix <m...@linnix.info-for.us> wrote:
>
> > > We had
> > > about 10% burn through (during assembly) with traces under the ground
> > > pad.
>
> > ? What does that mean ?
> > Did you try to route traces under the PAD, and rely on the solder mask
> > to protect you ?!
>
> Yes, I did. I confess.
>
Ouch!
If you _really_ have to do this, then you will need to pay more for
the solder-resist.
Get the best two-pot resist they have, and also ask about adding
glass beads - those can give a proven
finite gap. (used for gaping transformers)
- Of course, all of this adds costs....
-jg
linnix
I was thinking about adding epoxy on the edge of the ground pad. But
the added thickness makes it more difficult to solder the outer pads.
>
> - Of course, all of this adds costs....
It's a temporary solution. The boards work if it survives the
soldering process.
>
> -jg