Root Cause of FDC6303N FET drain and gate short circuit?
Myauk
In a typical PCBA design which consists of relay driver circuit, we
found the FET drain and gate short circuit problem causing damage to
MCU DIOs due to excessive sink current in production on 5 or 6 failed
out of 100 PCBA units.
Circuit Configuration is as follows:
The relay driver circuit consists of MCU DIO driving directly to the
gate of FDC6303N.
The Drain is connected to relay coil of internal resistance 86 ohms.
The realy is safely freewhelled with S1MB Diode.
The source is connected to ground.
The supply for the relay is 5V,
the MCU DIO is operating at 3.3V,
CMOS totempole output has maximum sinking current of 15mA.
The problem is obviously due to the shorted gate and drain of FDC6303N
however my questions here are,
1. Is it possible that there are defective FETs with alreadyshorted
gate and drain from the new lot of FETs catered for Production?
2. Or is there any possible fault condition which can cause a good
working FET to have gate and drain shorted?
Regards
Winfield Hill
>
> In a typical PCBA design which consists of relay driver circuit, we
> found the FET drain and gate short circuit problem causing damage to
> MCU DIOs due to excessive sink current in production on 5 or 6 failed
> out of 100 PCBA units.
> 2. Or is there any possible fault condition which can cause a good
> working FET to have gate and drain shorted?
Drain-to-gate shorts is a typical failure mode for power mosfets.
Amusingly, the mosfet is still probably operating properly, that
is it's operating the same as any other mosfet with its drain and
gate externally connected together. But I digress.
You want to know why the part failed. SFAIK, any of the various
overstress conditions can cause this type of failure. E.g.,
overheating, in any of the ways Rds(on), switching losses,
avalanche heating, or overvoltage. Including gate overvoltage,
which can happen if a high current is switched too fast, causing
high dI/dt, and a substantial source-wiring inductance, causing
high V = L dI/dt, which can be a short damaging gate-voltage spike.
Lot's of handwaving there, but the standard remedies apply, a diode
across the coil, a gate resistor to slow down switching speed, etc.
--
Thanks,
- Win
Myauk
wrote:
Thanks Win,
But I think it is not really a design issue. We have already added
freewheeling diode verifying the back emf is already eliminated by
checking the waveforms. And 10k Gate resistor is there. So there is no
way possibly to damage the FET.
Does anyone have similar experience?
Thanks and Best Regards
tm
"Myauk" <aungko...@gmail.com> wrote in message
news:cc5dfca7-d7fd-4f9d...@y32g2000prc.googlegroups.com...
On Jun 30, 9:38 pm, Winfield Hill <Winfield_mem...@newsguy.com>
wrote:
> Myauk wrote...
>
> > In a typical PCBA design which consists of relay driver circuit, we
> > found the FET drain and gate short circuit problem causing damage to
> > MCU DIOs due to excessive sink current in production on 5 or 6 failed
> > out of 100 PCBA units.
> > 2. Or is there any possible fault condition which can cause a good
> > working FET to have gate and drain shorted?
>
.But I think it is not really a design issue. We have already added
.freewheeling diode verifying the back emf is already eliminated by
.checking the waveforms. And 10k Gate resistor is there. So there is no
.way possibly to damage the FET.
.
.Does anyone have similar experience?
.
.Thanks and Best Regards
If you have a 10k gate resistor, how is it killing the DIO?
John Larkin
Wow. The fet is rated for 0.68 amps, 25 volts, and it's all zener
gate/ESD protected. You are running it at 5 volts and 60 mA. There's
no way it should fail.
Are they dead at turnon?
Are you buying the parts from an official distributor?
John
Myauk
>
> - Show quoted text -
They are already dead at turn on. We found it while we carried out the
relay circuit operation test, MCU reset issue while controlling relay
on/off.
Regards
Myauk
> "Myauk" <aungkokot...@gmail.com> wrote in message
Current from 5 V supply through relay is approximately 60mA sinking
into the LOW Dio pin rated at 15mA. (4 times the rated value).
tm
On Jun 30, 9:58 pm, "tm" <nob...@msnbc.org> wrote:
> "Myauk" <aungkokot...@gmail.com> wrote in message
>
> news:cc5dfca7-d7fd-4f9d...@y32g2000prc.googlegroups.com...
> On Jun 30, 9:38 pm, Winfield Hill <Winfield_mem...@newsguy.com>
> wrote:
>
> > Myauk wrote...
>
> > > In a typical PCBA design which consists of relay driver circuit, we
> > > found the FET drain and gate short circuit problem causing damage to
> > > MCU DIOs due to excessive sink current in production on 5 or 6 failed
> > > out of 100 PCBA units.
> > > 2. Or is there any possible fault condition which can cause a good
> > > working FET to have gate and drain shorted?
>
> .But I think it is not really a design issue. We have already added
> .freewheeling diode verifying the back emf is already eliminated by
> .checking the waveforms. And 10k Gate resistor is there. So there is no
> .way possibly to damage the FET.
> .
> .Does anyone have similar experience?
> .
> .Thanks and Best Regards
>
> If you have a 10k gate resistor, how is it killing the DIO?
.Current from 5 V supply through relay is approximately 60mA sinking
.into the LOW Dio pin rated at 15mA. (4 times the rated value).
Then there is something you are not telling us. From your two comments, you
say the
MCU DIO pin connects to the fet through a 10k resistor. If the fet shorts to
5 volts
(g to d), then the max current can be 0.5 mA. I=E/R= 5/10000=0.0005
Maybe you need to draw us a picture.
T
SoothSayer
<Winfiel...@newsguy.com> wrote:
I always noticed on year, when doing a huge amplifier design, which
contained a row of huge IGBTs and FETs on a 20 inch long sink, that we
had some odd failures early on in the design that had no reason for
being...
Early failure modes were tied to coplanarity issues on the sink. It
seems our assembler did not understand the concept of coplanarity until I
showed him the proper assembly sequence. Without it, it was as if any
part that did get attached right was not attached at all.
Anyway, we experienced plenty of what appeared to be "immediate"
failures due to the lack of a part being sinked properly. It was really
a matter of a few seconds. and went away once assembly efficacy was
achieved.
It seems that those thermal spikes were fast enough to take the part to
critical failure temperatures. Good heat sinking is REQUIRED, and that
right where it belongs... on the back of that tab!
SoothSayer
wrote:
>On Jun 30, 9:38 pm, Winfield Hill <Winfield_mem...@newsguy.com>
Do you have a thermal imager?
If not, you could rent one. Examine the device as you utilize it.
Watch the failure mode as it occurs and examine the waveforms during that
period to determine if it is circuit design related of heat management
related.
Make sure that your heat sink attachment has a high integrity thermal
pathway. Do not simply use a dry, "air" attachment. Make sure that it is
well sinked.
Once you rule out that, then get back to probing the circuit.
Have you ever used 'transzorbs', or put ferrite beads on the gate lead
during assembly? As close to the part as possible.
SoothSayer
wrote:
>Hi all,
>
>In a typical PCBA design which consists of relay driver circuit, we
>found the FET drain and gate short circuit problem causing damage to
>MCU DIOs due to excessive sink current in production on 5 or 6 failed
>out of 100 PCBA units.
>
>Circuit Configuration is as follows:
>
>The relay driver circuit consists of MCU DIO driving directly to the
>gate of FDC6303N.
>The Drain is connected to relay coil of internal resistance 86 ohms.
>The realy is safely freewhelled with S1MB Diode.
>The source is connected to ground.
>The supply for the relay is 5V,
>the MCU DIO is operating at 3.3V,
>CMOS totempole output has maximum sinking current of 15mA.
>
>The problem is obviously due to the shorted gate and drain of FDC6303N
>however my questions here are,
>
>1. Is it possible that there are defective FETs with alreadyshorted
>gate and drain from the new lot of FETs catered for Production?
If you cannot test each FET prior to assembly, you cannot blame the
lot. You *should* test a good "spc" like sample from what you buy, and
if more than a certain number fails, you reject the entire lot back to
the vendor.
If that level of testing is not feasible, then post-assembly testing
MUST be used to determine the failure mode in a NON-destructive way so
that the failed units can have that part trade out without causing any
proximal circuit failures, keeping the unit in the loop with less repair
requisite.
>2. Or is there any possible fault condition which can cause a good
>working FET to have gate and drain shorted?
Hand assembly, yes. Maintain strict ESD handling procedures.
Automated assembly, less likely. One must be careful to observe ESD
practices and procedures when loading the pick and place machine, AND
when receiving, inspecting, handling, stocking, and disbursement of the
parts as well.
ESD can cause prime pass yield problems that are hard to nail down.
Re-examine and strengthen your ESD policies and procedures where you may
need to.
SoothSayer
wrote:
>On Jun 30, 10:03 pm, John Larkin
Does your turn on test send a DC pulse? If so, how do you generate that
pulse?
Could it be a 'hard start' issue? In other words, make sure the DC you
send to the unit for your tests do not initiate at too high a slew rate.
A 'soft start' as the industry calls it.
I still think it may be an ESD issue, since the design works fine for
all the other units and the failed units are not circuit use failures,
but apparently failed devices prior to any use at all.
Myauk
10k resistor is the parallel pull down resistor between gate and
source of FET.
There is no resistance, the DIO directly drives the FET Gate.
Regards
Jan Panteltje
<aungko...@gmail.com> wrote in
<8df2da5f-1ece-4004...@s24g2000prs.googlegroups.com>:
>10k resistor is the parallel pull down resistor between gate and
>source of FET.
>
>There is no resistance, the DIO directly drives the FET Gate.
>
>Regards
Please note that it is not sufficient to just have the diode over the relay,
you ALSO must decouple the power rail at that point, else the drain will
spike way above the supply when the relay turns of, via the trace impedance
and whatever wires there are before you get the power supply.
And also add a small gate resistor *in series* please.
Sometimes a small (few nF) capacitor between drain and source can bring down
possible very high frequency oscillations that may also happen.
tm
.10k resistor is the parallel pull down resistor between gate and
.source of FET.
.
.There is no resistance, the DIO directly drives the FET Gate.
.
.Regards
I would at least put a small resistance, say 100 ohms or so, in series
with the gate to PIO pin. I'm not sure why you need the pull down as the
MCU should drive it ok. Unless the MCU three states the pin prior to
completing the reset. What bypassing are you using in the circuit? MCU?
Fet?
Regards,
T
Winfield Hill
>
> Winfield Hill wrote:
>> Myauk wrote...
>>
>>> In a typical PCBA design which consists of relay driver circuit,
>>> we found the FET drain and gate short circuit problem causing
>>> damage to MCU DIOs due to excessive sink current in production
>>> on 5 or 6 failed out of 100 PCBA units.
>>> 2. Or is there any possible fault condition which can cause a
>>> good working FET to have gate and drain shorted?
>>
>> Drain-to-gate shorts is a typical failure mode for power mosfets.
>>
>> Lot's of handwaving there, but the standard remedies apply, a diode
>> across the coil, a gate resistor to slow down switching speed, etc.
>
>
> But I think it is not really a design issue. We have already added
> freewheeling diode verifying the back emf is already eliminated by
> checking the waveforms. And 10k Gate resistor is there. So there
> is no way possibly to damage the FET.
Whoa! When I said, "a gate resistor to slow down switching speed"
I could not have meant a resistor to ground, how would that slow
the mosfet's switching speed? No, you may need a series resistor.
A 10k resistor to ground might make you feel comfortable, in case
the logic supply isn't present (could that happen?), but here I
was talking about an everyday series gate resistor. Maybe as high
as 470 to 1.8k or 3.3k or so, to slow your low-capacitance mosfet's
switching speed, and help it survive high-inductance PCB wiring.
Recall the damaging equations: high dI/dt ==> high V = L dI/dt.
The FDC6303N datasheet says Crss = 9pF. Assume a modest 50mA gate
drive from your processor, and we get dV/dt = I/C = 5.5V/ns, which
says your 5V 60mA relay current could shutoff in 1ns. Going back
to our equations, that would imply Vs = 60V for say 1uH of PCB
wiring inductance. OK, less for slower switching. Say 1/3 as
fast, that's still 20V on the source with the gate pinned, and
with an 8V max Vgs rating, 20V could certainly zap your gates.
And yes, that's a design problem.
I seriously doubt your mosfets would fail incoming inspection.
BTW, what are you doing with the FDC6303N's second mosfet?
--
Thanks,
- Win
Myauk
>
> - Show quoted text -
Thanks Win, sorry that I understand it wrongly. I am using both
MOSFETs for driving latching relay. One for ON coil, one for OFF coil.
Regards
Myauk
>
> - Show quoted text -
By the way, I have checked the rise time of the pulse to drive the
relay iwith scope. It is 37.6ns and the VGS rise is up to 3.82V only
at 3.3V dring singal to the FET. So it is safe to say that I won't
kill the FET as it is less than half of VGS rating 8V.
And checking turning on and turning off of the relay the VDS never
exceeds 5.8V.
This does not mean that I won't add the series resistor as I
understand that it will also prevent from excessive drain of current
into DIO of MCU in addition to slowing down the MOSFET switching
speed.
Special Thanks to you all on your suggestions and comments on this
topic.
Regards
Winfield Hill
>> wiring inductance. OK, less for slower switching. Say 1/3 as
>> fast, that's still 20V on the source with the gate pinned, and
>> with an 8V max Vgs rating, 20V could certainly zap your gates.
>> And yes, that's a design problem.
>>
>> I seriously doubt your mosfets would fail incoming inspection.
>>
>> BTW, what are you doing with the FDC6303N's second mosfet?
>
> relay iwith scope. It is 37.6ns and the VGS rise is up to 3.82V only
> kill the FET as it is less than half of VGS rating 8V.
Sorry, that's not the way it works. Yes of course your gate-
drive voltage is under 8V. And your risetime may not look fast,
but that includes the slow gnd-to-plateau, and plateau-to-Vcc
portions. It's during the short plateau when all the action
happens and drain voltage switches. Furthermore, what matters
is the true gate voltage, inside the die, hidden from you for
a short time on the far side of the gate spreading resistance.
And it's the source voltage that has the damaging spike, so
that the gate-to-source voltage Vgs exceeds 8V for an instant.
Being short, and internal to the mosfet, it's very hard to
probe fully. The best test for this effect is to see the
failures disappear after you slow down the drain's rise/fall
time by adding gate resistance.
But don't add too much resistance. At least for high-voltage
mosfets, above say 100V, if you switch too slowly, slower than
say 50 to 100ns, they can oscillate strongly at 8 to 20MHz,
involving the source inductance, and excess Vgs can damage
the mosfet. OK, perhaps that won't happen with your 25V part.
Once again, this isn't easy to probe. I've had success with
low-capacitance 500MHz probes. One of the big problems in
probing is the probe's ground return, which needs to be one
of those short (1/4") pieces of spring wire extending from
the probe's ground ring adjacent to the small sharp tip.
Done right, you're making a differential RF measurement. As
is often the case with these fast signals, exactly what are
you measuring, that's the question.
> And checking turning on and turning off of the relay the VDS
> never exceeds 5.8V.
>
> This does not mean that I won't add the series resistor as I
> understand that it will also prevent from excessive drain of
> current into DIO of MCU in addition to slowing down the MOSFET
> switching speed.
Yes, let us know what you learn.
> I am using both MOSFETs for driving latching relay. One
> for ON coil, one for OFF coil.
Is only one of the two mosfets failing?
BTW, for myself, I'd rather not use a wimpy 8V Vgs-rated
mosfet, unless I had to, and could take serious precautions.
I'd rather select a higher-voltage part and accept a little
higher Rds(on). Your FDC6303N is rated at 0.6 ohms max,
which is only 2.2mW max at 60mA. I mean, give me a break,
why not play it safe and let that bugger heat up a bit?
Like I said, these *are* design issues.
--
Thanks,
- Win
Myauk
Finally, we have decided to remove the relay part. So I have a good
chance to improve it and I will keep in mind of all your suggestions.
Thank you once again for the knowledge shared.
Regards
Myauk
> Sorry, that's not the way it works. Yes of course your gate-
> drive voltage is under 8V. And your risetime may not look fast,
> but that includes the slow gnd-to-plateau, and plateau-to-Vcc
> portions. It's during the short plateau when all the action
> happens and drain voltage switches.
I did see a plateau indeed. Is there any recommended source of
information where I can learn all the details?
Furthermore, what matters
> is the true gate voltage, inside the die, hidden from you for
> a short time on the far side of the gate spreading resistance.
>
> And it's the source voltage that has the damaging spike,
You mean the spike goes negative causing VGS to be higher?
> Is only one of the two mosfets failing?
Yes, only one of two MOSFETs have obvious failure. Gate to Drain low
resistance or short.
Regards
Winfield Hill
>
>> Sorry, that's not the way it works. Yes of course your gate-
>> drive voltage is under 8V. And your risetime may not look fast,
>> but that includes the slow gnd-to-plateau, and plateau-to-Vcc
>> portions. It's during the short plateau when all the action
>> happens and drain voltage switches.
>
> I did see a plateau indeed. Is there any recommended source
> of information where I can learn all the details?
There are a multitude of sources for information about FET
gate-charge waveforms and drain switching analysis. But
not so many about the effects of wiring inductance, etc.
>> Furthermore, what matters is the true gate voltage, inside
>> the die, hidden from you for a short time on the far side
>> of the gate spreading resistance.
>>
>> And it's the source voltage that has the damaging spike,
>
> You mean the spike goes negative causing VGS to be higher?
Actually, it's a resonant ringing, and is most likely to
happen at shutoff, at the end of your coil-current pulse.
It's possible it could fail on the very first relay pulse.
As for whether it's a positive or negative voltage that
does the job, can't say. But I'll wager that PCB wiring
inductance is involved.
>> Is only one of the two mosfets failing?
>
> Yes, only one of two MOSFETs have obvious failure.
> Gate to Drain low resistance or short.
That rules out ESD damage, I'd say.
I see you're giving up on the relay. But I hope you add
some resistance and do enough testing to see if it helps.
If you replace a bad mosfet, and run it for a while, is
there a very high chance of failure again? High enough
to be able to get an idea if it's working.
--
Thanks,
- Win
Jeroen Belleman
>> Sorry, that's not the way it works. Yes of course your gate-
>> drive voltage is under 8V. And your risetime may not look fast,
>> but that includes the slow gnd-to-plateau, and plateau-to-Vcc
>> portions. It's during the short plateau when all the action
>> happens and drain voltage switches.
>
>
> I did see a plateau indeed. Is there any recommended source of
> information where I can learn all the details?
The plateau is caused by the falling drain voltage acting
back on the gate through the gate-drain capacitance.
>
> Furthermore, what matters
>> is the true gate voltage, inside the die, hidden from you for
>> a short time on the far side of the gate spreading resistance.
>>
>> And it's the source voltage that has the damaging spike,
>
> You mean the spike goes negative causing VGS to be higher?
How is this wired, anyway? Does the source connect directly to
the ground plane of the thingy driving it, or does it go to some
remote ground?
Jeroen Belleman
John Larkin
Good point. Split/star grounds can cause all sorts of problems. Star
grounds are evil.
John
Hammy
>
>I would at least put a small resistance, say 100 ohms or so, in series
>with the gate to PIO pin. I'm not sure why you need the pull down as the
>MCU should drive it ok. Unless the MCU three states the pin prior to
>completing the reset. What bypassing are you using in the circuit? MCU?
>Fet?
>
>
>Regards,
>T
>
>
>
I use a pull down when driving FET's directly off a PIC as well. Most
uC's on start-up default to input so a pull down ensures the FET stays
off. I usually use 220k Bleeder gate to source or higher though.
Its a pretty low threshold FET are you sure your Vgs is going low
enough to completely turn it off especially with a 10k pull down?
I don't know what uC your using but the worst case LOW on an I/O for a
PIC can be as high as 0.6V At as little as 1.2mA. I've never seen it
that high but it is the worst case.
You would figure a rupture of the gate oxide from over voltage would
cause it to fail open. I've never had a FET fail that way usually when
I blow one its pretty spectacular and obvious. ;-)
You really want to keep the loop for the gate source signal small as
well as the drain source loop to reduce trace inductance. You should
be using a gate resistor 4.7 to 22 ohm or a fusible resistor may be
better in this case;-)
Oh and just because your not seeing ringing doesnt mean it isnt, you
may just need a higher BW scope to see it. The gate oxide of such a
low threshold fet wouldnt be to tolerant to overvoltage transients.
Myauk
I did not give up, the decision was just made by my seniors to close
the case by removing the whole circuit and feature in the unit cuz we
we need to meet the project dead line.
Mean while, from experiments I just found out the even if the FET Gate
and Drain is shorted, it does not really kill the MCU DIO pin at 5V.
As the relay has 86 ohms, and DIO internal circuit has a regulation
scheme which controls sinking current not to exceed 15mA, the DIO was
not killed immediate if 5V is fed to it through 85 ohms at LOW
condition. This leads to a series of tests on MCU, this is the really
why I could not focus on FET yet.
But a decision also has been made to add relevant resistance between
MCU and FET Gate in next design release.
Regards
Myauk
> How is this wired, anyway? Does the source connect directly to
> the ground plane of the thingy driving it, or does it go to some
> remote ground?
The source connects directly to the ground plane.
Regards
Winfield Hill
>
> Winfield Hill wrote:
>> Myauk wrote...
>>
>>
>> Actually, it's a resonant ringing, and is most likely to
>> happen at shutoff, at the end of your coil-current pulse.
>> It's possible it could fail on the very first relay pulse.
>> As for whether it's a positive or negative voltage that
>> does the job, can't say. But I'll wager that PCB wiring
>> inductance is involved.
>
> and Drain is shorted, it does not really kill the MCU DIO pin at 5V.
> As the relay has 86 ohms, and DIO internal circuit has a regulation
> scheme which controls sinking current not to exceed 15mA, the DIO
> was not killed immediate if 5V is fed to it through 85 ohms at LOW
> condition. This leads to a series of tests on MCU, this is the
> really why I could not focus on FET yet.
With all the detailed discussion we've been having on ringing,
spikes, and transient situations causing your failures, I'd
have hoped by now that you would see that you can't always rely
on simple steady-state stress analysis. Consider what extreme
event is causing the mosfet to fail, and the processor's pin
connected directly to the mosfet gate and this event. It's
reasonable that it could take out the processor pin as well.
I wouldn't waste any time testing the processor's robustness.
I'd fix the design issue causing the fault event.
> But a decision also has been made to add relevant resistance between
> MCU and FET Gate in next design release.
Good.
--
Thanks,
- Win
Jamie
Yes, pay some poor student looking for extra cash to sit there with an
exacto knife to sever the trace and bridge it with a smt R on the
existing ones!...
Why make your customers suffer on first editions! Most likely those
that past the test will also fail soon!..
Myauk
wrote:
>
> - Show quoted text -
A question still comes into my mind.
How come we found this problem only in 5 out of 100 units, especially
in the first 100 units batch and no more?
Does that mean such kind of transient spikes fatal to the IOs and FETs
could happen rarely and randomly?
What if I test this relay switching function on a working unit say..a
million times? Will it probably happen again?
The case has already been closed, but I cannot reach my conclusion
from experiment results until now.
Regards