Good Find, CD4007 Spice Model Library....

[Jim Thompson]

Good Find, CD4007 Spice Model Library, at Rochester Institute of
Technology, actual measurements by Professor Lynn Fuller...

<https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>


...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I'm looking for work... see my website.

Thinking outside the box...producing elegant & economic solutions.

[Cursitor Doom]

On Sat, 15 Jul 2017 11:31:33 -0700, Jim Thompson wrote:

> Good Find, CD4007 Spice Model Library, at Rochester Institute of
> Technology, actual measurements by Professor Lynn Fuller...
>
> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>
>
> ...Jim Thompson

You must have an *exceedingly* copious library of spice models by now,
Jim?

[Jim Thompson]

119 Manufacturers/Foundries, some, like X-Fab, with 12 different
processes.

Plus all the behavioral models I've rolled myself, probably also in
the hundreds ;-)

[Piglet]

On 15/07/2017 19:31, Jim Thompson wrote:
> Good Find, CD4007 Spice Model Library, at Rochester Institute of
> Technology, actual measurements by Professor Lynn Fuller...
>
> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>
>
> ...Jim Thompson
>

Thanks Jim, very versatile chip that has saved my bacon more than once.

piglet

---
This email has been checked for viruses by AVG.
http://www.avg.com

[Jim Thompson]

On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
wrote:

>On 15/07/2017 19:31, Jim Thompson wrote:
>> Good Find, CD4007 Spice Model Library, at Rochester Institute of
>> Technology, actual measurements by Professor Lynn Fuller...
>>
>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>>
>>
>> ...Jim Thompson
>>
>
>Thanks Jim, very versatile chip that has saved my bacon more than once.
>
>piglet
>

I'm studying the pin out to see if it's a viable device to use for a
translator for conventional logic levels up to 15V swings.

Watch this space ;-)

[John Larkin]

On Sat, 15 Jul 2017 12:08:00 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
>wrote:
>
>>On 15/07/2017 19:31, Jim Thompson wrote:
>>> Good Find, CD4007 Spice Model Library, at Rochester Institute of
>>> Technology, actual measurements by Professor Lynn Fuller...
>>>
>>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>>>
>>>
>>> ...Jim Thompson
>>>
>>
>>Thanks Jim, very versatile chip that has saved my bacon more than once.
>>
>>piglet
>>
>
>I'm studying the pin out to see if it's a viable device to use for a
>translator for conventional logic levels up to 15V swings.
>
>Watch this space ;-)
>
> ...Jim Thompson

After 49 years, we finally get models!

I often use opamps as level translators. At lower voltages, LVDS line
receivers.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Cursitor Doom]

On Sat, 15 Jul 2017 11:54:10 -0700, Jim Thompson wrote:

> Plus all the behavioral models I've rolled myself, probably also in the
> hundreds ;-)

From your own empirical results, or constructed from datasheets?

[Jim Thompson]

Both.

Specific part numbers mostly from datasheets, although paying
customers usually provide netlists of the real deal, plus lab-quality
data.

Plus I have tons of functional blocks which aid me in both device
_and_ system modeling:

Like the most recent, hysteresis without feedback. Those who squawk
that it _requires_ a latch haven't looked at a B-H curve recently...
show me the "snap" (except, of course, those cores designed as memory
elements, and their "snap" is still soft if you look close-up and
personal ;-)

[Jim Thompson]

On Sat, 15 Jul 2017 14:11:20 -0700, John Larkin
<jjla...@highlandtechnology.com> wrote:

>On Sat, 15 Jul 2017 12:08:00 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
>>wrote:
>>
>>>On 15/07/2017 19:31, Jim Thompson wrote:
>>>> Good Find, CD4007 Spice Model Library, at Rochester Institute of
>>>> Technology, actual measurements by Professor Lynn Fuller...
>>>>
>>>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>>>>
>>>>
>>>> ...Jim Thompson
>>>>
>>>
>>>Thanks Jim, very versatile chip that has saved my bacon more than once.
>>>
>>>piglet
>>>
>>
>>I'm studying the pin out to see if it's a viable device to use for a
>>translator for conventional logic levels up to 15V swings.
>>
>>Watch this space ;-)
>>
>> ...Jim Thompson
>
>After 49 years, we finally get models!

Looks like I can make a pair of CD4007's work.

Maybe later today. I'm still in the throes of the side-effects that
occur _after_ the chemo is done, like itchy hives and diarrhea :-(

>
>I often use opamps as level translators. At lower voltages, LVDS line
>receivers.

I like LVDS... I've designed a few such chips.

[tabb...@gmail.com]

On Saturday, 15 July 2017 22:52:11 UTC+1, Jim Thompson wrote:

> Maybe later today. I'm still in the throes of the side-effects that
> occur _after_ the chemo is done, like itchy hives and diarrhea :-(

Fun :( FWIW it's spelt dire rear.


NT

[whit3rd]

On Saturday, July 15, 2017 at 12:08:10 PM UTC-7, Jim Thompson wrote:
> On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
> wrote:
>
> >On 15/07/2017 19:31, Jim Thompson wrote:
> >> Good Find, CD4007 Spice Model

> I'm studying the pin out to see if it's a viable device to use for a
> translator for conventional logic levels up to 15V swings.

The protection diodes are wired so that those swings wouldn't
be compatible with low PS voltages. The 4049 and 4050
would be a more usual solution (no positive-rail clamp on inputs).

[Jim Thompson]

{>:-}

[Piglet]

On 15/07/2017 20:08, Jim Thompson wrote:
>
> I'm studying the pin out to see if it's a viable device to use for a
> translator for conventional logic levels up to 15V swings.
>
> Watch this space ;-)
>
> ...Jim Thompson
>

I did a doubling level shifter (5V in to 10V out) way back, but it used
a flying capacitor. Being a monolithic designer I guess you'll find ways
to do it all silicon :)

[Cursitor Doom]

On Sat, 15 Jul 2017 15:58:37 -0700, Jim Thompson wrote:

Sorry if this has already been covered, Jim, but you used to be a
confirmed pspice user, and exclusively so, IIRC. Then you dabbled around
with ltspice and again, IIRC, quite liked it (with certain reservations).
Which of these two are you mainly using these days and are there any big
differences in the way each handles imported 'foreign' models?

[piglet]

On 15/07/2017 23:55, whit3rd wrote:
> The protection diodes are wired so that those swings wouldn't
> be compatible with low PS voltages. The 4049 and 4050
> would be a more usual solution (no positive-rail clamp on inputs).
>

In my 4007 voltage doubling level shifter the chip's Vdd rail was not
connected to any system rails but self generated higher voltage.

piglet

[Jim Thompson]

I'm still a died-in-the-wool PSpice user.

I've dabbled with LTspice only because some of my clients wanted to
"play along" during their chip design.

Those who simply simulated my .CIR file got excellent correlation.

Those that chose to "draw" their own schematic got overly optimistic
results.

I mused for sometime over how Mike Engelhardt bragged about his speed
advantage over PSpice and every other simulator.

I went to one of his seminars and he touted over and over that his
technique of a special "compiling" of the netlist gave him the
advantage.

Then it dawned. His "compiling" is going in and replacing every
recognizable "standard" part in the netlist with idealized
equivalents. Thus the speed "improvement".

You can see his speed advantage fall apart if you feed LTspice with
only components not native to LTspice.

The absence of the Berkeley-Spice-standard .OUT file in LTspice
confirms my suspicions... that would list the actual circuit simulated
along with all the model data, operating points, etc, the whole
shebang.

As for model handling... any Berkeley-Spice-standard model should work
in LTspice (if not encrypted).

(The only way to avoid LTspice "compiling" is to run from another
schematic-capture-generated .CIR/.NET. If you run from a .ASC you get
the "treatment".)

[Jim Thompson]

On Sat, 15 Jul 2017 12:08:00 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
>wrote:
>
>>On 15/07/2017 19:31, Jim Thompson wrote:
>>> Good Find, CD4007 Spice Model Library, at Rochester Institute of
>>> Technology, actual measurements by Professor Lynn Fuller...
>>>
>>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>>>
>>>
>>> ...Jim Thompson
>>>
>>
>>Thanks Jim, very versatile chip that has saved my bacon more than once.
>>
>>piglet
>>
>
>I'm studying the pin out to see if it's a viable device to use for a
>translator for conventional logic levels up to 15V swings.
>
>Watch this space ;-)
>
> ...Jim Thompson

See "CD4007_Logic_Level_Shifter.zip" on the S.E.D/Schematics Page of
my website.

Had the original CD4007 designer been more free and not tied gates
together, it could be done without the resistors.

[Cursitor Doom]

On Sun, 16 Jul 2017 09:26:30 -0700, Jim Thompson wrote:

> Then it dawned. His "compiling" is going in and replacing every
> recognizable "standard" part in the netlist with idealized equivalents.
> Thus the speed "improvement".

Oh boy. Well, I guess Mike in his own defence would simply say he'd
refund you every single cent you paid for it. ;-)
I hope Mike's not reading this, btw, as from the exchanges I've had with
him from time to time in the past, he doesn't like this kind of thing
being openly discussed in a public forum (not surprisingly).

[Jim Thompson]

Having met him face-to-face over lunch at one of his seminars a few
years back, I'd rank Mike Engelhardt as a first class narcissistic
pompous ass... and I'm being kind >:-}

[Jim Thompson]

On Sat, 15 Jul 2017 15:55:25 -0700 (PDT), whit3rd <whi...@gmail.com>
wrote:

What are you bloviating about?

See...

Message-ID: <nmfnmctnkb54vmoic...@4ax.com>

[John Larkin]

On Sun, 16 Jul 2017 13:35:38 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 15 Jul 2017 15:55:25 -0700 (PDT), whit3rd <whi...@gmail.com>
>wrote:
>
>>On Saturday, July 15, 2017 at 12:08:10 PM UTC-7, Jim Thompson wrote:
>>> On Sat, 15 Jul 2017 20:02:11 +0100, Piglet <erichp...@hotmail.com>
>>> wrote:
>>>
>>> >On 15/07/2017 19:31, Jim Thompson wrote:
>>> >> Good Find, CD4007 Spice Model
>>
>>> I'm studying the pin out to see if it's a viable device to use for a
>>> translator for conventional logic levels up to 15V swings.
>>
>>The protection diodes are wired so that those swings wouldn't
>>be compatible with low PS voltages. The 4049 and 4050
>>would be a more usual solution (no positive-rail clamp on inputs).
>
>What are you bloviating about?
>
>See...
>
>Message-ID: <nmfnmctnkb54vmoic...@4ax.com>
>
> ...Jim Thompson

I think you can go 5 volts to 15 volts level conversion with a 4007
and zero external parts, but the power dissipation would be nasty.

One resistor, easy.

[Jim Thompson]

Show us.

[Tim Williams]

"Cursitor Doom" <cu...@notformail.com> wrote in message
news:okgh57$djj$2...@dont-email.me...

> Oh boy. Well, I guess Mike in his own defence would simply say he'd
> refund you every single cent you paid for it. ;-)

Good! Maybe then LT parts would be cost-competitive! ;-)

(Reminder what you're referring to: LTSpice is a marketing tool, and as
such, its development cost is rolled into the bottom line of _every part
purchased_. Strictly speaking, parts would be cheaper without LTSpice.
Presumably, they would get fewer design wins and therefore lower revenue if
they dropped it, so LTSpice carries on.)

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

[John Larkin]

On Sun, 16 Jul 2017 15:12:41 -0700, Jim Thompson

The single-resistor+single-4007 thing is trivial, and adding
hysteresis with one more resistor should be obvious. The trick would
be to do it with no resistors, working with the 4007 pinout.

This could work:

https://www.dropbox.com/s/l6g1h46nhsugb4t/CD4007_LS_1.JPG?raw=1

the trick being to get the first-stage pullup current down to some
sane value. This circuit might work with 5V input, probably not at
3.3.

Of course, there are better ways to do this function.

[Jim Thompson]

On Sun, 16 Jul 2017 20:19:14 -0700, John Larkin

I posted the Spice Model... show us that your scheme works.

>
>Of course, there are better ways to do this function.

Yes.

[Piglet]

In the CD4007 some of the sources are not connected to their substrate
so TGs become possible. How about in your circuit driving one of your
input pmos gates from the output instead of the input?

[John Larkin]

On Sun, 16 Jul 2017 21:09:11 -0700, Jim Thompson

No reason to do that. Too much work, and it's not my problem.

>
>>
>>Of course, there are better ways to do this function.
>
>Yes.
>
> ...Jim Thompson

--

[Jim Thompson]

On Sat, 15 Jul 2017 11:31:33 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>Good Find, CD4007 Spice Model Library, at Rochester Institute of
>Technology, actual measurements by Professor Lynn Fuller...
>
><https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>
>
> ...Jim Thompson

With Dr. Fuller's permission, it is now also posted on the Device
Models & Subcircuits Page of my website.

[piglet]

If the TTL world provides complementary true and true-bar inputs to the
level shifter then 2/3 of CD4007 can shift to high level very easily:

<https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0>

If there are inverters or other CD4007s living in the low rail
environment they could provide the low-level inversion.

Real shame all the CD4007 p-channels are tied to Vdd - then this
challenge would be simpler :>

piglet

[Jim Thompson]

On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichp...@hotmail.com>
wrote:

[snip]

>>
>
>If the TTL world provides complementary true and true-bar inputs to the
>level shifter then 2/3 of CD4007 can shift to high level very easily:
>
><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0>
>
>If there are inverters or other CD4007s living in the low rail
>environment they could provide the low-level inversion.

That is the classic way that level-shifting is done on-chip (with
embellishments that minimize the peak current required at each
transition).

First thing I tried. The problem is that the N-channel devices are
too 'weak' to overcome the P-channels, thus I went the route of the
added resistors.

>
>Real shame all the CD4007 p-channels are tied to Vdd - then this
>challenge would be simpler :>
>
>piglet
>

Only the body ties are to VDD, two of the P-channel devices have free
sources.

I'd would have loved to have a few 'free' N-channel gates, then my
embellishment tricks could be implemented.

On custom chip designs I have all those freedoms plus I can size
devices at will ;-)

(I think it was you, piglet, who commented, "...power from output" for
the first inverter. That's also in my bag of tricks, but also
wouldn't play because the N-channels at three volt gate drive are
'weenies' ;-)

[John Larkin]

Why not a single grounded-source n-fet, and a pullup resistor on the
drain?

--

John Larkin Highland Technology, Inc

picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Jim Thompson]

If your application can tolerate the exponential rising edge, sure,
why not.

The 'classic' approach in CMOS has quite 'stiff' edges at the output
(there _is_ positive feedback, two inverters tied back on themselves).

[John Larkin]

On Mon, 17 Jul 2017 13:43:52 -0700, Jim Thompson

After the nfet input stage, there are two leftover buffers in the
4007. It's easy to make a Schmitt, too.

[Jim Thompson]

On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichp...@hotmail.com>
>wrote:
>
>[snip]
>>>
>>
>>If the TTL world provides complementary true and true-bar inputs to the
>>level shifter then 2/3 of CD4007 can shift to high level very easily:
>>
>><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0>
>>
>>If there are inverters or other CD4007s living in the low rail
>>environment they could provide the low-level inversion.
>
>That is the classic way that level-shifting is done on-chip (with
>embellishments that minimize the peak current required at each
>transition).
>

[snip]

One embellishment method...

<http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png>

Done by ignoring the pin-out restrictions of the CD4007 but no
optimizing size scaling.

[whit3rd]

That's an example of Leaver's Law. Putting many transistors into an integrated
circuit is a big win. But, everything it does FOR you, it also does TO you.

SOS (silicon-on-sapphire) and other oxide isolation gets around this, but
adds cost and complication.

[pcdh...@gmail.com]

>SOS (silicon-on-sapphire) and other oxide isolation gets
>around this, but
adds cost and complication.

SOS was an '80s enthusiasm, mostly of HP's, iirc. More modern S0I is a whole lot cheaper--a bonded or SIMOX wafer isn't that much more expensive than a bulk wafer.

There are still a few folks using SoS, but it's far from mainstream.

Cheers

Phil Hobbs

[piglet]

On 17/07/2017 22:59, Jim Thompson wrote:
> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson
>

> One embellishment method...
>
> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png>
>
> Done by ignoring the pin-out restrictions of the CD4007 but no
> optimizing size scaling.
>
> ...Jim Thompson
>

Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have
their gates at +15V and their substrates at 0V so both will be fully
enhanced and basically just two pieces of wire. Is that a monolithic way
of making a low resistance?

piglet

[piglet]

On 17/07/2017 21:31, John Larkin wrote:
>
> Why not a single grounded-source n-fet, and a pullup resistor on the
> drain?
>
>

Yeah, but that is a real-world way of doing things :>

The more interesting problem was to make it true to the ethos of CMOS
and have no current draw for either logical state.

piglet

[John Larkin]

On Tue, 18 Jul 2017 09:51:05 +0100, piglet <erichp...@hotmail.com>
wrote:

Don't cheat by requiring complementary TTL inputs!

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Jim Thompson]

On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichp...@hotmail.com>
wrote:

At the low end of the output swing they're low resistances, at the
high end of the output swing they're high resistances. Thus the low
current required to 'upset' the latch.

[piglet]

On 18/07/2017 16:24, Jim Thompson wrote:
> On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichp...@hotmail.com>
> wrote:
>
>> On 17/07/2017 22:59, Jim Thompson wrote:
>>> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson
>>>
>>> One embellishment method...
>>>
>>> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png>
>>>
>>> Done by ignoring the pin-out restrictions of the CD4007 but no
>>> optimizing size scaling.
>>>
>>> ...Jim Thompson
>>>
>>
>> Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have
>> their gates at +15V and their substrates at 0V so both will be fully
>> enhanced and basically just two pieces of wire. Is that a monolithic way
>> of making a low resistance?
>>
>> piglet
>
> At the low end of the output swing they're low resistances, at the
> high end of the output swing they're high resistances. Thus the low
> current required to 'upset' the latch.
>
> ...Jim Thompson
>

Thanks. I see now.

piglet

[Jim Thompson]

On Tue, 18 Jul 2017 22:20:37 +0100, piglet <erichp...@hotmail.com>

There are far snazzier ways, but can't be done with CD4007 devices...
plus the device count would offend Larkin's sensibilities ;-)

(Did you note that low power even at a 10MHz rate?)

[Kevin Aylward]

"Jim Thompson" wrote in message
news:jdinmc5tvkl0kbcv9...@4ax.com...

On Sun, 16 Jul 2017 20:09:11 -0000 (UTC), Cursitor Doom
<cu...@notformail.com> wrote:

>On Sun, 16 Jul 2017 09:26:30 -0700, Jim Thompson wrote:
>
>> Then it dawned. His "compiling" is going in and replacing every
>> recognizable "standard" part in the netlist with idealized equivalents.
>> Thus the speed "improvement".

>s

>>Oh boy. Well, I guess Mike in his own defence would simply say he'd
>>refund you every single cent you paid for it. ;-)
>>I hope Mike's not reading this, btw, as from the exchanges I've had with
>>him from time to time in the past, he doesn't like this kind of thing
>>being openly discussed in a public forum (not surprisingly).

>Having met him face-to-face over lunch at one of his seminars a few
>years back, I'd rank Mike Engelhardt as a first class narcissistic
>pompous ass... and I'm being kind >:-}

I have to agree. If you recall around 2,000 he posted to this PUBLIC NG that
I had applied to LT, and trashed my resume in PUBLIC, and hence told the
world that I had applied for a job whilst employed at TI. I made an
official complaint to LT HR that Mike had breached a clear confidentiality.
17 years on, I have yet to receive any apology from LT. This also says
something about LT.

Anyway, at least I now have a superior to Mikes LTSpice VDMOS. To wit,
non-linear cgs, cgd, quasi-sat and subthreshold...

http://www.anasoft.co.uk/MOS1Model.htm :-)

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

[Jim Thompson]

Nice!

[Jim Thompson]

On Sat, 15 Jul 2017 11:54:10 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Sat, 15 Jul 2017 18:36:23 -0000 (UTC), Cursitor Doom
><cu...@notformail.com> wrote:

>
>>On Sat, 15 Jul 2017 11:31:33 -0700, Jim Thompson wrote:
>>
>>> Good Find, CD4007 Spice Model Library, at Rochester Institute of
>>> Technology, actual measurements by Professor Lynn Fuller...
>>>
>>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf>
>>>
>>>
>>> ...Jim Thompson
>>

>>You must have an *exceedingly* copious library of spice models by now,
>>Jim?
>
>119 Manufacturers/Foundries, some, like X-Fab, with 12 different
>processes.
>
>Plus all the behavioral models I've rolled myself, probably also in
>the hundreds ;-)
>
> ...Jim Thompson

Just added foundry #120... Vanguard International Semiconductor
Corporation ;-)