Interfacing ECL to TTL
Mika Koistinen
I´m working with PLL-project that calls interfacing prescaler SA 702
(from Philips) to 74AC02.Single transistor converter seems to have poor
noise immunity. Any links and tips will be greatly appreciated.
Thanks,
Mika
John Trites
Check out Motorola's Web site @ http://scgproducts.motorola.com/taxonomy3.asp?lvl1=Logiclvl2=Translators&lvltable=Logic.Translators
They have MECL10K and MECL10KH Translators for TTL to ECL and ECL to
TTL conversion with excellent noise immunity.
The MC10124 is a quad TTL to ECL converter
The MC10125 is a quad ECL to TTL converter
I hope this helps.
Regards,
JT
Robert
Another alternative would be to AC couple the 1.6 Vpp prescaler output into a 74ACxx inverter biased into its linear region and cascade this with a few more gates to square the signal.
Robert
Bill sloman
Mika Koistinen wrote:
>
> Hello,
> I´m working with PLL-project that calls interfacing prescaler SA 702
> (from Philips) to 74AC02.Single transistor converter seems to have poor
> noise immunity. Any links and tips will be greatly appreciated.
Get hold of a Motorola High Performance ECL data book covering the
ECLinPS
and ECLinPS lite ranges.
This has data sheets for the MC10ELT25 and MC100ELT25 differential
ECL-to-TTL translators and the MC10ECL26 and MC100ELT26 differntial
PECL-to-TTL
translators.
Newark stocks a fair number of the ECLinPS parts - though not the
MC10/100ELT25 when I last looked, a couple of years ago.
Syzergy and Arizona Microtech both second source the ECLinPS range,
and Syzergy has been known to sell small quantities.
If none of this works, buy a couple of 5 or 6GHz wideband transistors
from Farnell or the like - the Philips/Siemens BFR92 or BFR93 (NPN)
and BFT92 and BFT93 (PNP) come to mind - and use the ECL output/s
to drive a long-tailed pair to convert the signal to a current, then
level shift to get your CMOS level swing.
The nature of the output circuit you will need depends how fast you
need to go, and whether your ECL signal is really ECL (swinging
between -0.8V and -1.6V) or PECL (swinging between 4.2V and 3.4V).
I always had to use a "base stopper" - a roughly 33R SMD resistor
close to and in series with the base - with these transistors to
stop them oscillating, but they were otherwise pretty easy to use.
Post (or e-mail) more detail if you want more advice.
Bill Sloman, Nijmegen
Mika Koistinen
Robert <rom...@earthlink.net> wrote in message news:37CF1E69...@earthlink.net...
This won't work here. The SA702 runs off a single Vcc for TTL/CMOS compatible control inputs and differential ECL compatible outputs referenced to Vcc. What he needs is a single supply comparator with Tpd in the 10ns range, CMOS compatible output drive, and input common mode range that can handle the Q and /Q SA702 outputs in the range Vcc-1.4 to Vcc-2.6 volts. There are many choices.
Another alternative would be to AC couple the 1.6 Vpp prescaler output into a 74ACxx inverter biased into its linear region and cascade this with a few more gates to square the signal.
Here´s the converter I have experimented with.VCC is connected to pin 2 , GND to pin 3 and 7.Modulus control(pin6) is driven by normal TTL levels and it seems to workalright.Output frequency of the prescaler is about 7.5MHz.5-------------------ESA702 BC557 C----2.7k--------GND|B |____________________________out4 ----- 3.3k----- || |10k 2.7k| || |GND VCC +5vThis circuit has been successfully used with L and LS TTL-families.Perhaps I should use one of these or AC coupled inverters,butsingle or double transistor solutions would be more convenient becausepcb is running out of space.Mika
John Trites
This actually DOES WORK!!! You run the ECL Translators with -VEE (-5.2V) at GND and the ECL GND at +5V. This shifts the ECL rails to +3.3v and +4.3v. I actually used this for a project back in 1990 and it worked just fine. But, there are newer ECL-TTL translators offered by Motorola (listed below) specifically designed for +5V and GND operation. Check it out.
Regards,
Happy Designing!
JT
Robert wrote:
This won't work here. The SA702 runs off a single Vcc for TTL/CMOS compatible control inputs and differential ECL compatible outputs referenced to Vcc. What he needs is a single supply comparator with Tpd in the 10ns range, CMOS compatible output drive, and input common mode range that can handle the Q and /Q SA702 outputs in the range Vcc-1.4 to Vcc-2.6 volts. There are many choices.
Another alternative would be to AC couple the 1.6 Vpp prescaler output into a 74ACxx inverter biased into its linear region and cascade this with a few more gates to square the signal.
John Trites wrote:
Mika,
Check out Motorola's Web site @ http://scgproducts.motorola.com/taxonomy3.asp?lvl1=Logiclvl2=Translators&lvltable=Logic.Translators
They have MECL10K and MECL10KH Translators for TTL to ECL and ECL to TTL conversion with excellent noise immunity.
The MC10124 is a quad TTL to ECL converter
The MC10125 is a quad ECL to TTL converter
I hope this helps.
Regards,
JT
Mika Koistinen wrote:
Hello,
I´m working with PLL-project that calls interfacing prescaler SA 702
(from Philips) to 74AC02.Single transistor converter seems to have poor
noise immunity. Any links and tips will be greatly appreciated.
Thanks,
Mika
Robert
if the arithmetic is right, the highest frequency he couldl handle is about
17 MHz. The actual conversion is no problem, the real issue is probably power
consumption as portable systems are the targeted market for these ICs. The
SA702 is ECL compatible in voltage only- it does not have the same current
drive capability; the test circuit shows the 'ECL' complementary outputs
terminated in 2.2K to ground.. The spec states that Voh,max=Vcc-1.4 and that
Vol,typ=Vcc-2.6 and that Vo,pp=1.6 typical. Would an AC coupling into a
74AC02 biased into linear operation be the lowest power choice? I would think
that a Vo,pp=1.6 would keep one or the other of the input FETs near cutoff so
that the Icc due to linear operation would be about the same as in logic
operation. The application should be for a CW output of the prescaler, of
course, and this is most likely.
Bill sloman wrote:
> Mika Koistinen wrote:
> >
> > Hello,
> > I´m working with PLL-project that calls interfacing prescaler SA 702
> > (from Philips) to 74AC02.Single transistor converter seems to have poor
> > noise immunity. Any links and tips will be greatly appreciated.
>
Bill Sloman
rom...@earthlink.net wrote:
> The SA702 handles up to 1.1 GHz input with a minimum divide ratio of
> 64- so if the arithmetic is right, the highest frequency he could
> issue is probably power consumption as portable systems are the
> targeted market for these ICs.
> The SA702 is ECL compatible in voltage only- it does not have the same
> current drive capability; the test circuit shows the 'ECL'
> complementary outputs terminated in 2.2K to ground.. The spec states
> that Voh,max=Vcc-1.4 and that Vol,typ=Vcc-2.6 and that Vo,pp=1.6
> typical. Would an AC coupling into a 74AC02 biased into linear
> operation be the lowest power choice?
If it is biased into linear operation, both the N- and P-channel MOSFETs
are going to be on at the same time, which is the antithesis of low
power.
> I would think that a Vo,pp=1.6 would keep one or the other of the
> input FETs near cutoff so that the Icc due to linear operation would
> be about the same as in logic operation.
Depends on the gain of the gate around the bias point. Single stage
gates have a gain of about 10 IRRR and two-stage gates about 40, which
sounds enough to keep the extra current consumption fairly small, but
you are operating outside the manufacturers specification, which is
always risky - what works fine today with one manufacturer's transistors
may not work with next year's new, improved batch or with batch from the
new cheap supplier that purchasing has found for you.
Another question is how fast the SA702 switches when driving a 10pF
load.
I'd feel safer with a couple of wide-band bipolar transistors - running
at low collector current if current consumption is a problem. You'd
balance the static consumption of your transistors against the width of
the current spike though the CMOS part they wer driving.
--
Bill Sloman, Nijmegen
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Bill Sloman
rom...@earthlink.net wrote:
> The SA702 handles up to 1.1 GHz input with a minimum divide ratio of
> 64- so if the arithmetic is right, the highest frequency he could
> handle is about 17 MHz. The actual conversion is no problem, the real
> issue is probably power consumption as portable systems are the
> targeted market for these ICs.
>
> The SA702 is ECL compatible in voltage only- it does not have the same
> current drive capability; the test circuit shows the 'ECL'
> complementary outputs terminated in 2.2K to ground.. The spec states
> that Voh,max=Vcc-1.4 and that Vol,typ=Vcc-2.6 and that Vo,pp=1.6
> typical. Would an AC coupling into a 74AC02 biased into linear
> that a Vo,pp=1.6 would keep one or the other of the input FETs near
> cutoff so that the Icc due to linear operation would be about the same
> the prescaler, of course, and this is most likely.
When I posted my initial response on Saturday evening I wasn't happy
with it, but it wasn't until I was cutting the grass on Sunday that the
penny dropped. The 74AC02 is definitely going to draw extra current from
the +5V if driven from the SA702, even if AC coupled.
If the SA702 is generating a nice 17MHz square-wave output you can
capacitor-couple this to an input to a 74AC02 quad NOR gate, but the
output put you should get will be a 50% duty cycle square wave. You can
feed this back to the CMOS input to bias the gate at Vcc/2, but this
doesn't mean that you are biassing the gate at its actual threshold,
which lies somewhere between about 1.6V and about 3.4V (for a 5V
supply).
A 1.6V swing around a 2.5V bias point is from 1.7V to 3.3V, which isn't
quite enough to include the worst case threshold range. The system will
still work with a worst case threshold, because the duty cyce will
adjust to something other than 50% to move the gate bias to the right
place, but note that the 74AC02 will no longer be switching on the fast
edges coming out of the SA702, but some way away.
This means that the edge jitter is going to be lousy, and that the
any significant noise on the 5V rail will be reflected as spikes on
the output from the 74AC02.
And the 74AC02 is going to spend about half its time biassed in a state
where both the P and N-channel MOSFETs on the input are biassed on,
so its power consumption is going to be high, and it may run hot enough
to compromise its reliability.
Even if the 74AC02 has a threshold comfortably within the 1.6V to 3.3V
input range, there is no guarantee that the power consumption won't be
high - when the 74AC02 is run from 1.5V rails, 1.2V from gate to rail is
enough to turn on one or other of the complementary MOSFETs, so with
something like 1.6V from gate to rail on the nominally "off" MOSFET the
74AC02 is defintely going to draw more current than it would if driven
by logic.
I'd go for the comparator approach, even if I had to make it
out of transistors (you only need a gain of about three or so).