Back to back Jfets

[David Eather]

A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain and
source. I am wondering how much different that would be compared to if you
got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain and
Q1 drain to Q2 source while commoning the gates together?

Any thoughts?

[Bill Sloman]

Regular J-FETs are perfectly symmetrical. The "drain" is the positive end of the channel, and the "source" the negative end. Swap the polarity and the J-FET works just the same way as it did before.

The gate cut-off voltage varies a lot from FET to FET - even with nominally identical devices - so what you propose is equivalent to connecting two random J-FETs in parallel. Under most circumstance most of the current is going to flow through just one of the devices, and the second part will just add stray capacitance.

You can (or a least could) buy monolithic matched pairs of J-FETs, where the channels tended to be adjacent serpentine stripes on the same wafer of silicon, and these could have fairly closely matched gate-cutoff voltages.

--
Bill Sloman, Sydney

[Jim Thompson]

On Thu, 13 Nov 2014 22:25:18 +1000, "David Eather" <eat...@tpg.com.au>
wrote:

A source to drain connection is called "cascoding", not the same thing
as I suspect Phil's "interchangeable" device would be.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[Phil Hobbs]

JFETs are depletion devices, which all work fine around I_DSS (i.e. zero
volts gate-source). So unless you're working at very low drain current,
parallelling two of them is pretty nearly equivalent to using twice as
big a FET. (There are some asymmetrical JFETs, in which case this isn't
quite the case, but they'll all be conducting heavily at zero volts bias.)

The only JFET I use with any regularity is the BF862, and I routinely
parallel them up to get higher transconductance and lower noise. Their
gate-drain capacitance is a few pF, so with high capacitance transducers
such as big photodiodes, you win SNR until the FET capacitance starts to
dominate.

With an I_DSS range of 10 to 25 mA, that costs a lot of power, of
course, so usually do you don't go quite that far. I've used as many as
10 of them, directly parallelled.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

[Phil Hobbs]

On 11/13/2014 10:17 AM, Jim Thompson wrote:
> On Thu, 13 Nov 2014 22:25:18 +1000, "David Eather" <eat...@tpg.com.au>
> wrote:
>
>> A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain and
>> source. I am wondering how much different that would be compared to if you
>> got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain and
>> Q1 drain to Q2 source while commoning the gates together?
>>
>> Any thoughts?
>>
>
> A source to drain connection is called "cascoding", not the same thing
> as I suspect Phil's "interchangeable" device would be.
>
> ...Jim Thompson
>

He's connecting D1 <-> S2 and D2 <-> S1, so they're in inverse parallel.
(To the OP: "back to back" usually means series opposing, e.g. making
a symmetrical bidirectional zener.)

[John Larkin]

On Thu, 13 Nov 2014 08:17:35 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Thu, 13 Nov 2014 22:25:18 +1000, "David Eather" <eat...@tpg.com.au>
>wrote:
>
>>A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain and
>>source.

Some jfets are nearly symmetric, some aren't. All are planar these
days, so aren't literally physically symmetric. Look at Ciss and Crss:
if they are very different, it's pretty asymmetric.

All jfets that I know of can be used as bidirectional switches, if you
manage the gate drive properly. Here's one nasty trick:


|--- D
gate drive----------|<------------->| nfet
diode G |--- S


There are photofets, too, with optical gate drive.

I am wondering how much different that would be compared to if you
>>got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain and
>>Q1 drain to Q2 source while commoning the gates together?
>>
>>Any thoughts?
>>
>
>A source to drain connection is called "cascoding", not the same thing
>as I suspect Phil's "interchangeable" device would be.
>
> ...Jim Thompson

He's talking about an antiparallel connection, not a cascode.

Seems like it would work, to me.

One could also connect two depletion fets in series, source-to-source,
with paralleled gates, to make a symmetric switch. Most depletion fets
have substrate diodes, so they can't be used antiparallel.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Spehro Pefhany]

If you maintain a (sufficient) voltage across the JFETs (as you would
have in a cascode, for example), each one will run at its own Idss,
which is fairly closely matched (maybe 2:1).

That's how you can parallel a metric crapload of JFETs and get
sqrt(metric crapload) (ideally, anyway) improvement in noise
performance.

Paralleling two (upside down or rightside up) will give a improvement
in noise of as much as 41% for double the current.

[John Larkin]

Clarifications:

If the gate is the substrate, a planar jfet can be symmetrical.

Ciss 2x Crss suggests symmetry.

[David Platt]

In article <e3273d04-cef5-4d01...@googlegroups.com>,

Bill Sloman <bill....@gmail.com> wrote:
>On Thursday, 13 November 2014 23:24:43 UTC+11, David Eather wrote:
>> A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain and
>> source. I am wondering how much different that would be compared to if you
>> got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain and
>> Q1 drain to Q2 source while commoning the gates together?
>>
>> Any thoughts?
>
>Regular J-FETs are perfectly symmetrical. The "drain" is the positive
>end of the channel, and the "source" the negative end. Swap the polarity
>and the J-FET works just the same way as it did before.

Somebody pointed me to an online copy of the National Semiconductor
JFET manual a while ago... it has actual diagrams of the layouts of
the dice for many of their JFET transistors. What I wrote at the
time:

For what it's worth... in the National Semiconductor book Bill
pointed me to, only one of the N-JFET processes (#52) explicitly
states that the source and drain are interchangeable.

In every one of those processes that I looked at (I think) it appears
that there is at least some asymmetry in the geometry of the source
and drain conductors on the dice. They're laid out as interlacing
"fingers", and it seems to be the case that one or the other of the
terminals has one more "finger" to it (that is, its outermost fingers
are always "outside" of the outermost fingers of the other terminal).
Most commonly it's the source which has the extra finger.

This could mean that this terminal has a bit of additional channel
area around it (on the "outside"). This might result in a slight
difference in channel-narrowing and pinch-off behavior between the two
possible orientations of the JFET (e.g. source-as-source, or
source-used-as-drain).

I'd hazard a guess that this is probably so slight that it's quite a
bit less than the part-to-part variation to be expected between
different JFETs of the same part number (or even from the same
wafer). I suppose it might be noticeable if you had a monolithic
dual, and ran one of the two right-side-up and the other
upside-down... but that'd be a silly way to spend your money :-)

I suppose I could put a few different ones on a curve-tracer and see
whether reversing the source/drain makes a significant difference.

I never did do that particular experiment... but since I've gotten a
7CT1N plug-in for my old 7904 scope, and have made a nice socketed
test-jig for it, I really should run one or two JFETs through a test
of this sort and take photos of the screen and see if the curves vary
at all when I flip the transistor upside-down.

[David Eather]

On Fri, 14 Nov 2014 01:33:02 +1000, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

> On 11/13/2014 10:17 AM, Jim Thompson wrote:
>> On Thu, 13 Nov 2014 22:25:18 +1000, "David Eather" <eat...@tpg.com.au>
>> wrote:
>>
>>> A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain
>>> and
>>> source. I am wondering how much different that would be compared to if
>>> you
>>> got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain
>>> and
>>> Q1 drain to Q2 source while commoning the gates together?
>>>
>>> Any thoughts?
>>>
>>
>> A source to drain connection is called "cascoding", not the same thing
>> as I suspect Phil's "interchangeable" device would be.
>>
>> ...Jim Thompson
>>
> He's connecting D1 <-> S2 and D2 <-> S1, so they're in inverse parallel.
> (To the OP: "back to back" usually means series opposing, e.g. making
> a symmetrical bidirectional zener.)

Oops, my bad

>
> Cheers
>
> Phil Hobbs

[Robert Baer]

Yes, but the price is ex$$$pensive!

[Kevin Aylward]

"Phil Hobbs" wrote in message news:5464CD4...@electrooptical.net...

On 11/13/2014 9:57 AM, Bill Sloman wrote:
> On Thursday, 13 November 2014 23:24:43 UTC+11, David Eather wrote:
>> A while ago Phil Hobbs mentioned a jfet with 'interchangeable'
>> drain and source. I am wondering how much different that would be
>> compared to if you got 2 jfets (call them Q1 and Q2) and connected
>> Q1 source to Q2 drain and Q1 drain to Q2 source while commoning the
>> gates together?
>>
>> Any thoughts?
>
> Regular J-FETs are perfectly symmetrical. The "drain" is the positive
> end of the channel, and the "source" the negative end. Swap the
> polarity and the J-FET works just the same way as it did before.
>
>> The gate cut-off voltage varies a lot from FET to FET - even with
>> nominally identical devices - so what you propose is equivalent to
>> connecting two random J-FETs in parallel. Under most circumstance
>> most of the current is going to flow through just one of the devices,
>> and the second part will just add stray capacitance.
>
>> You can (or a least could) buy monolithic matched pairs of J-FETs,
> >where the channels tended to be adjacent serpentine stripes on the
> >same wafer of silicon, and these could have fairly closely matched
> >gate-cutoff voltages.

Yes.

>

>JFETs are depletion devices, which all work fine around I_DSS (i.e. zero
>volts gate-source). So unless you're working at very low drain current,
>parallelling two of them is pretty nearly equivalent to using twice as big
>a FET. (There are some asymmetrical JFETs, in which case this isn't quite
>the case, but they'll all be conducting heavily at zero volts bias.)

>With an I_DSS range of 10 to 25 mA, that costs a lot of power, of course,
>so usually do you don't go quite that far. I've used as many as 10 of
>them, directly parallelled.

Ahmmm.... well, you have been very, very, lucky then. As Bill said, Vt
tolerances are relatively huge. Typically more than a 1V. Some data sheets
quote 3V.

Indeed, running at 0V gate source is worse than running with a source
resister to generate self bias.

Just a +/- 10% on a 2V Vt at vgs=0V might get you 20%, and 10% for self
bias.

I just just don't see it as viable to parallel jfets for reliable main
stream production, your goanna get 3:1 ratios in current.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

[Phil Hobbs]

No luck is involved, and you clearly have no idea of the application.

The I_DSS range of the BF862 is 2.5:1, and its transconductance is so
high that all the action is over in 400 mV of V_GS.

BF862s can be run slightly enhanced, which reduces their flatband noise
a bit and increases their transconductance, but of course increases the
gate leakage. Sometimes that's a win, sometimes not.

Servoing them to run at I_DSS optimizes the performance of each given
FET for bootstrap service, regardless of the I_DSS distribution. The
key metric of a bootstrap is how close its (loaded) gain is to (1.000000
+ j 0.0000000), so I don't need any particular value of I_DSS.

If I were building resistance-coupled audio preamps, I wouldn't be using
a JFET, for sure.

[Jan Panteltje]

On a sunny day (Fri, 14 Nov 2014 09:54:36 -0500) it happened Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote in
<546617AC...@electrooptical.net>:

>If I were building resistance-coupled audio preamps, I wouldn't be using
>a JFET, for sure.

I have seen, and used myself, JFETs as AGC element in audio mixers.
One applictation I have seen is where the DJ screams (speaks) into the mike,
then the music level is automagically reduced.


With a voltage divider on the gate it is sort of a resistor:


----------------- +
| |
R2 |-- d
|-||----->| JFET
R3 C2 | |-- s
| R4 |
| | |
---R1 --||---------)--------- audio out
audio C1 |
in volume
control
voltage

The JFET shorts the audio against the + supply line (that must be decoupled).
The volume control is between ground and some positive voltage,
the moee positive the less audio comes out.

The ratio R2 / R3 is to make a good resistor...
C1, C2 are simply coupling caps for audio

R1 is what the circuit works against.

R4 is a very high value.

JFETs are cool.

[Phil Hobbs]

The 50% gate feedback trick works pretty well for JFET variable
resistors, but interestingly not for MOSFETs. I took some data on that
one time, looking to see how well 2N7002s linearized. 50% had little
effect, but somewhere between 150% and 200% worked pretty well. I put
two of them in series, with their gates connected together, and took
about 90% feedback from the top drain to the two gates. THD improved
about 20 dB compared with a single device at the same resistance.

(This was down in the 2-10 ohm range.)

[David Eather]

Many thanks all!

[Kevin Aylward]

"Phil Hobbs" wrote in message news:546617AC...@electrooptical.net...

I don't know your exact circuit. However, I do know about jfets.

>The I_DSS range of the BF862 is 2.5:1, and its transconductance is so high
>that all the action is over in 400 mV of V_GS.

>Servoing them to run at I_DSS optimizes the performance of each given FET
>for bootstrap service, regardless of the I_DSS distribution. The key
>metric of a bootstrap is how close its (loaded) gain is to (1.000000 + j
>0.0000000), so I don't need any particular value of I_DSS.

I don't know your exact circuit.

Either you are putting them, as you actually claimed, in direct parallel,
i.e. gate to gate, source to source, drain to drain, or you are driving them
separately, e.g. individual current setting sources.

If they are in parallel as you claimed, they wont match. Period. They will
run at vastly different currents. With typical manufacturing specs of
several volts of Vt variations, some devices will be fully off, with the
other taking all the current. Period.

Hint: Go and run a SuperSpice test circuit and set one Vt to -1V and another
to -3V, which is way within typically variation specs for jfets. Typically a
10:1 ratio in currents results.

Hint: I very recently added parameter passing to .models allowing for
example, a parameter line spec for each device to be declared as, say,
scale=1.5, scale =0.5 with the model declared as:

.model (...Vto={-2.131 * scale} ...)

:-)

>If I were building resistance-coupled audio preamps, I wouldn't be using a
>JFET, for sure.

?

Jfets are brilliant as front end amps for guitars. You can get ones with <
1nv/rthz input noise. They gave, essentially, zero gate current noise, which
for a bipolar loaded by 1H on its input, might well generate huge amounts of
noise.

[Tim Williams]

"Kevin Aylward" <Extractke...@kevinaylward.co.uk> wrote in message
news:doidnTxYiLITl_rJ...@bt.com...

> Either you are putting them, as you actually claimed, in direct
> parallel, i.e. gate to gate, source to source, drain to drain, or you
> are driving them separately, e.g. individual current setting sources.
>
> If they are in parallel as you claimed, they wont match. Period. They
> will
> run at vastly different currents. With typical manufacturing specs of
> several volts of Vt variations, some devices will be fully off, with the

^^^^^^^^^

> other taking all the current. Period.
>
> Hint: Go and run a SuperSpice test circuit and set one Vt to -1V and
> another
> to -3V, which is way within typically variation specs for jfets.
> Typically a 10:1 ratio in currents results.

^^^^^^^^^^

Kevin,

You're contradicting yourself...

Phil also indicated that this JFET has a 2.5:1 spread, and that he uses
them around Vgs=0, so that the spread is entirely Idss only -- no effect
from Vt except as it relates to Idss.

True, the impact from several transistors being on the "1" end of the
range will be small relative to the current drawn by those on the "2.5"
end (assuming an even distribution in the reel), but with up to ten in
parallel, even that spread gets averaged out. Furthermore, the advantage
is still strictly monotonic: going from N to N+1 devices, even if the
additional unit has 40% the transconductance of the rest (and therefore
about 4% of the total at N=10), the total is still going up, and noise
factor, down. So I don't get what the confusion is.

As for distributions: Phil, I don't suppose you've collected any data
about typical batch or reel distributions from various manufacturers? Do
they tend to match well or not?

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

[Jan Panteltje]

On a sunny day (Sat, 15 Nov 2014 08:10:57 -0000) it happened "Kevin Aylward"
<Extractke...@kevinaylward.co.uk> wrote in
<doidnTxYiLITl_rJ...@bt.com>:

>I don't know your exact circuit.
>
>Either you are putting them, as you actually claimed, in direct parallel,
>i.e. gate to gate, source to source, drain to drain, or you are driving them
>separately, e.g. individual current setting sources.
>
>If they are in parallel as you claimed, they wont match. Period.

Oops:
http://panteltje.com/pub/lighting_a_LED_with_a_candle_hardware_IMG_3605.GIF
http://panteltje.com/pub/lighting_a_LED_with_a_candle_setup_IMG_3607.GIF
http://panteltje.com/pub/lighting_a_LED_with_a_candle_plus_.7_to_-5V_gate_voltage_for_44mV_in_IMG_3608.GIF
http://panteltje.com/pub/lighting_a_LED_with_a_candle_IMG_3604.GIF
http://panteltje.com/pub/lighting_a_LED_with_a_candle_circuit_diagram_with_added_power_MOSFET.gif

>They will
>run at vastly different currents.

possibly.
:-)

I do not remember why I added so many in parallel.
I think it worked better:
http://www.youtube.com/watch?v=hjsgwQs0LTw
http://www.youtube.com/watch?v=oAPAdcq5PtM

[Gerhard Hoffmann]

Am 15.11.2014 um 09:48 schrieb Tim Williams:

> As for distributions: Phil, I don't suppose you've collected any data
> about typical batch or reel distributions from various manufacturers? Do
> they tend to match well or not?

I have measured IDss for about 100 BF862 and nearly all were around
12.x mA. A few at 11 and a few upto 15. I wanted one from the upper
end of the data sheet range. Nothing.
All were from the same tape.


I remember that MPF102s were said to have just in common that they
were n-JFETs, that what remains when everything consistent and
interesting has been selected out.

regards, Gerhard

[Phil Hobbs]

Bill and Kevin seem to be thinking of FETs biased well below I_DSS, in
which case the pinchoff voltage spread will be a problem, but that's not
what I'm writing about, a-tall a-tall. A bootstrap is a glorified
source follower, and mine usually have other bells and whistles, often
including local shunt feedback, a drain bootstrap for the bootstrap FET,
and an op amp controlled current sink to servo V_DS to zero volts.
(Getting low noise in a photodiode front end is easily valuable enough
to pay the freight for these sorts of extras.)

As you say, when you run parallelled JFETs at zero volts G-S, they're
all conducting heavily, so they work fine. The production spread in N
parallelled devices is no worse than in a single device, and
statistically will be somewhat better. (I doubt the spread is really
random, so the improvement probably isn't 1/sqrt(N).)

So if the circuit works OK with random FETs from the bin, with N in
parallel it'll work N times better on average.

IME most BF862s come in at 15 mA +- 3 mA, but I've probably only seen
devices from a few batches. Devices from a single reel seem to be
fairly reliably within 20% of each other, to the point where I've used
them to temperature compensate each other as one does with BJTs.
You do have to allow for the full specified I_DSS spread, of course, or
else use selected devices, which is a huge pain with T&R.

[Kevin Aylward]

">Tim Williams" wrote in message news:m4740o$da6$1...@dont-email.me...

>"Kevin Aylward" <Extractke...@kevinaylward.co.uk> wrote in message
>news:doidnTxYiLITl_rJ...@bt.com...
>> Either you are putting them, as you actually claimed, in direct parallel,
>> i.e. gate to gate, source to source, drain to drain, or you are driving
>> them separately, e.g. individual current setting sources.
>
> If they are in parallel as you claimed, they wont match. Period. They will
> >run at vastly different currents. With typical manufacturing specs of
> >several volts of Vt variations, some devices will be fully off, with the
^^^^^^^^^
> >other taking all the current. Period.
>
>> Hint: Go and run a SuperSpice test circuit and set one Vt to -1V and
>> another
>> to -3V, which is way within typically variation specs for jfets.
>> Typically a 10:1 ratio in currents results.
^^^^^^^^^^
<Kevin,

<You're contradicting yourself...

Err... no. I am approximating, its analog. Its what we do. "Typical" covers
a wide range. A 10:1 for devices supposed to be matched is, essentially, one
of them off. Some fets have 5V Vt variations in their data sheets. I was
trying to give some benefit of doubt for those rarer devices that might be
specked at < 1V variations.

>Phil also indicated that this JFET has a 2.5:1 spread, and that he uses
>them around Vgs=0, so that the spread is entirely Idss only -- no effect
>from Vt except as it relates to Idss.

Er...No. Its is all over the place. Addressed in other post.

Go and run the sims.

[Kevin Aylward]

"Phil Hobbs" wrote in message news:546792C3...@electrooptical.net...

Err.. no. I gave the results of direct paralleling of devices with 0V gate
source voltage, when the devices are in normal operating "saturation"
region. With manufactures specs of several volts of Vt variation, their can
easily be a 10:1 ratio, or more difference in currents. This means that some
of the parallel devices are, essentially useless. Period.

>As you say, when you run parallelled JFETs at zero volts G-S, they're all
>conducting heavily, so they work fine. The production spread in N
>parallelled devices is no worse than in a single device, and statistically
>will be somewhat better. (I doubt the spread is really random, so the
>improvement probably isn't 1/sqrt(N).)

Err no... many of the devices might as well just not be there. Its money
being thrown away.

For a U309, it specks out as a Vt of 1V to 4V variation. In SS, this gets
you 81.3ma and 5.4ma at 0V Vgs and 5V across them. i.e. one might as well
not be there.

>So if the circuit works OK with random FETs from the bin, with N in
>parallel it'll work N times better on average.
>IME most BF862s come in at 15 mA +- 3 mA, but I've probably only seen
>devices from a few batches. Devices from a single reel seem to be fairly
>reliably within 20% of each other,

So, as I said, you have been lucky. This is no way to design for mass
production.

[Phil Hobbs]

Kevin,

You need to go read the BF6862 datasheet, instead of going on about
ancient U309s. The BF962's I_DSS range is 10 to 25 mA, but I've never
seen one above about 18 mA. Its transconductance range at I_DSS is 35
mS min, 45 mS typical.

When you wire JFETs in parallel, at zero volts G-S, they're all running
at I_DSS, and contributing at least 35 mS of transconducance. These are
datasheet parameters with guaranteed limits. From a datasheet POV,
pinchoff voltage doesn't matter at all.

If I take two BF862s from the same reel and parallel them directly, I
get a drain current range that is guaranteed to be between 20 mA and 50
mA, and has a sharply peaked distribution around 25-35 mA. I'm
guaranteed to get at least 70 mS of transconductance, which is well
outside the range for a single device. Ten devices run between 100 and
250 mA, with transconductance of a minimum 350 mS and typically 450 mS.

All those devices are pulling their weight. There will be some
variation in characteristics between amplifiers, but this will be no
larger than with a single JFET, and will generally be smaller due to the
statistics. One does have to design for the high current edge case, to
avoid e.g. saturating the current sink or roasting some resistor, but
that's just normal stuff.

If I need <= 0.5 nV 1-Hz noise, very low leakage current, and low
capacitance, there aren't a lot of alternatives to doing this. It works
fine and involves zero luck.

[John Larkin]

In many circuits, like followers for example, or anything with
ungrounded sources, none of them are likely to be running at their
Idss. Some of them could actually be a bit enhanced. So it's probably
prudent to run them at a current that practically guarantees that none
of the gates will be forward biased. With BF862's, that's not hard...
12 mA per fet should do it. As you say, BF862's are not like your
dad's old jfets. A bit of forward gate bias is usually OK, but some
circuits might care.

I recently did a photodiode bootstrap that used two BF862s in AC
parallel but DC separately biased. Having resistor packs around, that
only added one capacitor overall.

(We run some jfet type gadgets, mostly mesfets and phemts, with
forward gate bias. Mesfets ehnance maybe 50% above Idss, phemts can be
2:1 before the gate current gets dangerous.)

--

John Larkin Highland Technology, Inc

picosecond timing laser drivers and controllers

[John Larkin]

But BF862s are manufactured at Hogwarts Semiconductor.

[John S]

I don't mean to put words in Kevin's mouth, but I'd guess he is
referring to something similar to NXP's BF862 datasheet figure 3 where
it shows that Idss and Vp are related. If you connect g-s and measure
Idss, the graph gives Vp. Also, according to the data sheet, Vp can
range from -.3 to -1.2V. So, putting it all together, Idss can range
from 0 (silly) to 32mA.

Am I incorrectly interpreting the data sheet?

JohnS

[Phil Hobbs]

About 2/3 of my recent ones have op amps forcing them to run at IDSS, so
everybody's bias conditions are the same. The other ones run at 10-12
mA, which I agree is a good choice. Usually the customer wants to use
some gross huge PD at low current, and sometimes that's even the right
answer. ;)

My most recent one was 1600 pF and 20 nA full scale. The interesting
thing with that one was that it was a battery powered instrument, so the
measurement had to be made within about 0.5 seconds of turning the thing
on. Without the op amp, the thermal offset voltage transient in the
bootstrap was enough to cause serious measurement error due to the
differentiating action of the capacitance. Usually that's not a worry.

> I recently did a photodiode bootstrap that used two BF862s in AC
> parallel but DC separately biased. Having resistor packs around, that
> only added one capacitor overall.

I usually use some extra circuitry to get the gain closer to 1.000.
Sometimes the actual measured gain is better than 0.999, which is hard
to do with a resistor in the source. The source impedance is around 25
ohms for one FET, so getting to 0.999 would need a bias resistor of 25k
to -250V.

Some shunt feedback (like the PNP wraparound trick for 78xx regulators)
will reduce the source impedance a lot, so a resistor can work OK, or
else a BJT current source. It's important that the source bias current
be sub-Poissonian, or it'll dominate the noise. The nice thing about
shunt feedback is that the FET runs with a bit of voltage gain, so that
the loop suppresses the wraparound's noise.

> (We run some jfet type gadgets, mostly mesfets and phemts, with
> forward gate bias. Mesfets ehnance maybe 50% above Idss, phemts can be
> 2:1 before the gate current gets dangerous.)

You've mentioned that before--I've been meaning to try it. I have a few
hundred pHEMTs of various kinds in stock.

[Phil Hobbs]

They're related from the device physics and modelling POVs, of course,
but I'm talking about guaranteed data sheet parameters. Kevin was
claiming that some devices wouldn't pull their weight, and that's just
not so unless you're pretty far from V_GS=0. (Maybe his circuits are
all current-starved, or something.)

If you look at Fig 7, you'll see that the max, min, and typical curves
all have about the same slope at VGS=0, i.e. they have very similar
transconductances at I_DSS. I actually sucked in the curves using
Datathief, and the transconductances are (top to bottom) 39 mS, 39 mS,
and 32 mS. (So their lower-limit curve is actually slightly out of spec.)

From crunching the data from the curves in Fig 8, it turns out that the
transconductance is fractionally higher at V_DS ~ 2.5V. That's where I
usually like to run them, because it reduces both power dissipation and
gate leakage.

It's the transconductance that you mostly care about, because that's
what sets all the stage gains, bandwidths, and governs the noise
statistics. Each FET contributes a noise current of e_N * g_M, and the
results add RMS fashion, so if the transconductances are similar, the
noise voltage goes down as 1/sqrt(N).

[John S]

Now I'm really lost. Are you indicating that typical values are
guaranteed parameters?

> If you look at Fig 7, you'll see that the max, min, and typical curves
> all have about the same slope at VGS=0, i.e. they have very similar

Fig 7 is typical data, it says beneath the graph. So the max and min are
typical max and min.

[Phil Hobbs]

No, I'm not saying the whole curves are guaranteed. What's guaranteed is that 35 mS minimum transconductance at 0V GS, and that's all I need to establish the point at issue.

Cheers

Phil Hobbs

[Jan Panteltje]

On a sunny day (Sun, 16 Nov 2014 12:53:36 -0800 (PST)) it happened Phil Hobbs
<pcdh...@gmail.com> wrote in
<24576fbc-810d-40ee...@googlegroups.com>:

Phil, I 100% agree, the gain adds up.
This is why I had so many in parallel in the 'lighting a LED with a candle' project.

For RF if you have more in parallel, the noise goes down as you pointed out.
We should always see things in the perspective of the application.
Slimulations are often a distraction from reality.
In fact those are ONLY useful if you already know what you are doing,
know what to look for, and HAVE the real hardware to check against.
That is my expericence, and again very recent too with my QAM modulator driver.
Its great to see filter curves...
But I still measure those before and after the slimulations.