LTspice subckt model for AD734
JosephKK
I picked up the macromodel from AD(TI) for this IC. I
am using the manual to try to figure out how to
incorporate the model in a circuit idea, but i hit up
against errors. This one has me baffled though.
The error i am getting is:
"Port(pin) count mismatch between the definition of 'ad734.cir' and instance xu1. The instance has more connections than the definition."
I don't understand why i am getting this error.
I would like to better understand how to make this work.
Here is example test circuit:
+++++
Version 4
SHEET 1 2476 680
WIRE 800 -1120 688 -1120
WIRE 688 -1088 688 -1120
WIRE 800 -1088 800 -1120
WIRE 208 -1008 112 -1008
WIRE 0 -992 0 -1040
WIRE 208 -992 208 -1008
WIRE 640 -896 448 -896
WIRE 800 -896 800 -1008
WIRE 800 -896 640 -896
WIRE 208 -864 208 -912
WIRE 320 -864 320 -1040
WIRE 320 -864 208 -864
WIRE 0 -848 0 -912
WIRE 112 -848 112 -1008
WIRE 112 -848 0 -848
WIRE 0 -816 0 -848
WIRE 448 -608 448 -896
WIRE 496 -608 448 -608
WIRE 704 -608 704 -656
WIRE 704 -608 640 -608
WIRE 496 -576 464 -576
WIRE 656 -576 640 -576
WIRE 464 -544 464 -576
WIRE 464 -544 432 -544
WIRE 496 -544 464 -544
WIRE 672 -544 640 -544
WIRE 672 -528 672 -544
WIRE 816 -528 672 -528
WIRE 432 -512 432 -544
WIRE 464 -512 464 -544
WIRE 496 -512 464 -512
WIRE 672 -512 672 -528
WIRE 672 -512 640 -512
WIRE 464 -480 464 -512
WIRE 496 -480 464 -480
WIRE 768 -480 768 -608
WIRE 768 -480 640 -480
WIRE 192 -448 192 -480
WIRE 192 -448 48 -448
WIRE 496 -448 192 -448
WIRE 656 -448 640 -448
WIRE 464 -416 464 -480
WIRE 496 -416 464 -416
WIRE 672 -416 640 -416
WIRE 672 -304 672 -416
WIRE 704 -304 704 -320
WIRE 704 -304 672 -304
WIRE 768 -304 768 -480
WIRE 768 -256 768 -304
WIRE 48 208 48 -448
WIRE 48 368 48 288
FLAG 48 368 0
FLAG 688 -1088 0
FLAG 0 -1040 VP
FLAG 320 -1040 VN
FLAG 0 -816 0
FLAG 704 -656 VP
FLAG 704 -320 VN
FLAG 768 -256 0
FLAG 432 -512 0
FLAG 192 -480 Ain
FLAG 640 -896 C0
SYMBOL voltage 48 192 R0
WINDOW 3 46 82 Left 0
WINDOW 123 46 50 Left 0
WINDOW 39 47 110 Left 0
SYMATTR Value SINE(0 1 220 0 0 0)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=1 Cpar=100p
SYMATTR InstName V1
SYMBOL voltage 800 -1104 R0
WINDOW 3 43 69 Left 0
WINDOW 123 43 41 Left 0
WINDOW 39 44 95 Left 0
SYMATTR Value SINE(0 1 10.7M 0 0 0)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=5 Cpar=1p
SYMATTR InstName V5
SYMBOL voltage 0 -1008 R0
SYMATTR InstName V7
SYMBOL voltage 208 -1008 R0
SYMATTR InstName V8
SYMBOL AD734 576 -560 R0
SYMATTR InstName U1
SYMATTR Prefix X1 X2 U0 U1 U2 Y1 Y2 VN ER Z2 Z1 W DD VP
SYMATTR SpiceModel ad734.cir
SYMBOL cap 704 -592 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL cap 704 -288 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C3
SYMATTR Value 100n
TEXT 48 -1088 Left 0 !.subckt ad734.cir
TEXT -32 392 Left 0 !.tran 10m
=====
Here is the downloaded macromodel:
+++++
* AD734 SPICE Macro-model 4/92, Rev. B
* AAG / PMI
*
* Revision History:
* Removed input signal current compensation: GX1,GY1,GZ1
* Added Isy vs. Vsy
*
* Copyright 1992 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* X1
* | X2
* | | UO
* | | | U1
* | | | | U2
* | | | | | Y1
* | | | | | | Y2
* | | | | | | | VN
* | | | | | | | | ER
* | | | | | | | | | Z2
* | | | | | | | | | | Z1
* | | | | | | | | | | | W
* | | | | | | | | | | | | DD
* | | | | | | | | | | | | | VP
* | | | | | | | | | | | | | |
.SUBCKT AD734 10 11 49 50 51 20 21 200 58 31 30 77 54 100
*
EREF 300 0 POLY(2) 100 0 200 0 (0,0.5,0.5)
*
* X INPUT STAGE & POLE AT 40 MHz
*
CINX 10 11 2E-12
IBX1 10 0 DC 50E-9
IBX2 11 0 DC 50E-9
EOSX 12 10 POLY(1) 18 300 15E-3 1
RX1 12 13 25E3
RX2 13 11 25E3
*
GX1 300 14 12 11 1E-6
RX3 14 300 9.995E5
CX1 14 300 3.9809E-15
VX1 100 15 DC 3.1875
DX1 14 15 DX
VX2 16 200 DC 3.1875
DX2 16 14 DX
*
* X INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMX 17 300 13 300 56.234
RCMX1 17 18 1E6
CCMX 17 18 3.9789E-12
RCMX2 18 300 1
*
* Y INPUT STAGE & POLE AT 40 MHz
*
CINY 20 21 2E-12
IBY1 20 0 DC 50E-9
IBY2 21 0 DC 50E-9
EOSY 22 20 POLY(1) 28 300 10E-3 1
RY1 22 23 25E3
RY2 23 21 25E3
*
GY1 300 24 22 21 1E-6
RY3 24 300 9.995E5
CY1 24 300 3.9809E-15
VY1 100 25 DC 3.1875
DY1 24 25 DX
VY2 26 200 DC 3.1875
DY2 26 24 DX
*
* Y INPUT STAGE COMMON-MODE REJECTION AND ZERO 80 kHz
*
ECMY 27 300 23 300 56.234
RCMY1 27 28 1E6
CCMY 27 28 1.9895E-12
RCMY2 28 300 1
*
* Z INPUT STAGE & POLE AT 40 MHz
*
CINZ 30 31 2E-12
IBZ1 30 0 DC 50E-9
IBZ2 31 0 DC 50E-9
EOSZ 32 30 POLY(1) 38 300 20E-3 1
RZ1 32 33 25E3
RZ2 33 31 25E3
*
GZ1 300 34 32 31 1E-6
RZ3 34 300 1E6
CZ1 34 300 3.9789E-15
VZ1 100 35 DC 3.1875
DZ1 34 35 DX
VZ2 36 200 DC 3.1875
DZ2 36 34 DX
*
* Z INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMZ 37 300 33 300 56.234
RCMZ1 37 38 1E6
CCMZ 37 38 3.9789E-12
RCMZ2 38 300 1
*
* DENOMINATOR CONTROL & INTERNAL REFERENCE
*
QU1 100 49 50 QNU
RU1 50 51 28E3
*
VU 100 52
QU2 52 0 53 QNU
RU2 53 54 0.001
IU 53 200 DC 10E-6
FU1 300 55 VU 1.01
RU3 55 300 1E6
*
VR1 57 200 DC 8
QR 59 57 58 QPU
RR 57 58 1E5
VR2 59 200
FU4 300 56 VR2 1
RU4 56 300 28E3
*
EU 60 300 POLY(3) 50 51 55 300 56 300 (0,1.0101,1,1.0101)
RU5 60 300 1E6
*
* 250 MHz MULTIPLIER CORE
*
EXY 46 300 POLY(2) 14 300 24 300 (0,0,0,0,1)
RXY 46 300 1E6
GXY 300 47 46 300 1
GU 47 300 POLY(2) 60 300 47 300 (0,0,0,0,1)
RU 47 300 1E12
CU 47 300 6.65E-9
EW 48 300 POLY(2) 47 300 34 300 (0,1,-1)
RW 48 300 1E6
*
* OUTPUT AMP BUFFER
*
GW 64 300 48 300 1
QW1 100 0 61 QNW
QW2 200 0 62 QPW
QW3 63 62 64 QNW
QW4 65 61 64 QPW
RW1 100 63 1
RW2 65 200 1
IW1 100 62 DC 100E-6
IW2 61 200 DC 100E-6
VW1 100 66 DC 10
DW1 66 63 DX
VW2 67 200 DC 10
DW2 65 67 DX
*
* OUTPUT AMP GAIN STAGE
*
GW1 300 68 100 63 1
GW2 68 300 65 200 1
RW3 68 300 1.38E3
CW1 68 300 19E-9
VW3 100 69 DC 3.8
DW3 68 69 DX
VW4 70 200 DC 3.8
DW4 70 68 DX
*
* TRANSIENT SUPPLY CURRENT COMPENSATION
*
DCC1 80 100 DX
GCC 0 80 48 300 1
DCC2 0 80 DX
DEE1 81 0 DX
GEE 81 0 300 48 1
DEE2 200 81 DX
*
* POLE AT 17.5 MHz
*
GW3 300 71 68 300 1E-6
RW4 71 300 1E6
CW2 71 300 9.0946E-15
*
IDC 100 200 DC 4.0125E-3
RDC1 100 78 3.2E3
RDC2 78 200 3.2E3
DO1 100 72 DX
GO1 72 200 76 71 25E-3
DO2 200 72 DY
DO3 100 73 DX
GO2 73 200 71 76 25E-3
DO4 200 73 DY
VSC1 74 76 DC 0.4
DSC1 71 74 DX
VSC2 76 75 DC 0.4
DSC2 75 71 DX
GO3 76 100 100 71 25E-3
GO4 200 76 71 200 25E-3
RO1 100 76 40
RO2 76 200 40
LO 76 77 100E-9
*
* MODELS USED
*
.MODEL QNU NPN (BF=100 IS=1E-16)
.MODEL QPU PNP (BF=100 IS=1E-16)
.MODEL QNW NPN (BF=1E9 IS=1E-15)
.MODEL QPW PNP (BF=1E9 IS=1E-15)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS AD734
=====
Here is the symbol i created:
+++++
Version 4
SymbolType CELL
RECTANGLE Normal 64 187 -80 -85
TEXT -58 -106 Left 0 AD734
SYMATTR ModelFile AD734.cir
SYMATTR Prefix U
SYMATTR SpiceModel AD734
PIN -80 -48 LEFT 8
PINATTR PinName X1
PINATTR SpiceOrder 1
PIN -80 -16 LEFT 8
PINATTR PinName X2
PINATTR SpiceOrder 2
PIN -80 16 LEFT 8
PINATTR PinName U0
PINATTR SpiceOrder 3
PIN -80 48 LEFT 8
PINATTR PinName U1
PINATTR SpiceOrder 4
PIN -80 80 LEFT 8
PINATTR PinName U2
PINATTR SpiceOrder 5
PIN -80 112 LEFT 8
PINATTR PinName Y1
PINATTR SpiceOrder 6
PIN -80 144 LEFT 8
PINATTR PinName Y2
PINATTR SpiceOrder 7
PIN 64 144 RIGHT 8
PINATTR PinName VN
PINATTR SpiceOrder 8
PIN 64 112 RIGHT 8
PINATTR PinName ER
PINATTR SpiceOrder 9
PIN 64 80 RIGHT 8
PINATTR PinName Z2
PINATTR SpiceOrder 10
PIN 64 48 RIGHT 8
PINATTR PinName Z1
PINATTR SpiceOrder 11
PIN 64 16 RIGHT 8
PINATTR PinName W
PINATTR SpiceOrder 12
PIN 64 -16 RIGHT 8
PINATTR PinName DD
PINATTR SpiceOrder 13
PIN 64 -48 RIGHT 8
PINATTR PinName VP
PINATTR SpiceOrder 14
=====
Helmut Sennewald
> From: "JosephKK" <quiett...@yahoo.com>
> Newsgroups: sci.electronics.design
> Sent: Sunday, April 04, 2010 3:37 AM
> Subject: LTspice subckt model for AD734
> I picked up the macromodel from AD(TI) for this IC. I
> am using the manual to try to figure out how to
> incorporate the model in a circuit idea, but i hit up
> against errors. This one has me baffled though.
> The error i am getting is:
> "Port(pin) count mismatch between the definition of 'ad734.cir' and
> instance xu1.
> The instance has more connections than the definition."
> I don't understand why i am getting this error.
> I would like to better understand how to make this work.
Hello Joseph,
1. The Prefix in the symbol has to be always X for subcircuits.
Don't forget to re-instantiate the symbol in the schematic after this
change.
2. Delete this SPICE-directive ".subckt..." in your schematic.
3. The value of the voltage sources should be 15.
4. The multiplier M or m means milli. Maybe you want MEG or meg.
5. After you have fixed this, you may encounter problems with convergence.
You have to add the following SPICE-directives to get it working.
.options tseed=1n
.options method=gear
.options cshunt=7e-15
Unfortunately the ladder has already some impact on the bandwidth
of the AD737 at 10MHz.
If you just need a multiplier for some kind of higher level simulation,
then better use the behavioral sources Bv or Bi.
A multiplier:
V=V(nodea)*V(nodeb)
You should consider to become a member of the LTspice group.
An example with the AD734 has been already there in the group's
Files-section. Files > Lib > AD734
http://tech.groups.yahoo.com/group/LTspice/
To become a member is very easy if you create an email-account
in Yahoo before.
Best regards,
Helmut
JosephKK
>> ----- Original Message -----
>> From: "JosephKK" <quiett...@yahoo.com>
>> Newsgroups: sci.electronics.design
>> Sent: Sunday, April 04, 2010 3:37 AM
>> Subject: LTspice subckt model for AD734
>> I picked up the macromodel from AD(TI) for this IC. I
>> am using the manual to try to figure out how to
>> incorporate the model in a circuit idea, but i hit up
>> against errors. This one has me baffled though.
>> The error i am getting is:
>> "Port(pin) count mismatch between the definition of 'ad734.cir' and
>> instance xu1.
>> The instance has more connections than the definition."
>> I don't understand why i am getting this error.
>> I would like to better understand how to make this work.
>
>
>Hello Joseph,
>
>1. The Prefix in the symbol has to be always X for subcircuits.
>Don't forget to re-instantiate the symbol in the schematic after this
>change.
reinstantiating was easy enough
>
>2. Delete this SPICE-directive ".subckt..." in your schematic.
ok.
>
>3. The value of the voltage sources should be 15.
Fixed
>
>4. The multiplier M or m means milli. Maybe you want MEG or meg.
Changed
>
>5. After you have fixed this, you may encounter problems with convergence.
>You have to add the following SPICE-directives to get it working.
After i get operating point to go. Floating nodes.
>
>.options tseed=1n
>.options method=gear
>.options cshunt=7e-15
>
>Unfortunately the ladder has already some impact on the bandwidth
>of the AD737 at 10MHz.
Mostly an output amplifier slew rate limitation. I can dodge that well enough.
>
>If you just need a multiplier for some kind of higher level simulation,
>then better use the behavioral sources Bv or Bi.
>A multiplier:
>V=V(nodea)*V(nodeb)
I was trying to get a bit further away from that, but that is inside
the macromodel anyway. I intended to create a buildable circuit.
>
>You should consider to become a member of the LTspice group.
>An example with the AD734 has been already there in the group's
>Files-section. Files > Lib > AD734
>http://tech.groups.yahoo.com/group/LTspice/
>To become a member is very easy if you create an email-account
>in Yahoo before.
Sorry, they pissed me off. I couldn't read, search, or do anything
before signing up; i understand signing up to post though.
I have problems with managing all the damn passwords i use as is.
Not the way to attract friends.
>
>Best regards,
>Helmut
>
>
Jim Thompson
<excret...@invalid.invalid> wrote:
>Same here...
Poor babies :-)
I subscribed to receive the digests, and often post answers from
there, without having to use the website.
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The only thing bipartisan in this country is hypocrisy
JosephKK
>On Tue, 06 Apr 2010 12:40:00 -0700, Fred Abse
><excret...@invalid.invalid> wrote:
>
>>On Tue, 06 Apr 2010 05:55:53 -0700, JosephKK wrote:
>>
>>> On Sun, 4 Apr 2010 12:42:21 +0200, "Helmut Sennewald" <helmuts...@t-online.de> wrote:
>>
>>>>You should consider to become a member of the LTspice group.
>>>>An example with the AD734 has been already there in the group's
>>>>Files-section. Files > Lib > AD734
>>>>http://tech.groups.yahoo.com/group/LTspice/
>>>>To become a member is very easy if you create an email-account
>>>>in Yahoo before.
>>>
>>> Sorry, they pissed me off. I couldn't read, search, or do anything
>>> before signing up; i understand signing up to post though.
>>> I have problems with managing all the damn passwords i use as is.
>>> Not the way to attract friends.
>>
>>
>>Same here...
>
>Poor babies :-)
>
>I subscribed to receive the digests, and often post answers from
>there, without having to use the website.
>
> ...Jim Thompson
Understandable, i avoid blogs like the pox they are.
volkerk
I have a similar problem using the PLL-IC CD4046 model.
The exact error message is:
"
Port(pin) count mismatch between the definition of subcircuit "cd4046" and
instance: "xu1"
The instance has fewer connection terminals than the definition.
"
The Prefix in the symbol is "X" as should be, and i think i used the right
number of pins. Deleting the ".subckt" statement doesn't seem like a
solution to me, as this is what links to the symbol as far as i understood
(am i wrong?).
But see yourself:
######### CD4046 definition ############
* Taken from: mix_misc.lib
* Library of Miscellaneous Mixed Analog Models
* Copyright OrCAD, Inc. 1998 All Rights Reserved.
.subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
+ r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
+ Rin=1Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10
+ Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
* Rin = VCO Input Resistace
* S1 = Voltage Limiter linear slope
* S2 = Voltage Limiter non-linear slope
* Vx = Input threshold voltage (between S1 and S2)
* Kb = Arbitrary constant to adjust the value of the conversion gain
(transimpedance gain)
* Vfree= Frequency dependent constant in Emult
* Kc = Negative inverse amplitude of the square wave
* Vt = Trigger voltage of Schmitt trigger (not used)
* Vxqr = Amplitude of square wave (not used)
* M1 = Current mirror multiplier to adjust oscillator frequency
* M2 = Current mirror multiplier to adjust oscillator frequency
* Preliminary model still under development based on Natinal Semiconductor
CD4046BM
* RAPerez 9/98
* Phase detector section
U1 INVA(4) DPWR DGND sigin compin isigin icompin
+ isigin icompin clk1 clk2
+ INVA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL INVA_TIMING UGATE
U2 XOR DPWR DGND isigin icompin xorout
+ XOR_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL XOR_TIMING UGATE
***tplhty=20n tphlty=20n
U3 NAND(2) DPWR DGND q1 q2 pclr
+ NAND_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL NAND_TIMING UGATE (tplhty=1n tphlty=1n)
U4 DFF(1) DPWR DGND $D_HI clr clk1 $D_HI q1 qb1
+ DFF1_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DFF1_TIMING UEFF tppcqlhty=4n tppcqhlty=4n tpclkqlhty=4n
tpclkqhlty=4n
U5 DFF(1) DPWR DGND $D_HI clr clk2 $D_HI q2 qb2
+ DFF2_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DFF2_TIMING UEFF tppcqlhty=5n tppcqhlty=5n tpclkqlhty=5n
tpclkqhlty=5n
U7 BUFA(2) DPWR DGND fq1 fq2 s1 s2
+ BUFA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL BUFA_TIMING UGATE
ST2 vdd phcmpii s1 0 swt
SB2 phcmpii vss s2 0 swt
.model swt VSWITCH (ROFF=2G RON=10m VOFF=0.8 VON=3.0)
U6 AND(2) DPWR DGND pclr reset clr
+ AND_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL AND_TIMING UGATE
Ureset STIM(1,1) DPWR DGND
+ reset
+ IO_HCT
+ +0s 0
+ 2ns 1
+ 1s 1
U8 NOR(2) DPWR DGND fq1 fq2 norout
+ NOR_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL NOR_TIMING UGATE
U9 ANDA(2,2) DPWR DGND q1 od1 q2 od2 fq1 fq2
+ ANDA_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL ANDA_TIMING UGATE
U10 DLYLINE DPWR DGND q1 od1
+ DLY_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U11 DLYLINE DPWR DGND q2 od2
+ DLY_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_TIMING UDLY dlyty=12n
U12 BUFA(3) DPWR DGND norout xorout vcosqr phpls phcmpi vcoout
+ BUFB_TIMING IO_HCT
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL BUFB_TIMING UGATE
* VCO Section
Rin vcoin vss {Rin}
Evlim vlim 0 value={if(v(vcoin,vss)<v(vdd,vss),
+
S1*v(vcoin,vss),S2*(v(vcoin,vss)-v(vdd,vss))+v(vdd,vss))}
Rvlim vlim 0 1Meg
Emult mix 0 value={v(vlim)*Kb+Vfree}
*Hmult mix 0 poly(1) Vcm 1.44 0.586
Rmult mix 0 1
Edemout demout 0 table={ 200Meg*v(vcoin,demout)*v(off) } (-20,-20) (20,20)
Rdemout demout 0 1Meg
ER2 ir2 0 vdd ir2 200Meg
VR2 ir2 r2
ER1 ir1 0 mix ir1 200Meg
VR1 ir1 r1
Eosclg adj 0 table={abs((V(vdd)/I(VR2))/(V(mix)/I(VR1)))}
+ (0.5,1.43) (1,1.6) (10,1.04) (50,0.67) (100,0.84) (101,1)
+ (102,1) (1000,1)
Radj adj 0 1G
*GIM ce1 0 value={(M1*I(VR1)+M2*I(VR2))*Kc*V(sqrrc)}
GIM ce1 0 value={(M1*I(VR1)*V(adj)+M2*I(VR2))*Kc*V(sqrrc)}
*GIM ce1 0 value={(24*I(VR1)+3.067*I(VR2))}
Vcext ce2 0
Cstray ce1 ce2 6p
Rcext ce1 ce2 1T
Etrngl trngl 0 ce1 0 1
Rtrngl trngl 0 1Meg
Esqr sqr 0 value={-10Meg*V(trngl)+1.2Meg*V(sqrrc)}
Rsqr sqr sqrrc 0.1T
Csqr sqrrc 0 10f
Dsqr1 sqrrc 13 Diode
Vsqr1 13 0 {Vx}
Dsqr2 14 sqrrc Diode
.model Diode D (IS=10u N=0.01 CJO=80f)
*.model Diode D (IS=10u N=0.001 CJO=80f)
Vsqr2 14 0 {-Vx}
Ipls 0 sqrrc pwl 0 0 10n 0 20n 0.01u 0.1u 0.01u 0.12u 0 1 0
Evcoout vcosqr 0 table={5.0*v(off)*(v(sqrrc)/Vx)} (0.1,0.1) (4.5,4.5)
*Rvcoout vcosqr vcosqr1 1
**Et 7 0 TABLE {-10k*V(trngl)+1.2k*V(sqrrc)} (-2,-10) (2,10)
*Ipls 0 sqrrc pwl 0 0 10n 0 20n 1u 0.1u 1u 0.12u 0 1 0
*Et 7 0 value={table({-10Meg*V(trngl)+1.2Meg*V(sqrrc)},-10,{-Vx},10,{Vx})}
*Ro 7 sqrrc 100
*Co sqrrc 0 100p
*Est sqrrc o VALUE={table({2000k*(V(st)-V(trngl))},-2,{-Vx},2,{Vx})}
*Rst1 sqrrc st 8.8k
*Rst2 st 0 1.2k
*Cst st 0 200p ic=-10
Rinhbt inhibit 0 1Meg
Eoff off 0 value={if(v(inhibit)<0.9,1.0,0.0)}
Roff off 0 1Meg
Dzener vss zener znr
Rzener vss zener 1G
.model znr D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=160p M=.5484
+ Vj=.75 Fc=.5 Isr=1.8n Nr=2 Bv=5.2 Ibv=27.721m Nbv=1.1779
+ Ibvl=1.1646m Nbvl=21.894 Tbv1=176.47u)
.ends
*$
######### CD4046 symbol ############
Version 4
SymbolType BLOCK
LINE Normal -32 -32 32 -32
LINE Normal 16 16 32 16
LINE Normal 16 80 16 16
RECTANGLE Normal 32 80 -32 -96
TEXT -16 -64 Left 0 PC
TEXT -25 -8 Left 0 VCO
WINDOW 38 2 93 Center 0
WINDOW 3 -1 -107 Center 0
SYMATTR SpiceModel CD4046.lib
SYMATTR Value CD4046
SYMATTR Prefix X
SYMATTR Value2 CD4046
PIN -32 -64 RIGHT 8
PINATTR PinName SIG_IN
PINATTR SpiceOrder 1
PIN 32 -64 LEFT 8
PINATTR PinName PC2_OUT
PINATTR SpiceOrder 2
PIN 32 -80 LEFT 8
PINATTR PinName PC1_OUT
PINATTR SpiceOrder 3
PIN 32 -48 LEFT 8
PINATTR PinName PCP_OUT
PINATTR SpiceOrder 4
PIN -32 -80 RIGHT 8
PINATTR PinName COMP_IN
PINATTR SpiceOrder 5
PIN -32 48 RIGHT 8
PINATTR PinName VCO_IN
PINATTR SpiceOrder 6
PIN -32 16 RIGHT 8
PINATTR PinName R1
PINATTR SpiceOrder 7
PIN -32 32 RIGHT 8
PINATTR PinName R2
PINATTR SpiceOrder 8
PIN -32 -16 RIGHT 8
PINATTR PinName C1A
PINATTR SpiceOrder 9
PIN -32 0 RIGHT 8
PINATTR PinName C1B
PINATTR SpiceOrder 10
PIN 32 -16 LEFT 8
PINATTR PinName VCO_OUT
PINATTR SpiceOrder 11
PIN 32 0 LEFT 8
PINATTR PinName DEM_OUT
PINATTR SpiceOrder 12
PIN -32 64 RIGHT 8
PINATTR PinName INH
PINATTR SpiceOrder 13
PIN 32 32 LEFT 8
PINATTR PinName ZEN
PINATTR SpiceOrder 14
PIN 32 48 LEFT 8
PINATTR PinName VDD
PINATTR SpiceOrder 15
PIN 32 64 LEFT 8
PINATTR PinName VSS
PINATTR SpiceOrder 16
######### test circuit ############
Version 4
SHEET 1 880 680
WIRE 400 32 64 32
WIRE 64 96 64 32
WIRE 192 96 64 96
WIRE -16 112 -160 112
WIRE 192 112 48 112
WIRE 416 112 256 112
WIRE 496 128 256 128
WIRE 192 160 128 160
WIRE 400 160 400 32
WIRE 400 160 256 160
WIRE 64 176 64 160
WIRE 192 176 64 176
WIRE 192 192 48 192
WIRE 192 224 64 224
WIRE 352 224 256 224
WIRE 192 240 160 240
WIRE 304 240 256 240
WIRE 160 304 160 240
WIRE 304 304 304 240
WIRE 304 304 160 304
WIRE 352 304 304 304
WIRE 304 320 304 304
WIRE 64 352 64 224
WIRE 128 352 64 352
WIRE 192 352 128 352
WIRE 208 352 192 352
WIRE 416 352 416 112
WIRE 416 352 288 352
WIRE 192 368 192 352
WIRE 128 400 128 352
WIRE 192 464 192 448
WIRE 128 544 128 464
WIRE 160 544 128 544
WIRE 192 544 192 528
WIRE 192 544 160 544
WIRE 160 560 160 544
FLAG 160 560 0
FLAG 304 320 0
FLAG 496 208 0
FLAG -32 192 0
FLAG -160 192 0
SYMBOL res 304 336 R90
WINDOW 0 4 56 VBottom 0
WINDOW 3 28 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 33k
SYMBOL cap 176 464 R0
SYMATTR InstName C1
SYMATTR Value 10µ
SYMBOL voltage 352 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 64 176 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 1.2n
SYMBOL cap 112 400 R0
SYMATTR InstName C3
SYMATTR Value 1µ
SYMBOL res 176 352 R0
SYMATTR InstName R2
SYMATTR Value 330
SYMBOL res 480 112 R0
SYMATTR InstName R3
SYMATTR Value 2k
SYMBOL res 64 176 R90
WINDOW 0 4 56 VBottom 0
WINDOW 3 28 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 8.2k
SYMBOL voltage -160 96 R0
WINDOW 3 -242 131 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(-1 1 0 1n 1n 1.1u 2.2u)
SYMATTR InstName V2
SYMBOL cap 48 96 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL CD4046 224 176 R0
SYMATTR InstName U1
TEXT -408 584 Left 0 !.tran 100ms
######### END ############
---------------------------------------
Posted through http://www.Electronics-Related.com
Jim Thompson
<volkerkible@n_o_s_p_a_m.gmx.net> wrote:
>Dear Folks,
>
>I have a similar problem using the PLL-IC CD4046 model.
>
>The exact error message is:
>"
>Port(pin) count mismatch between the definition of subcircuit "cd4046" and
>instance: "xu1"
>The instance has fewer connection terminals than the definition.
>"
>
>The Prefix in the symbol is "X" as should be, and i think i used the right
>number of pins. Deleting the ".subckt" statement doesn't seem like a
>solution to me, as this is what links to the symbol as far as i understood
>(am i wrong?).
>
>But see yourself:
>
>######### CD4046 definition ############
>
>* Taken from: mix_misc.lib
>* Library of Miscellaneous Mixed Analog Models
>* Copyright OrCAD, Inc. 1998 All Rights Reserved.
Syntax error, the definition/"declaration" must be as (note the
dotSUBCKT):
.SUBCKT MODELNAME PINLIST
|
GUTS
|
.ENDS
(Note the dotENDS)
The "instantiation" must be as
Xnnn NODELIST MODELNAME
"NODELIST" must be of the same number of connections as "PINLIST",
otherwise you get the "count mismatch" error message.
>
>subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
>+ r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
>+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
[snip]
>model znr D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=160p M=.5484
>+ Vj=.75 Fc=.5 Isr=1.8n Nr=2 Bv=5.2 Ibv=27.721m Nbv=1.1779
>+ Ibvl=1.1646m Nbvl=21.894 Tbv1=176.47u)
>
>ends
>*$
>
>######### CD4046 symbol ############
>
>Version 4
>SymbolType BLOCK
>LINE Normal -32 -32 32 -32
[snip]
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
volkerk
Unluckily the missing dots were not the problem, as they are at the right
places in my file - they must have gotten lost somewhere while posting the
file contents to this thread.
I looked up in the netlist of my test file, and the "instantiation" is as
follows:
"XU1 N003 N004 NC_01 N005 N001 N009 N008 NC_02 N006 N007 N001 NC_03 0 NC_04
N010 0 CD4046
" (number of connections: 16)
Are there no not connected nodes (NC_xx) allowed?
For reference: The model's "portlist" is as follows:
".subckt CD4046 sigin phcmpii phcmpi phpls compin vcoin
+ r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
+ Rin=1Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10
+ Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
" (number of ports: 16 if i count right???)
And there are 16 pins defined in the Symbol.
I also tried to make two more pins in case the "OPTIONAL:" field in the
model's "header" also counts as ports (what i think is not the case) - i
got the same error message.
Can it be something else? I'm really a bit lost.
Jim Thompson
The pin/node count matches. Comment out the "OPTIONAL:" line and see
what happens.
Jim Thompson
<excret...@invalid.invalid> wrote:
>It appears that it is necessary to include the whole Orcad mix_misc
>library, plus other libraries which mix_misc references.
>
>I don't like libraries that require other libraries. Stinks of
>programmers' methods. Change one thing and break lots of others.
>
>Also, the Orcad libraries include syntax that LTSpice doesn't understand.
>
>Major rewrite necessary.
OrCAD (and PSpice, for that matter) can utilize global power and
ground nodes as a means to keeping schematics from becoming a jungle
of wires.
You _could_ learn to make your own libraries (I do ;-)
Jim Thompson
Or simply copy-and-paste for specialty items, like my D2A part that
bridges between digital environment parts (e.g. 74HC stuff) to a
specific analog environment:
*******************************************************************
* LOGIC to ANALOG Translator
.SUBCKT D2A IN OUT $G_DPWR $G_DGND PARAMS: VH=3.3V VL=0V TRF=10ns
X_HB1_UT1A IN INV $G_DPWR $G_DGND 74HC04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
**
E1 N_2 0 VALUE {LIMIT(V(N_1),-1,+1)}
R2 N_2 0 10K
G2 N_1 0 N_1 N_2 1
R1 N_1 0 10K
C1 0 N_1 {1.35375*TRF/160}
R3 OUT 0 10K
E2 OUT 0 VALUE {(VL-VH)/2*SIN(1.570796*V(N_2, 0))+(VH+VL)/2}
G1 0 N_1 VALUE {(V(INV,0)-2.5)/250}
RINN INV 0 1G
*******************************************************************
Jim Thompson
<excret...@invalid.invalid> wrote:
>On Fri, 08 Oct 2010 12:43:04 -0700, Jim Thompson wrote:
>
>> On Fri, 08 Oct 2010 12:17:08 -0700, Fred Abse
>> <excret...@invalid.invalid> wrote:
>>
>>>On Thu, 07 Oct 2010 09:04:59 -0700, Jim Thompson wrote:
>>>
>>>> On Thu, 07 Oct 2010 07:50:54 -0500, "volkerk"
>>>> <volkerkible@n_o_s_p_a_m.n_o_s_p_a_m.gmx.net> wrote:
>>>>
[snip]
>>>>>Can it be something else? I'm really a bit lost.
>>>>>
>>>>
>>>> The pin/node count matches. Comment out the "OPTIONAL:" line and see
>>>> what happens.
>>>>
>>>
>>>It appears that it is necessary to include the whole Orcad mix_misc
>>>library, plus other libraries which mix_misc references.
>>>
>>>I don't like libraries that require other libraries. Stinks of
>>>programmers' methods. Change one thing and break lots of others.
>>>
>>>Also, the Orcad libraries include syntax that LTSpice doesn't understand.
>>>
>>>Major rewrite necessary.
>>
>> OrCAD (and PSpice, for that matter) can utilize global power and
>> ground nodes as a means to keeping schematics from becoming a jungle
>> of wires.
>>
>> You _could_ learn to make your own libraries (I do ;-)
>>
>
>I already do. I don't have any use for a CD4046 model, I was just
>investigating the OP's problem to see if I could offer anything
>constructive.
>
>PSpice models usually just work in LTSpice. Some of the Orcad stuff seems
>a bit byzantine.
"Byzantine"?
Thumbing back thru my LTspice "digests" E-mails I see the very same
digital notation. Apparently LTspice lacks the full complement of
74HC... libraries, so you have to do some rolling of your own.
PSpice (OrCAD) has mixed-signal capabilities... digital is primarily
behavioral (for speed of simulation) plus regular analog stuff. You
have to know what you are doing to mix it together and still retain
speed.
Take a look at my D2A (digital-world-to-analog-world) interface. I
did that to keep digital screaming along as a digital simulation, then
make a single translation to analog.
Jim Thompson
I missed your next-to-last paragraph. With enough flattery I could
probably be cajoled into writing a CD4046 that's a generic
(behavioral) Spice model ;-)
Jim Thompson
<excret...@invalid.invalid> wrote:
>On Fri, 08 Oct 2010 13:46:40 -0700, Jim Thompson wrote:
>
>> I missed your next-to-last paragraph. With enough flattery I could
>> probably be cajoled into writing a CD4046 that's a generic
>> (behavioral) Spice model ;-)
>
>That's what I'd do. I like behavioral models. However it isn't me that
>wants one, it's volkerk. I don't know whether his flattery skills are
>sufficiently honed ;-)
>
>Byzantine: characterized by elaborate scheming and intrigue, esp. for the
>gaining of political power or favor. (Dictionary.com)
I'm not a programmer, but my understanding is that the PSpice digital
behavioral models are based on "C" code. Charlie?
tm
"Jim Thompson" <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
message news:rj0va614o71k91m1r...@4ax.com...
>
> I missed your next-to-last paragraph. With enough flattery I could
> probably be cajoled into writing a CD4046 that's a generic
> (behavioral) Spice model ;-)
>
> ...Jim Thompson
Yer an ugly old coot and I don't think you can do it!
How's that for cajoling? :)
tm
PS, I like your sig.
Charlie E.
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Fri, 08 Oct 2010 14:16:09 -0700, Fred Abse
><excret...@invalid.invalid> wrote:
>
>>On Fri, 08 Oct 2010 13:46:40 -0700, Jim Thompson wrote:
>>
>>> I missed your next-to-last paragraph. With enough flattery I could
>>> probably be cajoled into writing a CD4046 that's a generic
>>> (behavioral) Spice model ;-)
>>
>>That's what I'd do. I like behavioral models. However it isn't me that
>>wants one, it's volkerk. I don't know whether his flattery skills are
>>sufficiently honed ;-)
>>
>>Byzantine: characterized by elaborate scheming and intrigue, esp. for the
>>gaining of political power or favor. (Dictionary.com)
>
>I'm not a programmer, but my understanding is that the PSpice digital
>behavioral models are based on "C" code. Charlie?
>
> ...Jim Thompson
Actually, it is probably more complicated than that, and simpler. I
know that the the time step processes gave them fits, especially for
fast transitions, but that when they were done they were pretty happy
about it. But, basically, they did actually digital logic, and then
wrapped an AtoD and DtoA around it. When they did PLSyn for
programmable logic, like Xilinx FPGAs, they used the logic expressions
provided for the PLA and the timing expressions, and then did the A-D
translations at the borders. The PSpiceHDL tool would have used
NC-SIM as the VHDL or Verilog simulator, with the same types of
translations, including IBIS models. However, that would have sold in
the $20K range, and been a valid replacement for $200K tools, so they
just eliminated the entire development team...
Charlie
Helmut Sennewald
I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.
http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046
Best regards,
Helmut
"volkerk" <volkerkible@n_o_s_p_a_m.n_o_s_p_a_m.gmx.net> schrieb im
Newsbeitrag news:65adncxqVvmzXzDR...@giganews.com...
Jim Thompson
<helmuts...@t-online.de> wrote:
>Hello,
>
>I have written sometimes ago a CD4046 model for LTspice.
>You can download it from the LTspice Yahoo group.
>
>http://tech.groups.yahoo.com/group/LTspice/
>Files > Lib > CD4046
>
>Best regards,
>Helmut
>
[snip]
Hi Helmut,
Thanks for a clean hierarchical schematic!
Amusing myself with how to make a full behavioral model...
Do you have any ideas on how to characterize a CMOS inverter?
I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.
Muzaffer Kal
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>Do you have any ideas on how to characterize a CMOS inverter?
One usually uses input transition rate and output load as parameters
to characterize the behavior of an inverter (or any other gate) ie you
make tables of delays which give you output delay and transition given
input transition and output load (usually only in terms of
capacitance) for a specific corner of pvt.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
Jim Thompson
wrote:
>On Sun, 10 Oct 2010 10:25:34 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>Do you have any ideas on how to characterize a CMOS inverter?
>
>One usually uses input transition rate and output load as parameters
>to characterize the behavior of an inverter (or any other gate) ie you
>make tables of delays which give you output delay and transition given
>input transition and output load (usually only in terms of
>capacitance) for a specific corner of pvt.
I'm interested in making a voltage-controlled resistor which matches
that of a CMOS transistor. I'm guessing a SINH function might be a
good start.
That'll be the easy part. The hard part will be getting input and
output capacitances as a function of input AND output voltages.
Tables won't improve simulation time that much. Though they certainly
can model parts that are difficult to fit with _smooth_ equations.
Take a look at the varicap models on my website.
Helmut Sennewald
"Jim Thompson" <To-Email-Use-Th...@On-My-Web-Site.com> schrieb
im Newsbeitrag news:lus3b69srmui4h3mk...@4ax.com...
Hello Jim,
I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.
Best regards,
Helmut
Jim Thompson
<helmuts...@t-online.de> wrote:
Hi Helmut,
I wasn't thinking transistor-level, just a behavioral equivalent that
avoided special digital structures... make an inverter from G-sources
and a capacitor or two.
That led me to thinking that an NMOS device is just a two-variable
G-source (VGS and VDS) with a TANH equation...
Then one could make up their own accurate digital library using analog
behavioral components :-)
Joerg
Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.
Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.
--
Regards, Joerg
http://www.analogconsultants.com/
"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
Jim Thompson
wrote:
Subscribe to the E-mailed "digests". I do. I go thru the Yahoo
interface so rarely I have trouble remembering my password ;-)
Of course I still predominately use PSpice, but the group is just
stock-full of great ideas, and pro-level posters... Helmut and
Woodgate... yep _our_ Woodgate.
Joerg
Can you post via that?
> Of course I still predominately use PSpice, but the group is just
> stock-full of great ideas, and pro-level posters... Helmut and
> Woodgate... yep _our_ Woodgate.
>
Yes, that is very true. The icing on the cake would be if Mike
Engelhardt would stick his head in there once in a while.
Jim Thompson
wrote:
I think so. I've certainly "Replied to group" with suggestions of
solutions to problems.
>
>
>> Of course I still predominately use PSpice, but the group is just
>> stock-full of great ideas, and pro-level posters... Helmut and
>> Woodgate... yep _our_ Woodgate.
>>
>
>Yes, that is very true. The icing on the cake would be if Mike
>Engelhardt would stick his head in there once in a while.
I've not seen Mike post there. That doesn't mean he hasn't.
Joerg
That would be cool. But first I have to find out why it won't let me in
anymore, else I won't be able to set anything.
[...]
Michael A. Terrell
Too many PHTTTTTTTTTTTTs.
--
Politicians should only get paid if the budget is balanced, and there is
enough left over to pay them.
Jim Thompson
wrote:
Helmut is (I think) the moderator... ask him.
Helmut Sennewald
"Joerg" <inv...@invalid.invalid> schrieb im Newsbeitrag
news:8hetar...@mid.individual.net...
Hello Joerg,
"Join now" only menas you have to login with your password.
This happens after a every few weeks for safety reason.
Somebody from Yahoo had this bad idea to name this "Join now" instead of
"Login".
Type in your login and password.
In the next window, directly go to Messages.
Best regards,
Helmut
Helmut Sennewald
"Jim Thompson" <To-Email-Use-Th...@On-My-Web-Site.com> schrieb
im Newsbeitrag news:1je4b691vi00td2l9...@4ax.com...
Hello Jim,
A simulation with digital devices is much faster than the same with analog
devices.
Best regards,
Helmut
Joerg
Thanks, Helmut, but it doesn't work anymore. After entering name and
password a 2nd time it pops over to regular Yahoo. Wants all that a 3rd
time but won't take it. Plus it moans and groans about cookies before
that and then sets ad cookies.
IMHO they have royally screwed up this time. Can't you open the LTSpice
group to gmane like the other tech groups? Then all this script kiddie
nonsense is gone and people can use it like a real newsgroup. Without
the file section, of course, for that one would have to wade through the
morass (or try ...).
--
Regards, Joerg
Jim Thompson
<helmuts...@t-online.de> wrote:
Of course, but how many people have, or can cope with, digital
primitives ?:-)
And TANH is determinate... not exactly an analog component.
Jim Thompson
<excret...@invalid.invalid> wrote:
>On Sun, 10 Oct 2010 16:59:28 -0700, Joerg wrote:
>
>> That would be cool. But first I have to find out why it won't let me in
>> anymore, else I won't be able to set anything.
>
>I've tried to register several times. Each time it's failed with various
>messages about cookies (enabled) Javascript (enabled), or just plain not
>responding. Eventually, I gave up. A plague on its house!
>
>BTW have you noticed the fine print? "Yahoo collects personal data".
The only thing true I feed such sites is an E-mail address. And
that's not a problem, I currently have 260 different E-mail addresses
:-) Anyone who abuses an E-mail address... it's gone.
Joerg
> On Sun, 10 Oct 2010 16:59:28 -0700, Joerg wrote:
>
>> anymore, else I won't be able to set anything.
>
> messages about cookies (enabled) Javascript (enabled), or just plain not
> responding. Eventually, I gave up. A plague on its house!
>
> BTW have you noticed the fine print? "Yahoo collects personal data".
>
Now you know the reason why I declined the "upgrade" to Yahoo mail from
SBC or now AT&T, which at least to me looks like a cheap outsourcing
attempt.
Jim Thompson
The datasheets are crocks... can't work as shown. But the general
scheme implies that someone did a copy attempt of my vintage (mid
'60's) MC4024 core (which was actually current mode).
If someone has a working unit, take a snapshot of the voltage across
the VCO capacitor.
Thanks!
Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>Does anyone have a transistor-level schematic of the CD4046 VCO?
>
>The datasheets are crocks... can't work as shown. But the general
>scheme implies that someone did a copy attempt of my vintage (mid
>'60's) MC4024 core (which was actually current mode).
>
>If someone has a working unit, take a snapshot of the voltage across
>the VCO capacitor.
>
>Thanks!
>
> ...Jim Thompson
Like as shown in...
Newsgroups: alt.binaries.schematics.electronic
Subject: LTspice subckt model for CD4046 (SED) - VCOala4046.pdf
Date: Thu, 14 Oct 2010 11:56:33 -0700
Message-ID: <hekeb6dqpm3dh73a7...@4ax.com>